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#include "i915_drm.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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#include "intel_drv.h"
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#define DRM_WAKEUP( queue ) wake_up( queue )
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#define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue )
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#define MAX_NOPID ((u32)~0)
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#define MAX_NOPID ((u32)~0)
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/**
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/**
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        dev_priv->irq_mask |= mask;
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        dev_priv->irq_mask |= mask;
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        I915_WRITE(DEIMR, dev_priv->irq_mask);
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        I915_WRITE(DEIMR, dev_priv->irq_mask);
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        POSTING_READ(DEIMR);
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        POSTING_READ(DEIMR);
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    }
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    }
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}
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}
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static void notify_ring(struct drm_device *dev,
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			struct intel_ring_buffer *ring)
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{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	u32 seqno;
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	if (ring->obj == NULL)
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		return;
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	seqno = ring->get_seqno(ring);
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	trace_i915_gem_request_complete(ring, seqno);
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	ring->irq_seqno = seqno;
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	wake_up_all(&ring->irq_queue);
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//   if (i915_enable_hangcheck) {
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//       dev_priv->hangcheck_count = 0;
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//       mod_timer(&dev_priv->hangcheck_timer,
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//             jiffies +
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//             msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
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//   }
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}
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        hotplug_mask = SDE_HOTPLUG_MASK;
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        hotplug_mask = SDE_HOTPLUG_MASK;
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    ret = IRQ_HANDLED;
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    ret = IRQ_HANDLED;
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//    if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
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    if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
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//        notify_ring(dev, &dev_priv->ring[RCS]);
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        notify_ring(dev, &dev_priv->ring[RCS]);
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//    if (gt_iir & bsd_usr_interrupt)
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    if (gt_iir & bsd_usr_interrupt)
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//        notify_ring(dev, &dev_priv->ring[VCS]);
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        notify_ring(dev, &dev_priv->ring[VCS]);
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//    if (gt_iir & GT_BLT_USER_INTERRUPT)
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    if (gt_iir & GT_BLT_USER_INTERRUPT)
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//        notify_ring(dev, &dev_priv->ring[BCS]);
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        notify_ring(dev, &dev_priv->ring[BCS]);
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    u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
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    u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
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               DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
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               DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
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    u32 render_irqs;
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    u32 render_irqs;
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    u32 hotplug_mask;
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    u32 hotplug_mask;
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//    DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
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    DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
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//    if (HAS_BSD(dev))
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    if (HAS_BSD(dev))
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//        DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
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        DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
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//    if (HAS_BLT(dev))
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    if (HAS_BLT(dev))
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//        DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
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        DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
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    dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
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    dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;