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1 | /* |
1 | /* |
2 | * Copyright © 2014 Intel Corporation |
2 | * Copyright © 2014 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
21 | * IN THE SOFTWARE. |
21 | * IN THE SOFTWARE. |
22 | * |
22 | * |
23 | */ |
23 | */ |
24 | #include |
24 | #include |
25 | #include |
25 | #include |
26 | #include "i915_drv.h" |
26 | #include "i915_drv.h" |
27 | #include "intel_guc.h" |
27 | #include "intel_guc.h" |
28 | 28 | ||
29 | /** |
29 | /** |
30 | * DOC: GuC-based command submission |
30 | * DOC: GuC-based command submission |
31 | * |
31 | * |
32 | * i915_guc_client: |
32 | * i915_guc_client: |
33 | * We use the term client to avoid confusion with contexts. A i915_guc_client is |
33 | * We use the term client to avoid confusion with contexts. A i915_guc_client is |
34 | * equivalent to GuC object guc_context_desc. This context descriptor is |
34 | * equivalent to GuC object guc_context_desc. This context descriptor is |
35 | * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell |
35 | * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell |
36 | * and workqueue for it. Also the process descriptor (guc_process_desc), which |
36 | * and workqueue for it. Also the process descriptor (guc_process_desc), which |
37 | * is mapped to client space. So the client can write Work Item then ring the |
37 | * is mapped to client space. So the client can write Work Item then ring the |
38 | * doorbell. |
38 | * doorbell. |
39 | * |
39 | * |
40 | * To simplify the implementation, we allocate one gem object that contains all |
40 | * To simplify the implementation, we allocate one gem object that contains all |
41 | * pages for doorbell, process descriptor and workqueue. |
41 | * pages for doorbell, process descriptor and workqueue. |
42 | * |
42 | * |
43 | * The Scratch registers: |
43 | * The Scratch registers: |
44 | * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes |
44 | * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes |
45 | * a value to the action register (SOFT_SCRATCH_0) along with any data. It then |
45 | * a value to the action register (SOFT_SCRATCH_0) along with any data. It then |
46 | * triggers an interrupt on the GuC via another register write (0xC4C8). |
46 | * triggers an interrupt on the GuC via another register write (0xC4C8). |
47 | * Firmware writes a success/fail code back to the action register after |
47 | * Firmware writes a success/fail code back to the action register after |
48 | * processes the request. The kernel driver polls waiting for this update and |
48 | * processes the request. The kernel driver polls waiting for this update and |
49 | * then proceeds. |
49 | * then proceeds. |
50 | * See host2guc_action() |
50 | * See host2guc_action() |
51 | * |
51 | * |
52 | * Doorbells: |
52 | * Doorbells: |
53 | * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW) |
53 | * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW) |
54 | * mapped into process space. |
54 | * mapped into process space. |
55 | * |
55 | * |
56 | * Work Items: |
56 | * Work Items: |
57 | * There are several types of work items that the host may place into a |
57 | * There are several types of work items that the host may place into a |
58 | * workqueue, each with its own requirements and limitations. Currently only |
58 | * workqueue, each with its own requirements and limitations. Currently only |
59 | * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which |
59 | * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which |
60 | * represents in-order queue. The kernel driver packs ring tail pointer and an |
60 | * represents in-order queue. The kernel driver packs ring tail pointer and an |
61 | * ELSP context descriptor dword into Work Item. |
61 | * ELSP context descriptor dword into Work Item. |
62 | * See guc_add_workqueue_item() |
62 | * See guc_add_workqueue_item() |
63 | * |
63 | * |
64 | */ |
64 | */ |
65 | 65 | ||
66 | /* |
66 | /* |
67 | * Read GuC command/status register (SOFT_SCRATCH_0) |
67 | * Read GuC command/status register (SOFT_SCRATCH_0) |
68 | * Return true if it contains a response rather than a command |
68 | * Return true if it contains a response rather than a command |
69 | */ |
69 | */ |
70 | static inline bool host2guc_action_response(struct drm_i915_private *dev_priv, |
70 | static inline bool host2guc_action_response(struct drm_i915_private *dev_priv, |
71 | u32 *status) |
71 | u32 *status) |
72 | { |
72 | { |
73 | u32 val = I915_READ(SOFT_SCRATCH(0)); |
73 | u32 val = I915_READ(SOFT_SCRATCH(0)); |
74 | *status = val; |
74 | *status = val; |
75 | return GUC2HOST_IS_RESPONSE(val); |
75 | return GUC2HOST_IS_RESPONSE(val); |
76 | } |
76 | } |
77 | 77 | ||
78 | static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len) |
78 | static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len) |
79 | { |
79 | { |
80 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
80 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
81 | u32 status; |
81 | u32 status; |
82 | int i; |
82 | int i; |
83 | int ret; |
83 | int ret; |
84 | 84 | ||
85 | if (WARN_ON(len < 1 || len > 15)) |
85 | if (WARN_ON(len < 1 || len > 15)) |
86 | return -EINVAL; |
86 | return -EINVAL; |
87 | 87 | ||
88 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
88 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
89 | 89 | ||
90 | dev_priv->guc.action_count += 1; |
90 | dev_priv->guc.action_count += 1; |
91 | dev_priv->guc.action_cmd = data[0]; |
91 | dev_priv->guc.action_cmd = data[0]; |
92 | 92 | ||
93 | for (i = 0; i < len; i++) |
93 | for (i = 0; i < len; i++) |
94 | I915_WRITE(SOFT_SCRATCH(i), data[i]); |
94 | I915_WRITE(SOFT_SCRATCH(i), data[i]); |
95 | 95 | ||
96 | POSTING_READ(SOFT_SCRATCH(i - 1)); |
96 | POSTING_READ(SOFT_SCRATCH(i - 1)); |
97 | 97 | ||
98 | I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER); |
98 | I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER); |
99 | 99 | ||
100 | /* No HOST2GUC command should take longer than 10ms */ |
100 | /* No HOST2GUC command should take longer than 10ms */ |
101 | ret = wait_for_atomic(host2guc_action_response(dev_priv, &status), 10); |
101 | ret = wait_for_atomic(host2guc_action_response(dev_priv, &status), 10); |
102 | if (status != GUC2HOST_STATUS_SUCCESS) { |
102 | if (status != GUC2HOST_STATUS_SUCCESS) { |
103 | /* |
103 | /* |
104 | * Either the GuC explicitly returned an error (which |
104 | * Either the GuC explicitly returned an error (which |
105 | * we convert to -EIO here) or no response at all was |
105 | * we convert to -EIO here) or no response at all was |
106 | * received within the timeout limit (-ETIMEDOUT) |
106 | * received within the timeout limit (-ETIMEDOUT) |
107 | */ |
107 | */ |
108 | if (ret != -ETIMEDOUT) |
108 | if (ret != -ETIMEDOUT) |
109 | ret = -EIO; |
109 | ret = -EIO; |
110 | 110 | ||
111 | DRM_ERROR("GUC: host2guc action 0x%X failed. ret=%d " |
111 | DRM_ERROR("GUC: host2guc action 0x%X failed. ret=%d " |
112 | "status=0x%08X response=0x%08X\n", |
112 | "status=0x%08X response=0x%08X\n", |
113 | data[0], ret, status, |
113 | data[0], ret, status, |
114 | I915_READ(SOFT_SCRATCH(15))); |
114 | I915_READ(SOFT_SCRATCH(15))); |
115 | 115 | ||
116 | dev_priv->guc.action_fail += 1; |
116 | dev_priv->guc.action_fail += 1; |
117 | dev_priv->guc.action_err = ret; |
117 | dev_priv->guc.action_err = ret; |
118 | } |
118 | } |
119 | dev_priv->guc.action_status = status; |
119 | dev_priv->guc.action_status = status; |
120 | 120 | ||
121 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
121 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
122 | 122 | ||
123 | return ret; |
123 | return ret; |
124 | } |
124 | } |
125 | 125 | ||
126 | /* |
126 | /* |
127 | * Tell the GuC to allocate or deallocate a specific doorbell |
127 | * Tell the GuC to allocate or deallocate a specific doorbell |
128 | */ |
128 | */ |
129 | 129 | ||
130 | static int host2guc_allocate_doorbell(struct intel_guc *guc, |
130 | static int host2guc_allocate_doorbell(struct intel_guc *guc, |
131 | struct i915_guc_client *client) |
131 | struct i915_guc_client *client) |
132 | { |
132 | { |
133 | u32 data[2]; |
133 | u32 data[2]; |
134 | 134 | ||
135 | data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL; |
135 | data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL; |
136 | data[1] = client->ctx_index; |
136 | data[1] = client->ctx_index; |
137 | 137 | ||
138 | return host2guc_action(guc, data, 2); |
138 | return host2guc_action(guc, data, 2); |
139 | } |
139 | } |
140 | 140 | ||
141 | static int host2guc_release_doorbell(struct intel_guc *guc, |
141 | static int host2guc_release_doorbell(struct intel_guc *guc, |
142 | struct i915_guc_client *client) |
142 | struct i915_guc_client *client) |
143 | { |
143 | { |
144 | u32 data[2]; |
144 | u32 data[2]; |
145 | 145 | ||
146 | data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL; |
146 | data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL; |
147 | data[1] = client->ctx_index; |
147 | data[1] = client->ctx_index; |
148 | 148 | ||
149 | return host2guc_action(guc, data, 2); |
149 | return host2guc_action(guc, data, 2); |
150 | } |
150 | } |
151 | 151 | ||
152 | static int host2guc_sample_forcewake(struct intel_guc *guc, |
152 | static int host2guc_sample_forcewake(struct intel_guc *guc, |
153 | struct i915_guc_client *client) |
153 | struct i915_guc_client *client) |
154 | { |
154 | { |
155 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
155 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
156 | struct drm_device *dev = dev_priv->dev; |
156 | struct drm_device *dev = dev_priv->dev; |
157 | u32 data[2]; |
157 | u32 data[2]; |
158 | 158 | ||
159 | data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; |
159 | data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; |
160 | /* WaRsDisableCoarsePowerGating:skl,bxt */ |
160 | /* WaRsDisableCoarsePowerGating:skl,bxt */ |
161 | if (!intel_enable_rc6(dev_priv->dev) || |
161 | if (!intel_enable_rc6(dev) || |
162 | IS_BXT_REVID(dev, 0, BXT_REVID_A1) || |
162 | NEEDS_WaRsDisableCoarsePowerGating(dev)) |
163 | (IS_SKL_GT3(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0)) || |
- | |
164 | (IS_SKL_GT4(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0))) |
- | |
165 | data[1] = 0; |
163 | data[1] = 0; |
166 | else |
164 | else |
167 | /* bit 0 and 1 are for Render and Media domain separately */ |
165 | /* bit 0 and 1 are for Render and Media domain separately */ |
168 | data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA; |
166 | data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA; |
169 | 167 | ||
170 | return host2guc_action(guc, data, ARRAY_SIZE(data)); |
168 | return host2guc_action(guc, data, ARRAY_SIZE(data)); |
171 | } |
169 | } |
172 | 170 | ||
173 | /* |
171 | /* |
174 | * Initialise, update, or clear doorbell data shared with the GuC |
172 | * Initialise, update, or clear doorbell data shared with the GuC |
175 | * |
173 | * |
176 | * These functions modify shared data and so need access to the mapped |
174 | * These functions modify shared data and so need access to the mapped |
177 | * client object which contains the page being used for the doorbell |
175 | * client object which contains the page being used for the doorbell |
178 | */ |
176 | */ |
179 | 177 | ||
180 | static void guc_init_doorbell(struct intel_guc *guc, |
178 | static void guc_init_doorbell(struct intel_guc *guc, |
181 | struct i915_guc_client *client) |
179 | struct i915_guc_client *client) |
182 | { |
180 | { |
183 | struct guc_doorbell_info *doorbell; |
181 | struct guc_doorbell_info *doorbell; |
184 | void *base; |
182 | void *base; |
185 | 183 | ||
186 | base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); |
184 | base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); |
187 | doorbell = base + client->doorbell_offset; |
185 | doorbell = base + client->doorbell_offset; |
188 | 186 | ||
189 | doorbell->db_status = 1; |
187 | doorbell->db_status = 1; |
190 | doorbell->cookie = 0; |
188 | doorbell->cookie = 0; |
191 | 189 | ||
192 | kunmap_atomic(base); |
190 | kunmap_atomic(base); |
193 | } |
191 | } |
194 | 192 | ||
195 | static int guc_ring_doorbell(struct i915_guc_client *gc) |
193 | static int guc_ring_doorbell(struct i915_guc_client *gc) |
196 | { |
194 | { |
197 | struct guc_process_desc *desc; |
195 | struct guc_process_desc *desc; |
198 | union guc_doorbell_qw db_cmp, db_exc, db_ret; |
196 | union guc_doorbell_qw db_cmp, db_exc, db_ret; |
199 | union guc_doorbell_qw *db; |
197 | union guc_doorbell_qw *db; |
200 | void *base; |
198 | void *base; |
201 | int attempt = 2, ret = -EAGAIN; |
199 | int attempt = 2, ret = -EAGAIN; |
202 | 200 | ||
203 | base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0)); |
201 | base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0)); |
204 | desc = base + gc->proc_desc_offset; |
202 | desc = base + gc->proc_desc_offset; |
205 | 203 | ||
206 | /* Update the tail so it is visible to GuC */ |
204 | /* Update the tail so it is visible to GuC */ |
207 | desc->tail = gc->wq_tail; |
205 | desc->tail = gc->wq_tail; |
208 | 206 | ||
209 | /* current cookie */ |
207 | /* current cookie */ |
210 | db_cmp.db_status = GUC_DOORBELL_ENABLED; |
208 | db_cmp.db_status = GUC_DOORBELL_ENABLED; |
211 | db_cmp.cookie = gc->cookie; |
209 | db_cmp.cookie = gc->cookie; |
212 | 210 | ||
213 | /* cookie to be updated */ |
211 | /* cookie to be updated */ |
214 | db_exc.db_status = GUC_DOORBELL_ENABLED; |
212 | db_exc.db_status = GUC_DOORBELL_ENABLED; |
215 | db_exc.cookie = gc->cookie + 1; |
213 | db_exc.cookie = gc->cookie + 1; |
216 | if (db_exc.cookie == 0) |
214 | if (db_exc.cookie == 0) |
217 | db_exc.cookie = 1; |
215 | db_exc.cookie = 1; |
218 | 216 | ||
219 | /* pointer of current doorbell cacheline */ |
217 | /* pointer of current doorbell cacheline */ |
220 | db = base + gc->doorbell_offset; |
218 | db = base + gc->doorbell_offset; |
221 | 219 | ||
222 | while (attempt--) { |
220 | while (attempt--) { |
223 | /* lets ring the doorbell */ |
221 | /* lets ring the doorbell */ |
224 | db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db, |
222 | db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db, |
225 | db_cmp.value_qw, db_exc.value_qw); |
223 | db_cmp.value_qw, db_exc.value_qw); |
226 | 224 | ||
227 | /* if the exchange was successfully executed */ |
225 | /* if the exchange was successfully executed */ |
228 | if (db_ret.value_qw == db_cmp.value_qw) { |
226 | if (db_ret.value_qw == db_cmp.value_qw) { |
229 | /* db was successfully rung */ |
227 | /* db was successfully rung */ |
230 | gc->cookie = db_exc.cookie; |
228 | gc->cookie = db_exc.cookie; |
231 | ret = 0; |
229 | ret = 0; |
232 | break; |
230 | break; |
233 | } |
231 | } |
234 | 232 | ||
235 | /* XXX: doorbell was lost and need to acquire it again */ |
233 | /* XXX: doorbell was lost and need to acquire it again */ |
236 | if (db_ret.db_status == GUC_DOORBELL_DISABLED) |
234 | if (db_ret.db_status == GUC_DOORBELL_DISABLED) |
237 | break; |
235 | break; |
238 | 236 | ||
239 | DRM_ERROR("Cookie mismatch. Expected %d, returned %d\n", |
237 | DRM_ERROR("Cookie mismatch. Expected %d, returned %d\n", |
240 | db_cmp.cookie, db_ret.cookie); |
238 | db_cmp.cookie, db_ret.cookie); |
241 | 239 | ||
242 | /* update the cookie to newly read cookie from GuC */ |
240 | /* update the cookie to newly read cookie from GuC */ |
243 | db_cmp.cookie = db_ret.cookie; |
241 | db_cmp.cookie = db_ret.cookie; |
244 | db_exc.cookie = db_ret.cookie + 1; |
242 | db_exc.cookie = db_ret.cookie + 1; |
245 | if (db_exc.cookie == 0) |
243 | if (db_exc.cookie == 0) |
246 | db_exc.cookie = 1; |
244 | db_exc.cookie = 1; |
247 | } |
245 | } |
- | 246 | ||
- | 247 | /* Finally, update the cached copy of the GuC's WQ head */ |
|
- | 248 | gc->wq_head = desc->head; |
|
248 | 249 | ||
249 | kunmap_atomic(base); |
250 | kunmap_atomic(base); |
250 | return ret; |
251 | return ret; |
251 | } |
252 | } |
252 | 253 | ||
253 | static void guc_disable_doorbell(struct intel_guc *guc, |
254 | static void guc_disable_doorbell(struct intel_guc *guc, |
254 | struct i915_guc_client *client) |
255 | struct i915_guc_client *client) |
255 | { |
256 | { |
256 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
257 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
257 | struct guc_doorbell_info *doorbell; |
258 | struct guc_doorbell_info *doorbell; |
258 | void *base; |
259 | void *base; |
259 | i915_reg_t drbreg = GEN8_DRBREGL(client->doorbell_id); |
260 | i915_reg_t drbreg = GEN8_DRBREGL(client->doorbell_id); |
260 | int value; |
261 | int value; |
261 | 262 | ||
262 | base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); |
263 | base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); |
263 | doorbell = base + client->doorbell_offset; |
264 | doorbell = base + client->doorbell_offset; |
264 | 265 | ||
265 | doorbell->db_status = 0; |
266 | doorbell->db_status = 0; |
266 | 267 | ||
267 | kunmap_atomic(base); |
268 | kunmap_atomic(base); |
268 | 269 | ||
269 | I915_WRITE(drbreg, I915_READ(drbreg) & ~GEN8_DRB_VALID); |
270 | I915_WRITE(drbreg, I915_READ(drbreg) & ~GEN8_DRB_VALID); |
270 | 271 | ||
271 | value = I915_READ(drbreg); |
272 | value = I915_READ(drbreg); |
272 | WARN_ON((value & GEN8_DRB_VALID) != 0); |
273 | WARN_ON((value & GEN8_DRB_VALID) != 0); |
273 | 274 | ||
274 | I915_WRITE(GEN8_DRBREGU(client->doorbell_id), 0); |
275 | I915_WRITE(GEN8_DRBREGU(client->doorbell_id), 0); |
275 | I915_WRITE(drbreg, 0); |
276 | I915_WRITE(drbreg, 0); |
276 | 277 | ||
277 | /* XXX: wait for any interrupts */ |
278 | /* XXX: wait for any interrupts */ |
278 | /* XXX: wait for workqueue to drain */ |
279 | /* XXX: wait for workqueue to drain */ |
279 | } |
280 | } |
280 | 281 | ||
281 | /* |
282 | /* |
282 | * Select, assign and relase doorbell cachelines |
283 | * Select, assign and relase doorbell cachelines |
283 | * |
284 | * |
284 | * These functions track which doorbell cachelines are in use. |
285 | * These functions track which doorbell cachelines are in use. |
285 | * The data they manipulate is protected by the host2guc lock. |
286 | * The data they manipulate is protected by the host2guc lock. |
286 | */ |
287 | */ |
287 | 288 | ||
288 | static uint32_t select_doorbell_cacheline(struct intel_guc *guc) |
289 | static uint32_t select_doorbell_cacheline(struct intel_guc *guc) |
289 | { |
290 | { |
290 | const uint32_t cacheline_size = cache_line_size(); |
291 | const uint32_t cacheline_size = cache_line_size(); |
291 | uint32_t offset; |
292 | uint32_t offset; |
292 | 293 | ||
293 | /* Doorbell uses a single cache line within a page */ |
294 | /* Doorbell uses a single cache line within a page */ |
294 | offset = offset_in_page(guc->db_cacheline); |
295 | offset = offset_in_page(guc->db_cacheline); |
295 | 296 | ||
296 | /* Moving to next cache line to reduce contention */ |
297 | /* Moving to next cache line to reduce contention */ |
297 | guc->db_cacheline += cacheline_size; |
298 | guc->db_cacheline += cacheline_size; |
298 | 299 | ||
299 | DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n", |
300 | DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n", |
300 | offset, guc->db_cacheline, cacheline_size); |
301 | offset, guc->db_cacheline, cacheline_size); |
301 | 302 | ||
302 | return offset; |
303 | return offset; |
303 | } |
304 | } |
304 | 305 | ||
305 | static uint16_t assign_doorbell(struct intel_guc *guc, uint32_t priority) |
306 | static uint16_t assign_doorbell(struct intel_guc *guc, uint32_t priority) |
306 | { |
307 | { |
307 | /* |
308 | /* |
308 | * The bitmap is split into two halves; the first half is used for |
309 | * The bitmap is split into two halves; the first half is used for |
309 | * normal priority contexts, the second half for high-priority ones. |
310 | * normal priority contexts, the second half for high-priority ones. |
310 | * Note that logically higher priorities are numerically less than |
311 | * Note that logically higher priorities are numerically less than |
311 | * normal ones, so the test below means "is it high-priority?" |
312 | * normal ones, so the test below means "is it high-priority?" |
312 | */ |
313 | */ |
313 | const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH); |
314 | const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH); |
314 | const uint16_t half = GUC_MAX_DOORBELLS / 2; |
315 | const uint16_t half = GUC_MAX_DOORBELLS / 2; |
315 | const uint16_t start = hi_pri ? half : 0; |
316 | const uint16_t start = hi_pri ? half : 0; |
316 | const uint16_t end = start + half; |
317 | const uint16_t end = start + half; |
317 | uint16_t id; |
318 | uint16_t id; |
318 | 319 | ||
319 | id = find_next_zero_bit(guc->doorbell_bitmap, end, start); |
320 | id = find_next_zero_bit(guc->doorbell_bitmap, end, start); |
320 | if (id == end) |
321 | if (id == end) |
321 | id = GUC_INVALID_DOORBELL_ID; |
322 | id = GUC_INVALID_DOORBELL_ID; |
322 | else |
323 | else |
323 | bitmap_set(guc->doorbell_bitmap, id, 1); |
324 | bitmap_set(guc->doorbell_bitmap, id, 1); |
324 | 325 | ||
325 | DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n", |
326 | DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n", |
326 | hi_pri ? "high" : "normal", id); |
327 | hi_pri ? "high" : "normal", id); |
327 | 328 | ||
328 | return id; |
329 | return id; |
329 | } |
330 | } |
330 | 331 | ||
331 | static void release_doorbell(struct intel_guc *guc, uint16_t id) |
332 | static void release_doorbell(struct intel_guc *guc, uint16_t id) |
332 | { |
333 | { |
333 | bitmap_clear(guc->doorbell_bitmap, id, 1); |
334 | bitmap_clear(guc->doorbell_bitmap, id, 1); |
334 | } |
335 | } |
335 | 336 | ||
336 | /* |
337 | /* |
337 | * Initialise the process descriptor shared with the GuC firmware. |
338 | * Initialise the process descriptor shared with the GuC firmware. |
338 | */ |
339 | */ |
339 | static void guc_init_proc_desc(struct intel_guc *guc, |
340 | static void guc_init_proc_desc(struct intel_guc *guc, |
340 | struct i915_guc_client *client) |
341 | struct i915_guc_client *client) |
341 | { |
342 | { |
342 | struct guc_process_desc *desc; |
343 | struct guc_process_desc *desc; |
343 | void *base; |
344 | void *base; |
344 | 345 | ||
345 | base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); |
346 | base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); |
346 | desc = base + client->proc_desc_offset; |
347 | desc = base + client->proc_desc_offset; |
347 | 348 | ||
348 | memset(desc, 0, sizeof(*desc)); |
349 | memset(desc, 0, sizeof(*desc)); |
349 | 350 | ||
350 | /* |
351 | /* |
351 | * XXX: pDoorbell and WQVBaseAddress are pointers in process address |
352 | * XXX: pDoorbell and WQVBaseAddress are pointers in process address |
352 | * space for ring3 clients (set them as in mmap_ioctl) or kernel |
353 | * space for ring3 clients (set them as in mmap_ioctl) or kernel |
353 | * space for kernel clients (map on demand instead? May make debug |
354 | * space for kernel clients (map on demand instead? May make debug |
354 | * easier to have it mapped). |
355 | * easier to have it mapped). |
355 | */ |
356 | */ |
356 | desc->wq_base_addr = 0; |
357 | desc->wq_base_addr = 0; |
357 | desc->db_base_addr = 0; |
358 | desc->db_base_addr = 0; |
358 | 359 | ||
359 | desc->context_id = client->ctx_index; |
360 | desc->context_id = client->ctx_index; |
360 | desc->wq_size_bytes = client->wq_size; |
361 | desc->wq_size_bytes = client->wq_size; |
361 | desc->wq_status = WQ_STATUS_ACTIVE; |
362 | desc->wq_status = WQ_STATUS_ACTIVE; |
362 | desc->priority = client->priority; |
363 | desc->priority = client->priority; |
363 | 364 | ||
364 | kunmap_atomic(base); |
365 | kunmap_atomic(base); |
365 | } |
366 | } |
366 | 367 | ||
367 | /* |
368 | /* |
368 | * Initialise/clear the context descriptor shared with the GuC firmware. |
369 | * Initialise/clear the context descriptor shared with the GuC firmware. |
369 | * |
370 | * |
370 | * This descriptor tells the GuC where (in GGTT space) to find the important |
371 | * This descriptor tells the GuC where (in GGTT space) to find the important |
371 | * data structures relating to this client (doorbell, process descriptor, |
372 | * data structures relating to this client (doorbell, process descriptor, |
372 | * write queue, etc). |
373 | * write queue, etc). |
373 | */ |
374 | */ |
374 | 375 | ||
375 | static void guc_init_ctx_desc(struct intel_guc *guc, |
376 | static void guc_init_ctx_desc(struct intel_guc *guc, |
376 | struct i915_guc_client *client) |
377 | struct i915_guc_client *client) |
377 | { |
378 | { |
- | 379 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
|
- | 380 | struct intel_engine_cs *ring; |
|
378 | struct intel_context *ctx = client->owner; |
381 | struct intel_context *ctx = client->owner; |
379 | struct guc_context_desc desc; |
382 | struct guc_context_desc desc; |
380 | struct sg_table *sg; |
383 | struct sg_table *sg; |
381 | int i; |
384 | int i; |
382 | 385 | ||
383 | memset(&desc, 0, sizeof(desc)); |
386 | memset(&desc, 0, sizeof(desc)); |
384 | 387 | ||
385 | desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL; |
388 | desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL; |
386 | desc.context_id = client->ctx_index; |
389 | desc.context_id = client->ctx_index; |
387 | desc.priority = client->priority; |
390 | desc.priority = client->priority; |
388 | desc.db_id = client->doorbell_id; |
391 | desc.db_id = client->doorbell_id; |
389 | 392 | ||
390 | for (i = 0; i < I915_NUM_RINGS; i++) { |
393 | for_each_ring(ring, dev_priv, i) { |
391 | struct guc_execlist_context *lrc = &desc.lrc[i]; |
- | |
392 | struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf; |
- | |
393 | struct intel_engine_cs *ring; |
394 | struct guc_execlist_context *lrc = &desc.lrc[ring->guc_id]; |
394 | struct drm_i915_gem_object *obj; |
395 | struct drm_i915_gem_object *obj; |
395 | uint64_t ctx_desc; |
396 | uint64_t ctx_desc; |
396 | 397 | ||
397 | /* TODO: We have a design issue to be solved here. Only when we |
398 | /* TODO: We have a design issue to be solved here. Only when we |
398 | * receive the first batch, we know which engine is used by the |
399 | * receive the first batch, we know which engine is used by the |
399 | * user. But here GuC expects the lrc and ring to be pinned. It |
400 | * user. But here GuC expects the lrc and ring to be pinned. It |
400 | * is not an issue for default context, which is the only one |
401 | * is not an issue for default context, which is the only one |
401 | * for now who owns a GuC client. But for future owner of GuC |
402 | * for now who owns a GuC client. But for future owner of GuC |
402 | * client, need to make sure lrc is pinned prior to enter here. |
403 | * client, need to make sure lrc is pinned prior to enter here. |
403 | */ |
404 | */ |
404 | obj = ctx->engine[i].state; |
405 | obj = ctx->engine[i].state; |
405 | if (!obj) |
406 | if (!obj) |
406 | break; /* XXX: continue? */ |
407 | break; /* XXX: continue? */ |
407 | - | ||
408 | ring = ringbuf->ring; |
408 | |
409 | ctx_desc = intel_lr_context_descriptor(ctx, ring); |
409 | ctx_desc = intel_lr_context_descriptor(ctx, ring); |
410 | lrc->context_desc = (u32)ctx_desc; |
410 | lrc->context_desc = (u32)ctx_desc; |
411 | 411 | ||
412 | /* The state page is after PPHWSP */ |
412 | /* The state page is after PPHWSP */ |
413 | lrc->ring_lcra = i915_gem_obj_ggtt_offset(obj) + |
413 | lrc->ring_lcra = i915_gem_obj_ggtt_offset(obj) + |
414 | LRC_STATE_PN * PAGE_SIZE; |
414 | LRC_STATE_PN * PAGE_SIZE; |
415 | lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) | |
415 | lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) | |
416 | (ring->id << GUC_ELC_ENGINE_OFFSET); |
416 | (ring->guc_id << GUC_ELC_ENGINE_OFFSET); |
417 | 417 | ||
418 | obj = ringbuf->obj; |
418 | obj = ctx->engine[i].ringbuf->obj; |
419 | 419 | ||
420 | lrc->ring_begin = i915_gem_obj_ggtt_offset(obj); |
420 | lrc->ring_begin = i915_gem_obj_ggtt_offset(obj); |
421 | lrc->ring_end = lrc->ring_begin + obj->base.size - 1; |
421 | lrc->ring_end = lrc->ring_begin + obj->base.size - 1; |
422 | lrc->ring_next_free_location = lrc->ring_begin; |
422 | lrc->ring_next_free_location = lrc->ring_begin; |
423 | lrc->ring_current_tail_pointer_value = 0; |
423 | lrc->ring_current_tail_pointer_value = 0; |
424 | 424 | ||
425 | desc.engines_used |= (1 << ring->id); |
425 | desc.engines_used |= (1 << ring->guc_id); |
426 | } |
426 | } |
427 | 427 | ||
428 | WARN_ON(desc.engines_used == 0); |
428 | WARN_ON(desc.engines_used == 0); |
429 | 429 | ||
430 | /* |
430 | /* |
431 | * The CPU address is only needed at certain points, so kmap_atomic on |
431 | * The CPU address is only needed at certain points, so kmap_atomic on |
432 | * demand instead of storing it in the ctx descriptor. |
432 | * demand instead of storing it in the ctx descriptor. |
433 | * XXX: May make debug easier to have it mapped |
433 | * XXX: May make debug easier to have it mapped |
434 | */ |
434 | */ |
435 | desc.db_trigger_cpu = 0; |
435 | desc.db_trigger_cpu = 0; |
436 | desc.db_trigger_uk = client->doorbell_offset + |
436 | desc.db_trigger_uk = client->doorbell_offset + |
437 | i915_gem_obj_ggtt_offset(client->client_obj); |
437 | i915_gem_obj_ggtt_offset(client->client_obj); |
438 | desc.db_trigger_phy = client->doorbell_offset + |
438 | desc.db_trigger_phy = client->doorbell_offset + |
439 | sg_dma_address(client->client_obj->pages->sgl); |
439 | sg_dma_address(client->client_obj->pages->sgl); |
440 | 440 | ||
441 | desc.process_desc = client->proc_desc_offset + |
441 | desc.process_desc = client->proc_desc_offset + |
442 | i915_gem_obj_ggtt_offset(client->client_obj); |
442 | i915_gem_obj_ggtt_offset(client->client_obj); |
443 | 443 | ||
444 | desc.wq_addr = client->wq_offset + |
444 | desc.wq_addr = client->wq_offset + |
445 | i915_gem_obj_ggtt_offset(client->client_obj); |
445 | i915_gem_obj_ggtt_offset(client->client_obj); |
446 | 446 | ||
447 | desc.wq_size = client->wq_size; |
447 | desc.wq_size = client->wq_size; |
448 | 448 | ||
449 | /* |
449 | /* |
450 | * XXX: Take LRCs from an existing intel_context if this is not an |
450 | * XXX: Take LRCs from an existing intel_context if this is not an |
451 | * IsKMDCreatedContext client |
451 | * IsKMDCreatedContext client |
452 | */ |
452 | */ |
453 | desc.desc_private = (uintptr_t)client; |
453 | desc.desc_private = (uintptr_t)client; |
454 | 454 | ||
455 | /* Pool context is pinned already */ |
455 | /* Pool context is pinned already */ |
456 | sg = guc->ctx_pool_obj->pages; |
456 | sg = guc->ctx_pool_obj->pages; |
457 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), |
457 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), |
458 | sizeof(desc) * client->ctx_index); |
458 | sizeof(desc) * client->ctx_index); |
459 | } |
459 | } |
460 | 460 | ||
461 | static void guc_fini_ctx_desc(struct intel_guc *guc, |
461 | static void guc_fini_ctx_desc(struct intel_guc *guc, |
462 | struct i915_guc_client *client) |
462 | struct i915_guc_client *client) |
463 | { |
463 | { |
464 | struct guc_context_desc desc; |
464 | struct guc_context_desc desc; |
465 | struct sg_table *sg; |
465 | struct sg_table *sg; |
466 | 466 | ||
467 | memset(&desc, 0, sizeof(desc)); |
467 | memset(&desc, 0, sizeof(desc)); |
468 | 468 | ||
469 | sg = guc->ctx_pool_obj->pages; |
469 | sg = guc->ctx_pool_obj->pages; |
470 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), |
470 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), |
471 | sizeof(desc) * client->ctx_index); |
471 | sizeof(desc) * client->ctx_index); |
472 | } |
472 | } |
473 | - | ||
474 | /* Get valid workqueue item and return it back to offset */ |
473 | |
475 | static int guc_get_workqueue_space(struct i915_guc_client *gc, u32 *offset) |
474 | int i915_guc_wq_check_space(struct i915_guc_client *gc) |
476 | { |
475 | { |
477 | struct guc_process_desc *desc; |
476 | struct guc_process_desc *desc; |
478 | void *base; |
477 | void *base; |
479 | u32 size = sizeof(struct guc_wq_item); |
478 | u32 size = sizeof(struct guc_wq_item); |
480 | int ret = -ETIMEDOUT, timeout_counter = 200; |
479 | int ret = -ETIMEDOUT, timeout_counter = 200; |
- | 480 | ||
- | 481 | if (!gc) |
|
- | 482 | return 0; |
|
- | 483 | ||
- | 484 | /* Quickly return if wq space is available since last time we cache the |
|
- | 485 | * head position. */ |
|
- | 486 | if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size) |
|
- | 487 | return 0; |
|
481 | 488 | ||
482 | base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0)); |
489 | base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0)); |
483 | desc = base + gc->proc_desc_offset; |
490 | desc = base + gc->proc_desc_offset; |
484 | 491 | ||
485 | while (timeout_counter-- > 0) { |
492 | while (timeout_counter-- > 0) { |
486 | if (CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size) >= size) { |
- | |
487 | *offset = gc->wq_tail; |
493 | gc->wq_head = desc->head; |
488 | - | ||
489 | /* advance the tail for next workqueue item */ |
- | |
490 | gc->wq_tail += size; |
494 | |
491 | gc->wq_tail &= gc->wq_size - 1; |
- | |
492 | - | ||
493 | /* this will break the loop */ |
- | |
494 | timeout_counter = 0; |
495 | if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size) { |
- | 496 | ret = 0; |
|
495 | ret = 0; |
497 | break; |
496 | } |
498 | } |
497 | 499 | ||
498 | if (timeout_counter) |
500 | if (timeout_counter) |
499 | usleep_range(1000, 2000); |
501 | usleep_range(1000, 2000); |
500 | }; |
502 | }; |
501 | 503 | ||
502 | kunmap_atomic(base); |
504 | kunmap_atomic(base); |
503 | 505 | ||
504 | return ret; |
506 | return ret; |
505 | } |
507 | } |
506 | 508 | ||
507 | static int guc_add_workqueue_item(struct i915_guc_client *gc, |
509 | static int guc_add_workqueue_item(struct i915_guc_client *gc, |
508 | struct drm_i915_gem_request *rq) |
510 | struct drm_i915_gem_request *rq) |
509 | { |
511 | { |
510 | enum intel_ring_id ring_id = rq->ring->id; |
- | |
511 | struct guc_wq_item *wqi; |
512 | struct guc_wq_item *wqi; |
512 | void *base; |
513 | void *base; |
513 | u32 tail, wq_len, wq_off = 0; |
514 | u32 tail, wq_len, wq_off, space; |
514 | int ret; |
- | |
515 | 515 | ||
- | 516 | space = CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size); |
|
- | 517 | if (WARN_ON(space < sizeof(struct guc_wq_item))) |
|
- | 518 | return -ENOSPC; /* shouldn't happen */ |
|
- | 519 | ||
516 | ret = guc_get_workqueue_space(gc, &wq_off); |
520 | /* postincrement WQ tail for next time */ |
- | 521 | wq_off = gc->wq_tail; |
|
517 | if (ret) |
522 | gc->wq_tail += sizeof(struct guc_wq_item); |
518 | return ret; |
523 | gc->wq_tail &= gc->wq_size - 1; |
519 | 524 | ||
520 | /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we |
525 | /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we |
521 | * should not have the case where structure wqi is across page, neither |
526 | * should not have the case where structure wqi is across page, neither |
522 | * wrapped to the beginning. This simplifies the implementation below. |
527 | * wrapped to the beginning. This simplifies the implementation below. |
523 | * |
528 | * |
524 | * XXX: if not the case, we need save data to a temp wqi and copy it to |
529 | * XXX: if not the case, we need save data to a temp wqi and copy it to |
525 | * workqueue buffer dw by dw. |
530 | * workqueue buffer dw by dw. |
526 | */ |
531 | */ |
527 | WARN_ON(sizeof(struct guc_wq_item) != 16); |
532 | WARN_ON(sizeof(struct guc_wq_item) != 16); |
528 | WARN_ON(wq_off & 3); |
533 | WARN_ON(wq_off & 3); |
529 | 534 | ||
530 | /* wq starts from the page after doorbell / process_desc */ |
535 | /* wq starts from the page after doorbell / process_desc */ |
531 | base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, |
536 | base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, |
532 | (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT)); |
537 | (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT)); |
533 | wq_off &= PAGE_SIZE - 1; |
538 | wq_off &= PAGE_SIZE - 1; |
534 | wqi = (struct guc_wq_item *)((char *)base + wq_off); |
539 | wqi = (struct guc_wq_item *)((char *)base + wq_off); |
535 | 540 | ||
536 | /* len does not include the header */ |
541 | /* len does not include the header */ |
537 | wq_len = sizeof(struct guc_wq_item) / sizeof(u32) - 1; |
542 | wq_len = sizeof(struct guc_wq_item) / sizeof(u32) - 1; |
538 | wqi->header = WQ_TYPE_INORDER | |
543 | wqi->header = WQ_TYPE_INORDER | |
539 | (wq_len << WQ_LEN_SHIFT) | |
544 | (wq_len << WQ_LEN_SHIFT) | |
540 | (ring_id << WQ_TARGET_SHIFT) | |
545 | (rq->ring->guc_id << WQ_TARGET_SHIFT) | |
541 | WQ_NO_WCFLUSH_WAIT; |
546 | WQ_NO_WCFLUSH_WAIT; |
542 | 547 | ||
543 | /* The GuC wants only the low-order word of the context descriptor */ |
548 | /* The GuC wants only the low-order word of the context descriptor */ |
544 | wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, rq->ring); |
549 | wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, rq->ring); |
545 | 550 | ||
546 | /* The GuC firmware wants the tail index in QWords, not bytes */ |
551 | /* The GuC firmware wants the tail index in QWords, not bytes */ |
547 | tail = rq->ringbuf->tail >> 3; |
552 | tail = rq->ringbuf->tail >> 3; |
548 | wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT; |
553 | wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT; |
549 | wqi->fence_id = 0; /*XXX: what fence to be here */ |
554 | wqi->fence_id = 0; /*XXX: what fence to be here */ |
550 | 555 | ||
551 | kunmap_atomic(base); |
556 | kunmap_atomic(base); |
552 | 557 | ||
553 | return 0; |
558 | return 0; |
554 | } |
559 | } |
555 | - | ||
556 | #define CTX_RING_BUFFER_START 0x08 |
- | |
557 | - | ||
558 | /* Update the ringbuffer pointer in a saved context image */ |
- | |
559 | static void lr_context_update(struct drm_i915_gem_request *rq) |
- | |
560 | { |
- | |
561 | enum intel_ring_id ring_id = rq->ring->id; |
- | |
562 | struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring_id].state; |
- | |
563 | struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj; |
- | |
564 | struct page *page; |
- | |
565 | uint32_t *reg_state; |
- | |
566 | - | ||
567 | BUG_ON(!ctx_obj); |
- | |
568 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj)); |
- | |
569 | WARN_ON(!i915_gem_obj_is_pinned(rb_obj)); |
- | |
570 | - | ||
571 | page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN); |
- | |
572 | reg_state = kmap_atomic(page); |
- | |
573 | - | ||
574 | reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj); |
- | |
575 | - | ||
576 | kunmap_atomic(reg_state); |
- | |
577 | } |
- | |
578 | 560 | ||
579 | /** |
561 | /** |
580 | * i915_guc_submit() - Submit commands through GuC |
562 | * i915_guc_submit() - Submit commands through GuC |
581 | * @client: the guc client where commands will go through |
563 | * @client: the guc client where commands will go through |
582 | * @rq: request associated with the commands |
564 | * @rq: request associated with the commands |
583 | * |
565 | * |
584 | * Return: 0 if succeed |
566 | * Return: 0 if succeed |
585 | */ |
567 | */ |
586 | int i915_guc_submit(struct i915_guc_client *client, |
568 | int i915_guc_submit(struct i915_guc_client *client, |
587 | struct drm_i915_gem_request *rq) |
569 | struct drm_i915_gem_request *rq) |
588 | { |
570 | { |
589 | struct intel_guc *guc = client->guc; |
571 | struct intel_guc *guc = client->guc; |
590 | enum intel_ring_id ring_id = rq->ring->id; |
572 | unsigned int engine_id = rq->ring->guc_id; |
591 | int q_ret, b_ret; |
573 | int q_ret, b_ret; |
592 | - | ||
593 | /* Need this because of the deferred pin ctx and ring */ |
- | |
594 | /* Shall we move this right after ring is pinned? */ |
- | |
595 | lr_context_update(rq); |
- | |
596 | 574 | ||
597 | q_ret = guc_add_workqueue_item(client, rq); |
575 | q_ret = guc_add_workqueue_item(client, rq); |
598 | if (q_ret == 0) |
576 | if (q_ret == 0) |
599 | b_ret = guc_ring_doorbell(client); |
577 | b_ret = guc_ring_doorbell(client); |
600 | 578 | ||
601 | client->submissions[ring_id] += 1; |
579 | client->submissions[engine_id] += 1; |
602 | if (q_ret) { |
580 | if (q_ret) { |
603 | client->q_fail += 1; |
581 | client->q_fail += 1; |
604 | client->retcode = q_ret; |
582 | client->retcode = q_ret; |
605 | } else if (b_ret) { |
583 | } else if (b_ret) { |
606 | client->b_fail += 1; |
584 | client->b_fail += 1; |
607 | client->retcode = q_ret = b_ret; |
585 | client->retcode = q_ret = b_ret; |
608 | } else { |
586 | } else { |
609 | client->retcode = 0; |
587 | client->retcode = 0; |
610 | } |
588 | } |
611 | guc->submissions[ring_id] += 1; |
589 | guc->submissions[engine_id] += 1; |
612 | guc->last_seqno[ring_id] = rq->seqno; |
590 | guc->last_seqno[engine_id] = rq->seqno; |
613 | 591 | ||
614 | return q_ret; |
592 | return q_ret; |
615 | } |
593 | } |
616 | 594 | ||
617 | /* |
595 | /* |
618 | * Everything below here is concerned with setup & teardown, and is |
596 | * Everything below here is concerned with setup & teardown, and is |
619 | * therefore not part of the somewhat time-critical batch-submission |
597 | * therefore not part of the somewhat time-critical batch-submission |
620 | * path of i915_guc_submit() above. |
598 | * path of i915_guc_submit() above. |
621 | */ |
599 | */ |
622 | 600 | ||
623 | /** |
601 | /** |
624 | * gem_allocate_guc_obj() - Allocate gem object for GuC usage |
602 | * gem_allocate_guc_obj() - Allocate gem object for GuC usage |
625 | * @dev: drm device |
603 | * @dev: drm device |
626 | * @size: size of object |
604 | * @size: size of object |
627 | * |
605 | * |
628 | * This is a wrapper to create a gem obj. In order to use it inside GuC, the |
606 | * This is a wrapper to create a gem obj. In order to use it inside GuC, the |
629 | * object needs to be pinned lifetime. Also we must pin it to gtt space other |
607 | * object needs to be pinned lifetime. Also we must pin it to gtt space other |
630 | * than [0, GUC_WOPCM_TOP) because this range is reserved inside GuC. |
608 | * than [0, GUC_WOPCM_TOP) because this range is reserved inside GuC. |
631 | * |
609 | * |
632 | * Return: A drm_i915_gem_object if successful, otherwise NULL. |
610 | * Return: A drm_i915_gem_object if successful, otherwise NULL. |
633 | */ |
611 | */ |
634 | static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev, |
612 | static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev, |
635 | u32 size) |
613 | u32 size) |
636 | { |
614 | { |
637 | struct drm_i915_private *dev_priv = dev->dev_private; |
615 | struct drm_i915_private *dev_priv = dev->dev_private; |
638 | struct drm_i915_gem_object *obj; |
616 | struct drm_i915_gem_object *obj; |
639 | 617 | ||
640 | obj = i915_gem_alloc_object(dev, size); |
618 | obj = i915_gem_alloc_object(dev, size); |
641 | if (!obj) |
619 | if (!obj) |
642 | return NULL; |
620 | return NULL; |
643 | 621 | ||
644 | if (i915_gem_object_get_pages(obj)) { |
622 | if (i915_gem_object_get_pages(obj)) { |
645 | drm_gem_object_unreference(&obj->base); |
623 | drm_gem_object_unreference(&obj->base); |
646 | return NULL; |
624 | return NULL; |
647 | } |
625 | } |
648 | 626 | ||
649 | if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, |
627 | if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, |
650 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP)) { |
628 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP)) { |
651 | drm_gem_object_unreference(&obj->base); |
629 | drm_gem_object_unreference(&obj->base); |
652 | return NULL; |
630 | return NULL; |
653 | } |
631 | } |
654 | 632 | ||
655 | /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ |
633 | /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ |
656 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); |
634 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); |
657 | 635 | ||
658 | return obj; |
636 | return obj; |
659 | } |
637 | } |
660 | 638 | ||
661 | /** |
639 | /** |
662 | * gem_release_guc_obj() - Release gem object allocated for GuC usage |
640 | * gem_release_guc_obj() - Release gem object allocated for GuC usage |
663 | * @obj: gem obj to be released |
641 | * @obj: gem obj to be released |
664 | */ |
642 | */ |
665 | static void gem_release_guc_obj(struct drm_i915_gem_object *obj) |
643 | static void gem_release_guc_obj(struct drm_i915_gem_object *obj) |
666 | { |
644 | { |
667 | if (!obj) |
645 | if (!obj) |
668 | return; |
646 | return; |
669 | 647 | ||
670 | if (i915_gem_obj_is_pinned(obj)) |
648 | if (i915_gem_obj_is_pinned(obj)) |
671 | i915_gem_object_ggtt_unpin(obj); |
649 | i915_gem_object_ggtt_unpin(obj); |
672 | 650 | ||
673 | drm_gem_object_unreference(&obj->base); |
651 | drm_gem_object_unreference(&obj->base); |
674 | } |
652 | } |
675 | 653 | ||
676 | static void guc_client_free(struct drm_device *dev, |
654 | static void guc_client_free(struct drm_device *dev, |
677 | struct i915_guc_client *client) |
655 | struct i915_guc_client *client) |
678 | { |
656 | { |
679 | struct drm_i915_private *dev_priv = dev->dev_private; |
657 | struct drm_i915_private *dev_priv = dev->dev_private; |
680 | struct intel_guc *guc = &dev_priv->guc; |
658 | struct intel_guc *guc = &dev_priv->guc; |
681 | 659 | ||
682 | if (!client) |
660 | if (!client) |
683 | return; |
661 | return; |
684 | 662 | ||
685 | if (client->doorbell_id != GUC_INVALID_DOORBELL_ID) { |
663 | if (client->doorbell_id != GUC_INVALID_DOORBELL_ID) { |
686 | /* |
664 | /* |
687 | * First disable the doorbell, then tell the GuC we've |
665 | * First disable the doorbell, then tell the GuC we've |
688 | * finished with it, finally deallocate it in our bitmap |
666 | * finished with it, finally deallocate it in our bitmap |
689 | */ |
667 | */ |
690 | guc_disable_doorbell(guc, client); |
668 | guc_disable_doorbell(guc, client); |
691 | host2guc_release_doorbell(guc, client); |
669 | host2guc_release_doorbell(guc, client); |
692 | release_doorbell(guc, client->doorbell_id); |
670 | release_doorbell(guc, client->doorbell_id); |
693 | } |
671 | } |
694 | 672 | ||
695 | /* |
673 | /* |
696 | * XXX: wait for any outstanding submissions before freeing memory. |
674 | * XXX: wait for any outstanding submissions before freeing memory. |
697 | * Be sure to drop any locks |
675 | * Be sure to drop any locks |
698 | */ |
676 | */ |
699 | 677 | ||
700 | gem_release_guc_obj(client->client_obj); |
678 | gem_release_guc_obj(client->client_obj); |
701 | 679 | ||
702 | if (client->ctx_index != GUC_INVALID_CTX_ID) { |
680 | if (client->ctx_index != GUC_INVALID_CTX_ID) { |
703 | guc_fini_ctx_desc(guc, client); |
681 | guc_fini_ctx_desc(guc, client); |
704 | ida_simple_remove(&guc->ctx_ids, client->ctx_index); |
682 | ida_simple_remove(&guc->ctx_ids, client->ctx_index); |
705 | } |
683 | } |
706 | 684 | ||
707 | kfree(client); |
685 | kfree(client); |
708 | } |
686 | } |
709 | 687 | ||
710 | /** |
688 | /** |
711 | * guc_client_alloc() - Allocate an i915_guc_client |
689 | * guc_client_alloc() - Allocate an i915_guc_client |
712 | * @dev: drm device |
690 | * @dev: drm device |
713 | * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW |
691 | * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW |
714 | * The kernel client to replace ExecList submission is created with |
692 | * The kernel client to replace ExecList submission is created with |
715 | * NORMAL priority. Priority of a client for scheduler can be HIGH, |
693 | * NORMAL priority. Priority of a client for scheduler can be HIGH, |
716 | * while a preemption context can use CRITICAL. |
694 | * while a preemption context can use CRITICAL. |
717 | * @ctx: the context that owns the client (we use the default render |
695 | * @ctx: the context that owns the client (we use the default render |
718 | * context) |
696 | * context) |
719 | * |
697 | * |
720 | * Return: An i915_guc_client object if success. |
698 | * Return: An i915_guc_client object if success. |
721 | */ |
699 | */ |
722 | static struct i915_guc_client *guc_client_alloc(struct drm_device *dev, |
700 | static struct i915_guc_client *guc_client_alloc(struct drm_device *dev, |
723 | uint32_t priority, |
701 | uint32_t priority, |
724 | struct intel_context *ctx) |
702 | struct intel_context *ctx) |
725 | { |
703 | { |
726 | struct i915_guc_client *client; |
704 | struct i915_guc_client *client; |
727 | struct drm_i915_private *dev_priv = dev->dev_private; |
705 | struct drm_i915_private *dev_priv = dev->dev_private; |
728 | struct intel_guc *guc = &dev_priv->guc; |
706 | struct intel_guc *guc = &dev_priv->guc; |
729 | struct drm_i915_gem_object *obj; |
707 | struct drm_i915_gem_object *obj; |
730 | 708 | ||
731 | client = kzalloc(sizeof(*client), GFP_KERNEL); |
709 | client = kzalloc(sizeof(*client), GFP_KERNEL); |
732 | if (!client) |
710 | if (!client) |
733 | return NULL; |
711 | return NULL; |
734 | 712 | ||
735 | client->doorbell_id = GUC_INVALID_DOORBELL_ID; |
713 | client->doorbell_id = GUC_INVALID_DOORBELL_ID; |
736 | client->priority = priority; |
714 | client->priority = priority; |
737 | client->owner = ctx; |
715 | client->owner = ctx; |
738 | client->guc = guc; |
716 | client->guc = guc; |
739 | 717 | ||
740 | client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0, |
718 | client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0, |
741 | GUC_MAX_GPU_CONTEXTS, GFP_KERNEL); |
719 | GUC_MAX_GPU_CONTEXTS, GFP_KERNEL); |
742 | if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) { |
720 | if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) { |
743 | client->ctx_index = GUC_INVALID_CTX_ID; |
721 | client->ctx_index = GUC_INVALID_CTX_ID; |
744 | goto err; |
722 | goto err; |
745 | } |
723 | } |
746 | 724 | ||
747 | /* The first page is doorbell/proc_desc. Two followed pages are wq. */ |
725 | /* The first page is doorbell/proc_desc. Two followed pages are wq. */ |
748 | obj = gem_allocate_guc_obj(dev, GUC_DB_SIZE + GUC_WQ_SIZE); |
726 | obj = gem_allocate_guc_obj(dev, GUC_DB_SIZE + GUC_WQ_SIZE); |
749 | if (!obj) |
727 | if (!obj) |
750 | goto err; |
728 | goto err; |
751 | 729 | ||
752 | client->client_obj = obj; |
730 | client->client_obj = obj; |
753 | client->wq_offset = GUC_DB_SIZE; |
731 | client->wq_offset = GUC_DB_SIZE; |
754 | client->wq_size = GUC_WQ_SIZE; |
732 | client->wq_size = GUC_WQ_SIZE; |
755 | 733 | ||
756 | client->doorbell_offset = select_doorbell_cacheline(guc); |
734 | client->doorbell_offset = select_doorbell_cacheline(guc); |
757 | 735 | ||
758 | /* |
736 | /* |
759 | * Since the doorbell only requires a single cacheline, we can save |
737 | * Since the doorbell only requires a single cacheline, we can save |
760 | * space by putting the application process descriptor in the same |
738 | * space by putting the application process descriptor in the same |
761 | * page. Use the half of the page that doesn't include the doorbell. |
739 | * page. Use the half of the page that doesn't include the doorbell. |
762 | */ |
740 | */ |
763 | if (client->doorbell_offset >= (GUC_DB_SIZE / 2)) |
741 | if (client->doorbell_offset >= (GUC_DB_SIZE / 2)) |
764 | client->proc_desc_offset = 0; |
742 | client->proc_desc_offset = 0; |
765 | else |
743 | else |
766 | client->proc_desc_offset = (GUC_DB_SIZE / 2); |
744 | client->proc_desc_offset = (GUC_DB_SIZE / 2); |
767 | 745 | ||
768 | client->doorbell_id = assign_doorbell(guc, client->priority); |
746 | client->doorbell_id = assign_doorbell(guc, client->priority); |
769 | if (client->doorbell_id == GUC_INVALID_DOORBELL_ID) |
747 | if (client->doorbell_id == GUC_INVALID_DOORBELL_ID) |
770 | /* XXX: evict a doorbell instead */ |
748 | /* XXX: evict a doorbell instead */ |
771 | goto err; |
749 | goto err; |
772 | 750 | ||
773 | guc_init_proc_desc(guc, client); |
751 | guc_init_proc_desc(guc, client); |
774 | guc_init_ctx_desc(guc, client); |
752 | guc_init_ctx_desc(guc, client); |
775 | guc_init_doorbell(guc, client); |
753 | guc_init_doorbell(guc, client); |
776 | 754 | ||
777 | /* XXX: Any cache flushes needed? General domain mgmt calls? */ |
755 | /* XXX: Any cache flushes needed? General domain mgmt calls? */ |
778 | 756 | ||
779 | if (host2guc_allocate_doorbell(guc, client)) |
757 | if (host2guc_allocate_doorbell(guc, client)) |
780 | goto err; |
758 | goto err; |
781 | 759 | ||
782 | DRM_DEBUG_DRIVER("new priority %u client %p: ctx_index %u db_id %u\n", |
760 | DRM_DEBUG_DRIVER("new priority %u client %p: ctx_index %u db_id %u\n", |
783 | priority, client, client->ctx_index, client->doorbell_id); |
761 | priority, client, client->ctx_index, client->doorbell_id); |
784 | 762 | ||
785 | return client; |
763 | return client; |
786 | 764 | ||
787 | err: |
765 | err: |
788 | DRM_ERROR("FAILED to create priority %u GuC client!\n", priority); |
766 | DRM_ERROR("FAILED to create priority %u GuC client!\n", priority); |
789 | 767 | ||
790 | guc_client_free(dev, client); |
768 | guc_client_free(dev, client); |
791 | return NULL; |
769 | return NULL; |
792 | } |
770 | } |
793 | 771 | ||
794 | static void guc_create_log(struct intel_guc *guc) |
772 | static void guc_create_log(struct intel_guc *guc) |
795 | { |
773 | { |
796 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
774 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
797 | struct drm_i915_gem_object *obj; |
775 | struct drm_i915_gem_object *obj; |
798 | unsigned long offset; |
776 | unsigned long offset; |
799 | uint32_t size, flags; |
777 | uint32_t size, flags; |
800 | 778 | ||
801 | if (i915.guc_log_level < GUC_LOG_VERBOSITY_MIN) |
779 | if (i915.guc_log_level < GUC_LOG_VERBOSITY_MIN) |
802 | return; |
780 | return; |
803 | 781 | ||
804 | if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX) |
782 | if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX) |
805 | i915.guc_log_level = GUC_LOG_VERBOSITY_MAX; |
783 | i915.guc_log_level = GUC_LOG_VERBOSITY_MAX; |
806 | 784 | ||
807 | /* The first page is to save log buffer state. Allocate one |
785 | /* The first page is to save log buffer state. Allocate one |
808 | * extra page for others in case for overlap */ |
786 | * extra page for others in case for overlap */ |
809 | size = (1 + GUC_LOG_DPC_PAGES + 1 + |
787 | size = (1 + GUC_LOG_DPC_PAGES + 1 + |
810 | GUC_LOG_ISR_PAGES + 1 + |
788 | GUC_LOG_ISR_PAGES + 1 + |
811 | GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT; |
789 | GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT; |
812 | 790 | ||
813 | obj = guc->log_obj; |
791 | obj = guc->log_obj; |
814 | if (!obj) { |
792 | if (!obj) { |
815 | obj = gem_allocate_guc_obj(dev_priv->dev, size); |
793 | obj = gem_allocate_guc_obj(dev_priv->dev, size); |
816 | if (!obj) { |
794 | if (!obj) { |
817 | /* logging will be off */ |
795 | /* logging will be off */ |
818 | i915.guc_log_level = -1; |
796 | i915.guc_log_level = -1; |
819 | return; |
797 | return; |
820 | } |
798 | } |
821 | 799 | ||
822 | guc->log_obj = obj; |
800 | guc->log_obj = obj; |
823 | } |
801 | } |
824 | 802 | ||
825 | /* each allocated unit is a page */ |
803 | /* each allocated unit is a page */ |
826 | flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL | |
804 | flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL | |
827 | (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) | |
805 | (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) | |
828 | (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) | |
806 | (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) | |
829 | (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT); |
807 | (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT); |
830 | 808 | ||
831 | offset = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; /* in pages */ |
809 | offset = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; /* in pages */ |
832 | guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags; |
810 | guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags; |
833 | } |
811 | } |
- | 812 | ||
- | 813 | static void init_guc_policies(struct guc_policies *policies) |
|
- | 814 | { |
|
- | 815 | struct guc_policy *policy; |
|
- | 816 | u32 p, i; |
|
- | 817 | ||
- | 818 | policies->dpc_promote_time = 500000; |
|
- | 819 | policies->max_num_work_items = POLICY_MAX_NUM_WI; |
|
- | 820 | ||
- | 821 | for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) { |
|
- | 822 | for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) { |
|
- | 823 | policy = &policies->policy[p][i]; |
|
- | 824 | ||
- | 825 | policy->execution_quantum = 1000000; |
|
- | 826 | policy->preemption_time = 500000; |
|
- | 827 | policy->fault_time = 250000; |
|
- | 828 | policy->policy_flags = 0; |
|
- | 829 | } |
|
- | 830 | } |
|
- | 831 | ||
- | 832 | policies->is_valid = 1; |
|
- | 833 | } |
|
- | 834 | ||
- | 835 | static void guc_create_ads(struct intel_guc *guc) |
|
- | 836 | { |
|
- | 837 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
|
- | 838 | struct drm_i915_gem_object *obj; |
|
- | 839 | struct guc_ads *ads; |
|
- | 840 | struct guc_policies *policies; |
|
- | 841 | struct guc_mmio_reg_state *reg_state; |
|
- | 842 | struct intel_engine_cs *ring; |
|
- | 843 | struct page *page; |
|
- | 844 | u32 size, i; |
|
- | 845 | ||
- | 846 | /* The ads obj includes the struct itself and buffers passed to GuC */ |
|
- | 847 | size = sizeof(struct guc_ads) + sizeof(struct guc_policies) + |
|
- | 848 | sizeof(struct guc_mmio_reg_state) + |
|
- | 849 | GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE; |
|
- | 850 | ||
- | 851 | obj = guc->ads_obj; |
|
- | 852 | if (!obj) { |
|
- | 853 | obj = gem_allocate_guc_obj(dev_priv->dev, PAGE_ALIGN(size)); |
|
- | 854 | if (!obj) |
|
- | 855 | return; |
|
- | 856 | ||
- | 857 | guc->ads_obj = obj; |
|
- | 858 | } |
|
- | 859 | ||
- | 860 | page = i915_gem_object_get_page(obj, 0); |
|
- | 861 | ads = kmap(page); |
|
- | 862 | ||
- | 863 | /* |
|
- | 864 | * The GuC requires a "Golden Context" when it reinitialises |
|
- | 865 | * engines after a reset. Here we use the Render ring default |
|
- | 866 | * context, which must already exist and be pinned in the GGTT, |
|
- | 867 | * so its address won't change after we've told the GuC where |
|
- | 868 | * to find it. |
|
- | 869 | */ |
|
- | 870 | ring = &dev_priv->ring[RCS]; |
|
- | 871 | ads->golden_context_lrca = ring->status_page.gfx_addr; |
|
- | 872 | ||
- | 873 | for_each_ring(ring, dev_priv, i) |
|
- | 874 | ads->eng_state_size[ring->guc_id] = intel_lr_context_size(ring); |
|
- | 875 | ||
- | 876 | /* GuC scheduling policies */ |
|
- | 877 | policies = (void *)ads + sizeof(struct guc_ads); |
|
- | 878 | init_guc_policies(policies); |
|
- | 879 | ||
- | 880 | ads->scheduler_policies = i915_gem_obj_ggtt_offset(obj) + |
|
- | 881 | sizeof(struct guc_ads); |
|
- | 882 | ||
- | 883 | /* MMIO reg state */ |
|
- | 884 | reg_state = (void *)policies + sizeof(struct guc_policies); |
|
- | 885 | ||
- | 886 | for_each_ring(ring, dev_priv, i) { |
|
- | 887 | reg_state->mmio_white_list[ring->guc_id].mmio_start = |
|
- | 888 | ring->mmio_base + GUC_MMIO_WHITE_LIST_START; |
|
- | 889 | ||
- | 890 | /* Nothing to be saved or restored for now. */ |
|
- | 891 | reg_state->mmio_white_list[ring->guc_id].count = 0; |
|
- | 892 | } |
|
- | 893 | ||
- | 894 | ads->reg_state_addr = ads->scheduler_policies + |
|
- | 895 | sizeof(struct guc_policies); |
|
- | 896 | ||
- | 897 | ads->reg_state_buffer = ads->reg_state_addr + |
|
- | 898 | sizeof(struct guc_mmio_reg_state); |
|
- | 899 | ||
- | 900 | kunmap(page); |
|
- | 901 | } |
|
834 | 902 | ||
835 | /* |
903 | /* |
836 | * Set up the memory resources to be shared with the GuC. At this point, |
904 | * Set up the memory resources to be shared with the GuC. At this point, |
837 | * we require just one object that can be mapped through the GGTT. |
905 | * we require just one object that can be mapped through the GGTT. |
838 | */ |
906 | */ |
839 | int i915_guc_submission_init(struct drm_device *dev) |
907 | int i915_guc_submission_init(struct drm_device *dev) |
840 | { |
908 | { |
841 | struct drm_i915_private *dev_priv = dev->dev_private; |
909 | struct drm_i915_private *dev_priv = dev->dev_private; |
842 | const size_t ctxsize = sizeof(struct guc_context_desc); |
910 | const size_t ctxsize = sizeof(struct guc_context_desc); |
843 | const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize; |
911 | const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize; |
844 | const size_t gemsize = round_up(poolsize, PAGE_SIZE); |
912 | const size_t gemsize = round_up(poolsize, PAGE_SIZE); |
845 | struct intel_guc *guc = &dev_priv->guc; |
913 | struct intel_guc *guc = &dev_priv->guc; |
846 | 914 | ||
847 | if (!i915.enable_guc_submission) |
915 | if (!i915.enable_guc_submission) |
848 | return 0; /* not enabled */ |
916 | return 0; /* not enabled */ |
849 | 917 | ||
850 | if (guc->ctx_pool_obj) |
918 | if (guc->ctx_pool_obj) |
851 | return 0; /* already allocated */ |
919 | return 0; /* already allocated */ |
852 | 920 | ||
853 | guc->ctx_pool_obj = gem_allocate_guc_obj(dev_priv->dev, gemsize); |
921 | guc->ctx_pool_obj = gem_allocate_guc_obj(dev_priv->dev, gemsize); |
854 | if (!guc->ctx_pool_obj) |
922 | if (!guc->ctx_pool_obj) |
855 | return -ENOMEM; |
923 | return -ENOMEM; |
856 | 924 | ||
857 | ida_init(&guc->ctx_ids); |
925 | ida_init(&guc->ctx_ids); |
858 | 926 | ||
859 | guc_create_log(guc); |
927 | guc_create_log(guc); |
- | 928 | ||
- | 929 | guc_create_ads(guc); |
|
860 | 930 | ||
861 | return 0; |
931 | return 0; |
862 | } |
932 | } |
863 | 933 | ||
864 | int i915_guc_submission_enable(struct drm_device *dev) |
934 | int i915_guc_submission_enable(struct drm_device *dev) |
865 | { |
935 | { |
866 | struct drm_i915_private *dev_priv = dev->dev_private; |
936 | struct drm_i915_private *dev_priv = dev->dev_private; |
867 | struct intel_guc *guc = &dev_priv->guc; |
937 | struct intel_guc *guc = &dev_priv->guc; |
868 | struct intel_context *ctx = dev_priv->ring[RCS].default_context; |
938 | struct intel_context *ctx = dev_priv->kernel_context; |
869 | struct i915_guc_client *client; |
939 | struct i915_guc_client *client; |
870 | 940 | ||
871 | /* client for execbuf submission */ |
941 | /* client for execbuf submission */ |
872 | client = guc_client_alloc(dev, GUC_CTX_PRIORITY_KMD_NORMAL, ctx); |
942 | client = guc_client_alloc(dev, GUC_CTX_PRIORITY_KMD_NORMAL, ctx); |
873 | if (!client) { |
943 | if (!client) { |
874 | DRM_ERROR("Failed to create execbuf guc_client\n"); |
944 | DRM_ERROR("Failed to create execbuf guc_client\n"); |
875 | return -ENOMEM; |
945 | return -ENOMEM; |
876 | } |
946 | } |
877 | 947 | ||
878 | guc->execbuf_client = client; |
948 | guc->execbuf_client = client; |
879 | 949 | ||
880 | host2guc_sample_forcewake(guc, client); |
950 | host2guc_sample_forcewake(guc, client); |
881 | 951 | ||
882 | return 0; |
952 | return 0; |
883 | } |
953 | } |
884 | 954 | ||
885 | void i915_guc_submission_disable(struct drm_device *dev) |
955 | void i915_guc_submission_disable(struct drm_device *dev) |
886 | { |
956 | { |
887 | struct drm_i915_private *dev_priv = dev->dev_private; |
957 | struct drm_i915_private *dev_priv = dev->dev_private; |
888 | struct intel_guc *guc = &dev_priv->guc; |
958 | struct intel_guc *guc = &dev_priv->guc; |
889 | 959 | ||
890 | guc_client_free(dev, guc->execbuf_client); |
960 | guc_client_free(dev, guc->execbuf_client); |
891 | guc->execbuf_client = NULL; |
961 | guc->execbuf_client = NULL; |
892 | } |
962 | } |
893 | 963 | ||
894 | void i915_guc_submission_fini(struct drm_device *dev) |
964 | void i915_guc_submission_fini(struct drm_device *dev) |
895 | { |
965 | { |
896 | struct drm_i915_private *dev_priv = dev->dev_private; |
966 | struct drm_i915_private *dev_priv = dev->dev_private; |
897 | struct intel_guc *guc = &dev_priv->guc; |
967 | struct intel_guc *guc = &dev_priv->guc; |
- | 968 | ||
- | 969 | gem_release_guc_obj(dev_priv->guc.ads_obj); |
|
- | 970 | guc->ads_obj = NULL; |
|
898 | 971 | ||
899 | gem_release_guc_obj(dev_priv->guc.log_obj); |
972 | gem_release_guc_obj(dev_priv->guc.log_obj); |
900 | guc->log_obj = NULL; |
973 | guc->log_obj = NULL; |
901 | 974 | ||
902 | if (guc->ctx_pool_obj) |
975 | if (guc->ctx_pool_obj) |
903 | ida_destroy(&guc->ctx_ids); |
976 | ida_destroy(&guc->ctx_ids); |
904 | gem_release_guc_obj(guc->ctx_pool_obj); |
977 | gem_release_guc_obj(guc->ctx_pool_obj); |
905 | guc->ctx_pool_obj = NULL; |
978 | guc->ctx_pool_obj = NULL; |
906 | } |
979 | } |
907 | 980 | ||
908 | /** |
981 | /** |
909 | * intel_guc_suspend() - notify GuC entering suspend state |
982 | * intel_guc_suspend() - notify GuC entering suspend state |
910 | * @dev: drm device |
983 | * @dev: drm device |
911 | */ |
984 | */ |
912 | int intel_guc_suspend(struct drm_device *dev) |
985 | int intel_guc_suspend(struct drm_device *dev) |
913 | { |
986 | { |
914 | struct drm_i915_private *dev_priv = dev->dev_private; |
987 | struct drm_i915_private *dev_priv = dev->dev_private; |
915 | struct intel_guc *guc = &dev_priv->guc; |
988 | struct intel_guc *guc = &dev_priv->guc; |
916 | struct intel_context *ctx; |
989 | struct intel_context *ctx; |
917 | u32 data[3]; |
990 | u32 data[3]; |
918 | 991 | ||
919 | if (!i915.enable_guc_submission) |
992 | if (!i915.enable_guc_submission) |
920 | return 0; |
993 | return 0; |
921 | 994 | ||
922 | ctx = dev_priv->ring[RCS].default_context; |
995 | ctx = dev_priv->kernel_context; |
923 | 996 | ||
924 | data[0] = HOST2GUC_ACTION_ENTER_S_STATE; |
997 | data[0] = HOST2GUC_ACTION_ENTER_S_STATE; |
925 | /* any value greater than GUC_POWER_D0 */ |
998 | /* any value greater than GUC_POWER_D0 */ |
926 | data[1] = GUC_POWER_D1; |
999 | data[1] = GUC_POWER_D1; |
927 | /* first page is shared data with GuC */ |
1000 | /* first page is shared data with GuC */ |
928 | data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); |
1001 | data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); |
929 | 1002 | ||
930 | return host2guc_action(guc, data, ARRAY_SIZE(data)); |
1003 | return host2guc_action(guc, data, ARRAY_SIZE(data)); |
931 | } |
1004 | } |
932 | 1005 | ||
933 | 1006 | ||
934 | /** |
1007 | /** |
935 | * intel_guc_resume() - notify GuC resuming from suspend state |
1008 | * intel_guc_resume() - notify GuC resuming from suspend state |
936 | * @dev: drm device |
1009 | * @dev: drm device |
937 | */ |
1010 | */ |
938 | int intel_guc_resume(struct drm_device *dev) |
1011 | int intel_guc_resume(struct drm_device *dev) |
939 | { |
1012 | { |
940 | struct drm_i915_private *dev_priv = dev->dev_private; |
1013 | struct drm_i915_private *dev_priv = dev->dev_private; |
941 | struct intel_guc *guc = &dev_priv->guc; |
1014 | struct intel_guc *guc = &dev_priv->guc; |
942 | struct intel_context *ctx; |
1015 | struct intel_context *ctx; |
943 | u32 data[3]; |
1016 | u32 data[3]; |
944 | 1017 | ||
945 | if (!i915.enable_guc_submission) |
1018 | if (!i915.enable_guc_submission) |
946 | return 0; |
1019 | return 0; |
947 | 1020 | ||
948 | ctx = dev_priv->ring[RCS].default_context; |
1021 | ctx = dev_priv->kernel_context; |
949 | 1022 | ||
950 | data[0] = HOST2GUC_ACTION_EXIT_S_STATE; |
1023 | data[0] = HOST2GUC_ACTION_EXIT_S_STATE; |
951 | data[1] = GUC_POWER_D0; |
1024 | data[1] = GUC_POWER_D0; |
952 | /* first page is shared data with GuC */ |
1025 | /* first page is shared data with GuC */ |
953 | data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); |
1026 | data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); |
954 | 1027 | ||
955 | return host2guc_action(guc, data, ARRAY_SIZE(data)); |
1028 | return host2guc_action(guc, data, ARRAY_SIZE(data)); |
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