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#ifndef _I915_GUC_REG_H_
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#ifndef _I915_GUC_REG_H_
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#define _I915_GUC_REG_H_
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#define _I915_GUC_REG_H_
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/* Definitions of GuC H/W registers, bits, etc */
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/* Definitions of GuC H/W registers, bits, etc */
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#define GUC_STATUS			0xc000
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#define GUC_STATUS			_MMIO(0xc000)
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#define   GS_BOOTROM_SHIFT		1
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#define   GS_BOOTROM_SHIFT		1
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#define   GS_BOOTROM_MASK		  (0x7F << GS_BOOTROM_SHIFT)
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#define   GS_BOOTROM_MASK		  (0x7F << GS_BOOTROM_SHIFT)
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#define   GS_BOOTROM_RSA_FAILED		  (0x50 << GS_BOOTROM_SHIFT)
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#define   GS_BOOTROM_RSA_FAILED		  (0x50 << GS_BOOTROM_SHIFT)
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#define   GS_UKERNEL_READY		  (0xF0 << GS_UKERNEL_SHIFT)
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#define   GS_UKERNEL_READY		  (0xF0 << GS_UKERNEL_SHIFT)
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#define   GS_MIA_SHIFT			16
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#define   GS_MIA_SHIFT			16
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#define   GS_MIA_MASK			  (0x07 << GS_MIA_SHIFT)
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#define   GS_MIA_MASK			  (0x07 << GS_MIA_SHIFT)
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#define   GS_MIA_CORE_STATE		  (1 << GS_MIA_SHIFT)
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#define   GS_MIA_CORE_STATE		  (1 << GS_MIA_SHIFT)
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#define SOFT_SCRATCH(n)			(0xc180 + ((n) * 4))
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#define SOFT_SCRATCH(n)			_MMIO(0xc180 + (n) * 4)
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#define UOS_RSA_SCRATCH(i)		_MMIO(0xc200 + (i) * 4)
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#define UOS_RSA_SCRATCH(i)		(0xc200 + (i) * 4)
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#define   UOS_RSA_SCRATCH_MAX_COUNT	  64
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#define DMA_ADDR_0_LOW			0xc300
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#define DMA_ADDR_0_LOW			_MMIO(0xc300)
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#define DMA_ADDR_0_HIGH			0xc304
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#define DMA_ADDR_0_HIGH			_MMIO(0xc304)
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#define DMA_ADDR_1_LOW			0xc308
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#define DMA_ADDR_1_LOW			_MMIO(0xc308)
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#define DMA_ADDR_1_HIGH			0xc30c
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#define DMA_ADDR_1_HIGH			_MMIO(0xc30c)
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#define   DMA_ADDRESS_SPACE_WOPCM	  (7 << 16)
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#define   DMA_ADDRESS_SPACE_WOPCM	  (7 << 16)
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#define   DMA_ADDRESS_SPACE_GTT		  (8 << 16)
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#define   DMA_ADDRESS_SPACE_GTT		  (8 << 16)
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#define DMA_COPY_SIZE			0xc310
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#define DMA_COPY_SIZE			_MMIO(0xc310)
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#define DMA_CTRL			0xc314
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#define DMA_CTRL			_MMIO(0xc314)
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#define   UOS_MOVE			  (1<<4)
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#define   UOS_MOVE			  (1<<4)
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#define   START_DMA			  (1<<0)
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#define   START_DMA			  (1<<0)
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#define DMA_GUC_WOPCM_OFFSET		0xc340
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#define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
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#define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
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#define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
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#define GUC_MAX_IDLE_COUNT		0xC3E4
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#define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
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#define GUC_WOPCM_SIZE			0xc050
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#define GUC_WOPCM_SIZE			_MMIO(0xc050)
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#define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
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#define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
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/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
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/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
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#define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)
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#define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)
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#define GEN8_GT_PM_CONFIG		0x138140
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#define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
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#define GEN9LP_GT_PM_CONFIG		0x138140
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#define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
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#define GEN9_GT_PM_CONFIG		0x13816c
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#define GEN9_GT_PM_CONFIG		_MMIO(0x13816c)
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#define   GT_DOORBELL_ENABLE		  (1<<0)
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#define   GT_DOORBELL_ENABLE		  (1<<0)
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#define GEN8_GTCR			0x4274
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#define GEN8_GTCR			_MMIO(0x4274)
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#define   GEN8_GTCR_INVALIDATE		  (1<<0)
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#define   GEN8_GTCR_INVALIDATE		  (1<<0)
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				 GUC_ENABLE_MIA_CACHING			| \
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				 GUC_ENABLE_MIA_CACHING			| \
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				 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA	| \
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				 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA	| \
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				 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA	| \
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				 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA	| \
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				 GUC_ENABLE_MIA_CLOCK_GATING)
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				 GUC_ENABLE_MIA_CLOCK_GATING)
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#define HOST2GUC_INTERRUPT		0xc4c8
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#define HOST2GUC_INTERRUPT		_MMIO(0xc4c8)
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#define   HOST2GUC_TRIGGER		  (1<<0)
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#define   HOST2GUC_TRIGGER		  (1<<0)
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#define DRBMISC1			0x1984
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#define DRBMISC1			0x1984
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#define   DOORBELL_ENABLE		  (1<<0)
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#define   DOORBELL_ENABLE		  (1<<0)
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#define GEN8_DRBREGL(x)			(0x1000 + (x) * 8)
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#define GEN8_DRBREGL(x)			_MMIO(0x1000 + (x) * 8)
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#define   GEN8_DRB_VALID		  (1<<0)
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#define   GEN8_DRB_VALID		  (1<<0)
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#define GEN8_DRBREGU(x)			(GEN8_DRBREGL(x) + 4)
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#define GEN8_DRBREGU(x)			_MMIO(0x1000 + (x) * 8 + 4)
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#define DE_GUCRMR			0x44054
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#define DE_GUCRMR			_MMIO(0x44054)
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