WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_gem_gtt.c


/*
 * Copyright © 2010 Daniel Vetter
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */
 
 
#define AGP_NORMAL_MEMORY 0
 
#define AGP_USER_TYPES (1 << 16)
#define AGP_USER_MEMORY (AGP_USER_TYPES)
#define AGP_USER_CACHED_MEMORY (AGP_USER_TYPES + 1)
 
#include 
#include 
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"
 
typedef uint32_t gen6_gtt_pte_t;
 
/* PPGTT stuff */
#define GEN6_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0xff0))
 
#define GEN6_PDE_VALID			(1 << 0)
/* gen6+ has bit 11-4 for physical addr bit 39-32 */
#define GEN6_PDE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
 
#define GEN6_PTE_VALID			(1 << 0)
#define GEN6_PTE_UNCACHED		(1 << 1)
#define HSW_PTE_UNCACHED		(0)
#define GEN6_PTE_CACHE_LLC		(2 << 1)
#define GEN6_PTE_CACHE_LLC_MLC		(3 << 1)
#define GEN6_PTE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
 
static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
				   dma_addr_t addr,
				   enum i915_cache_level level)
{
	gen6_gtt_pte_t pte = GEN6_PTE_VALID;
	pte |= GEN6_PTE_ADDR_ENCODE(addr);
 
	switch (level) {
	case I915_CACHE_LLC_MLC:
		/* Haswell doesn't set L3 this way */
		if (IS_HASWELL(dev))
			pte |= GEN6_PTE_CACHE_LLC;
		else
			pte |= GEN6_PTE_CACHE_LLC_MLC;
		break;
	case I915_CACHE_LLC:
		pte |= GEN6_PTE_CACHE_LLC;
		break;
	case I915_CACHE_NONE:
		if (IS_HASWELL(dev))
			pte |= HSW_PTE_UNCACHED;
		else
			pte |= GEN6_PTE_UNCACHED;
		break;
	default:
		BUG();
	}
 
	return pte;
}
 
static int gen6_ppgtt_enable(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	uint32_t pd_offset;
	struct intel_ring_buffer *ring;
	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
	gen6_gtt_pte_t __iomem *pd_addr;
	uint32_t pd_entry;
	int i;
 
	pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
		ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
	for (i = 0; i < ppgtt->num_pd_entries; i++) {
		dma_addr_t pt_addr;
 
		pt_addr = ppgtt->pt_dma_addr[i];
		pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
		pd_entry |= GEN6_PDE_VALID;
 
		writel(pd_entry, pd_addr + i);
	}
	readl(pd_addr);
 
	pd_offset = ppgtt->pd_offset;
	pd_offset /= 64; /* in cachelines, */
	pd_offset <<= 16;
 
	if (INTEL_INFO(dev)->gen == 6) {
		uint32_t ecochk, gab_ctl, ecobits;
 
		ecobits = I915_READ(GAC_ECO_BITS);
		I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
					 ECOBITS_PPGTT_CACHE64B);
 
		gab_ctl = I915_READ(GAB_CTL);
		I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 
		ecochk = I915_READ(GAM_ECOCHK);
		I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
				       ECOCHK_PPGTT_CACHE64B);
		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
	} else if (INTEL_INFO(dev)->gen >= 7) {
		uint32_t ecochk, ecobits;
 
		ecobits = I915_READ(GAC_ECO_BITS);
		I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 
		ecochk = I915_READ(GAM_ECOCHK);
		if (IS_HASWELL(dev)) {
			ecochk |= ECOCHK_PPGTT_WB_HSW;
		} else {
			ecochk |= ECOCHK_PPGTT_LLC_IVB;
			ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
		}
		I915_WRITE(GAM_ECOCHK, ecochk);
		/* GFX_MODE is per-ring on gen7+ */
	}
 
	for_each_ring(ring, dev_priv, i) {
		if (INTEL_INFO(dev)->gen >= 7)
			I915_WRITE(RING_MODE_GEN7(ring),
				   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 
		I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
		I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
	}
	return 0;
}
 
/* PPGTT support for Sandybdrige/Gen6 and later */
static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
				   unsigned first_entry,
				   unsigned num_entries)
{
	gen6_gtt_pte_t *pt_vaddr, scratch_pte;
	unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
	unsigned last_pte, i;
 
	scratch_pte = gen6_pte_encode(ppgtt->dev,
				      ppgtt->scratch_page_dma_addr,
				 I915_CACHE_LLC);
 
    pt_vaddr = AllocKernelSpace(4096);
 
    if(pt_vaddr == NULL)
        return;
 
	while (num_entries) {
            last_pte = first_pte + num_entries;
            if (last_pte > I915_PPGTT_PT_ENTRIES)
                last_pte = I915_PPGTT_PT_ENTRIES;
 
            MapPage(pt_vaddr,(addr_t)(ppgtt->pt_pages[act_pt]), 3);
 
            for (i = first_pte; i < last_pte; i++)
                pt_vaddr[i] = scratch_pte;
 
            num_entries -= last_pte - first_pte;
            first_pte = 0;
            act_pt++;
    };
 
    FreeKernelSpace(pt_vaddr);
}
 
static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
				      struct sg_table *pages,
				      unsigned first_entry,
				      enum i915_cache_level cache_level)
{
	gen6_gtt_pte_t *pt_vaddr;
	unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
	unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
	struct sg_page_iter sg_iter;
	dma_addr_t page_addr;
 
 
    pt_vaddr = AllocKernelSpace(4096);
 
    if(pt_vaddr == NULL)
        return;
 
    MapPage(pt_vaddr,(addr_t)(ppgtt->pt_pages[act_pt]), 3);
	for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
		dma_addr_t page_addr;
 
		page_addr = sg_page_iter_dma_address(&sg_iter);
		pt_vaddr[act_pte] = gen6_pte_encode(ppgtt->dev, page_addr,
						      cache_level);
		if (++act_pte == I915_PPGTT_PT_ENTRIES) {
			act_pt++;
    		MapPage(pt_vaddr,(addr_t)(ppgtt->pt_pages[act_pt]), 3);
			act_pte = 0;
 
		}
        }
        FreeKernelSpace(pt_vaddr);
}
 
static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)
{
	int i;
 
	if (ppgtt->pt_dma_addr) {
		for (i = 0; i < ppgtt->num_pd_entries; i++)
			pci_unmap_page(ppgtt->dev->pdev,
				       ppgtt->pt_dma_addr[i],
				       4096, PCI_DMA_BIDIRECTIONAL);
	}
 
	kfree(ppgtt->pt_dma_addr);
	for (i = 0; i < ppgtt->num_pd_entries; i++)
		__free_page(ppgtt->pt_pages[i]);
	kfree(ppgtt->pt_pages);
	kfree(ppgtt);
}
 
static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
{
	struct drm_device *dev = ppgtt->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned first_pd_entry_in_global_pt;
	int i;
	int ret = -ENOMEM;
 
	/* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
	 * entries. For aliasing ppgtt support we just steal them at the end for
	 * now. */
       first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt);
 
	ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
	ppgtt->enable = gen6_ppgtt_enable;
	ppgtt->clear_range = gen6_ppgtt_clear_range;
	ppgtt->insert_entries = gen6_ppgtt_insert_entries;
	ppgtt->cleanup = gen6_ppgtt_cleanup;
	ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
				  GFP_KERNEL);
	if (!ppgtt->pt_pages)
		return -ENOMEM;
 
	for (i = 0; i < ppgtt->num_pd_entries; i++) {
		ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
		if (!ppgtt->pt_pages[i])
			goto err_pt_alloc;
	}
 
	ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
					     GFP_KERNEL);
		if (!ppgtt->pt_dma_addr)
			goto err_pt_alloc;
 
		for (i = 0; i < ppgtt->num_pd_entries; i++) {
			dma_addr_t pt_addr;
 
		pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
					       PCI_DMA_BIDIRECTIONAL);
 
			ppgtt->pt_dma_addr[i] = pt_addr;
		}
 
	ppgtt->clear_range(ppgtt, 0,
			       ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
 
	ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
 
	return 0;
 
err_pd_pin:
	if (ppgtt->pt_dma_addr) {
		for (i--; i >= 0; i--)
			pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
				       4096, PCI_DMA_BIDIRECTIONAL);
	}
err_pt_alloc:
	kfree(ppgtt->pt_dma_addr);
	for (i = 0; i < ppgtt->num_pd_entries; i++) {
		if (ppgtt->pt_pages[i])
			__free_page(ppgtt->pt_pages[i]);
	}
	kfree(ppgtt->pt_pages);
 
	return ret;
}
 
static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct i915_hw_ppgtt *ppgtt;
	int ret;
 
	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
	if (!ppgtt)
		return -ENOMEM;
 
	ppgtt->dev = dev;
	ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma;
 
	if (INTEL_INFO(dev)->gen < 8)
	ret = gen6_ppgtt_init(ppgtt);
	else
		BUG();
 
	if (ret)
	kfree(ppgtt);
	else
		dev_priv->mm.aliasing_ppgtt = ppgtt;
 
	return ret;
}
 
void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 
	if (!ppgtt)
		return;
 
	ppgtt->cleanup(ppgtt);
	dev_priv->mm.aliasing_ppgtt = NULL;
}
 
void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
			    struct drm_i915_gem_object *obj,
			    enum i915_cache_level cache_level)
{
	ppgtt->insert_entries(ppgtt, obj->pages,
				     obj->gtt_space->start >> PAGE_SHIFT,
				     cache_level);
}
 
void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
			      struct drm_i915_gem_object *obj)
{
	ppgtt->clear_range(ppgtt,
			       obj->gtt_space->start >> PAGE_SHIFT,
			       obj->base.size >> PAGE_SHIFT);
}
 
extern int intel_iommu_gfx_mapped;
/* Certain Gen5 chipsets require require idling the GPU before
 * unmapping anything from the GTT when VT-d is enabled.
 */
static inline bool needs_idle_maps(struct drm_device *dev)
{
#ifdef CONFIG_INTEL_IOMMU
	/* Query intel_iommu to see if we need the workaround. Presumably that
	 * was loaded first.
	 */
	if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
		return true;
#endif
	return false;
}
 
static bool do_idling(struct drm_i915_private *dev_priv)
{
	bool ret = dev_priv->mm.interruptible;
 
	if (unlikely(dev_priv->gtt.do_idle_maps)) {
		dev_priv->mm.interruptible = false;
		if (i915_gpu_idle(dev_priv->dev)) {
			DRM_ERROR("Couldn't idle GPU\n");
			/* Wait a bit, in hopes it avoids the hang */
			udelay(10);
		}
	}
 
	return ret;
}
 
static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
{
	if (unlikely(dev_priv->gtt.do_idle_maps))
		dev_priv->mm.interruptible = interruptible;
}
 
void i915_gem_restore_gtt_mappings(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
 
	/* First fill our portion of the GTT with scratch pages */
	dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
				      dev_priv->gtt.total / PAGE_SIZE);
 
	list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
		i915_gem_clflush_object(obj);
		i915_gem_gtt_bind_object(obj, obj->cache_level);
	}
 
	i915_gem_chipset_flush(dev);
}
 
int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
{
	if (obj->has_dma_mapping)
		return 0;
 
	if (!dma_map_sg(&obj->base.dev->pdev->dev,
			obj->pages->sgl, obj->pages->nents,
			PCI_DMA_BIDIRECTIONAL))
		return -ENOSPC;
 
	return 0;
}
 
/*
 * Binds an object into the global gtt with the specified cache level. The object
 * will be accessible to the GPU via commands whose operands reference offsets
 * within the global GTT as well as accessible by the GPU through the GMADR
 * mapped BAR (dev_priv->mm.gtt->gtt).
 */
static void gen6_ggtt_insert_entries(struct drm_device *dev,
				     struct sg_table *st,
				     unsigned int first_entry,
				  enum i915_cache_level level)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	gen6_gtt_pte_t __iomem *gtt_entries =
		(gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
	int i = 0;
	struct sg_page_iter sg_iter;
	dma_addr_t addr;
 
	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
		addr = sg_page_iter_dma_address(&sg_iter);
		iowrite32(gen6_pte_encode(dev, addr, level), >t_entries[i]);
			i++;
		}
 
	/* XXX: This serves as a posting read to make sure that the PTE has
	 * actually been updated. There is some concern that even though
	 * registers and PTEs are within the same BAR that they are potentially
	 * of NUMA access patterns. Therefore, even with the way we assume
	 * hardware should work, we must keep this posting read for paranoia.
	 */
	if (i != 0)
		WARN_ON(readl(>t_entries[i-1])
			!= gen6_pte_encode(dev, addr, level));
 
	/* This next bit makes the above posting read even more important. We
	 * want to flush the TLBs only after we're certain all the PTE updates
	 * have finished.
	 */
	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
	POSTING_READ(GFX_FLSH_CNTL_GEN6);
}
 
static void gen6_ggtt_clear_range(struct drm_device *dev,
				  unsigned int first_entry,
				  unsigned int num_entries)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
		(gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
	const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
	int i;
 
//   if (WARN(num_entries > max_entries,
//        "First entry = %d; Num entries = %d (max=%d)\n",
//        first_entry, num_entries, max_entries))
   if (num_entries > max_entries)
		num_entries = max_entries;
 
	scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma,
				      I915_CACHE_LLC);
	for (i = 0; i < num_entries; i++)
		iowrite32(scratch_pte, >t_base[i]);
	readl(gtt_base);
}
 
 
static void i915_ggtt_insert_entries(struct drm_device *dev,
				     struct sg_table *st,
				     unsigned int pg_start,
				     enum i915_cache_level cache_level)
{
	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 
	intel_gtt_insert_sg_entries(st, pg_start, flags);
 
}
 
static void i915_ggtt_clear_range(struct drm_device *dev,
				  unsigned int first_entry,
				  unsigned int num_entries)
{
	intel_gtt_clear_range(first_entry, num_entries);
}
 
 
void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
				enum i915_cache_level cache_level)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
 
	dev_priv->gtt.gtt_insert_entries(dev, obj->pages,
					    obj->gtt_space->start >> PAGE_SHIFT,
					 cache_level);
 
	obj->has_global_gtt_mapping = 1;
}
 
void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
 
	dev_priv->gtt.gtt_clear_range(obj->base.dev,
			      obj->gtt_space->start >> PAGE_SHIFT,
			      obj->base.size >> PAGE_SHIFT);
 
	obj->has_global_gtt_mapping = 0;
}
 
void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	bool interruptible;
 
	interruptible = do_idling(dev_priv);
 
	if (!obj->has_dma_mapping)
		dma_unmap_sg(&dev->pdev->dev,
			     obj->pages->sgl, obj->pages->nents,
			     PCI_DMA_BIDIRECTIONAL);
 
	undo_idling(dev_priv, interruptible);
}
 
static void i915_gtt_color_adjust(struct drm_mm_node *node,
				  unsigned long color,
				  unsigned long *start,
				  unsigned long *end)
{
	if (node->color != color)
		*start += 4096;
 
	if (!list_empty(&node->node_list)) {
		node = list_entry(node->node_list.next,
				  struct drm_mm_node,
				  node_list);
		if (node->allocated && node->color != color)
			*end -= 4096;
	}
}
void i915_gem_setup_global_gtt(struct drm_device *dev,
			      unsigned long start,
			      unsigned long mappable_end,
			      unsigned long end)
{
	/* Let GEM Manage all of the aperture.
	 *
	 * However, leave one page at the end still bound to the scratch page.
	 * There are a number of places where the hardware apparently prefetches
	 * past the end of the object, and we've seen multiple hangs with the
	 * GPU head pointer stuck in a batchbuffer bound at the last page of the
	 * aperture.  One page should be enough to keep any prefetching inside
	 * of the aperture.
	 */
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_mm_node *entry;
	struct drm_i915_gem_object *obj;
	unsigned long hole_start, hole_end;
 
	BUG_ON(mappable_end > end);
 
	/* Subtract the guard page ... */
	drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
	if (!HAS_LLC(dev))
		dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
 
	/* Mark any preallocated objects as occupied */
	list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
		DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
			      obj->gtt_offset, obj->base.size);
 
		BUG_ON(obj->gtt_space != I915_GTT_RESERVED);
		obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space,
						     obj->gtt_offset,
						     obj->base.size,
						     false);
		obj->has_global_gtt_mapping = 1;
	}
 
	dev_priv->gtt.start = start;
	dev_priv->gtt.total = end - start;
 
	/* Clear any non-preallocated blocks */
	drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space,
			     hole_start, hole_end) {
		DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
			      hole_start, hole_end);
		dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE,
					      (hole_end-hole_start) / PAGE_SIZE);
	}
 
	/* And finally clear the reserved guard page */
	dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1);
}
 
static bool
intel_enable_ppgtt(struct drm_device *dev)
{
	if (i915_enable_ppgtt >= 0)
		return i915_enable_ppgtt;
 
#ifdef CONFIG_INTEL_IOMMU
	/* Disable ppgtt on SNB if VT-d is on. */
	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
		return false;
#endif
 
	return true;
}
 
void i915_gem_init_global_gtt(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long gtt_size, mappable_size;
 
	gtt_size = dev_priv->gtt.total;
	mappable_size = dev_priv->gtt.mappable_end;
 
#if 0
	if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
		int ret;
 
		if (INTEL_INFO(dev)->gen <= 7) {
		/* PPGTT pdes are stolen from global gtt ptes, so shrink the
		 * aperture accordingly when using aliasing ppgtt. */
        gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
		}
 
 
 
        i915_gem_setup_global_gtt(dev, LFB_SIZE, mappable_size, gtt_size);
 
		ret = i915_gem_init_aliasing_ppgtt(dev);
		if (!ret)
			return;
 
		DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
		drm_mm_takedown(&dev_priv->mm.gtt_space);
		gtt_size += I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
}
#endif
 
    i915_gem_setup_global_gtt(dev, LFB_SIZE, mappable_size, gtt_size);
}
 
static int setup_scratch_page(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct page *page;
	dma_addr_t dma_addr;
 
	page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
	if (page == NULL)
		return -ENOMEM;
	get_page(page);
	set_pages_uc(page, 1);
 
#ifdef CONFIG_INTEL_IOMMU
	dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
				PCI_DMA_BIDIRECTIONAL);
	if (pci_dma_mapping_error(dev->pdev, dma_addr))
		return -EINVAL;
#else
	dma_addr = page_to_phys(page);
#endif
	dev_priv->gtt.scratch_page = page;
	dev_priv->gtt.scratch_page_dma = dma_addr;
 
	return 0;
}
 
static void teardown_scratch_page(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	set_pages_wb(dev_priv->gtt.scratch_page, 1);
	pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma,
		       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
	put_page(dev_priv->gtt.scratch_page);
	__free_page(dev_priv->gtt.scratch_page);
}
 
static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
{
	snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
	snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
	return snb_gmch_ctl << 20;
}
 
static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
{
	snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
	snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
	return snb_gmch_ctl << 25; /* 32 MB units */
}
 
static int gen6_gmch_probe(struct drm_device *dev,
			   size_t *gtt_total,
			   size_t *stolen,
			   phys_addr_t *mappable_base,
			   unsigned long *mappable_end)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	phys_addr_t gtt_bus_addr;
	unsigned int gtt_size;
	u16 snb_gmch_ctl;
	int ret;
 
	*mappable_base = pci_resource_start(dev->pdev, 2);
	*mappable_end = pci_resource_len(dev->pdev, 2);
 
	/* 64/512MB is the current min/max we actually know of, but this is just
	 * a coarse sanity check.
	 */
	if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
		DRM_ERROR("Unknown GMADR size (%lx)\n",
			  dev_priv->gtt.mappable_end);
		return -ENXIO;
		}
 
	if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
		pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
	gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
 
		*stolen = gen6_get_stolen_size(snb_gmch_ctl);
	*gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
 
	/* For Modern GENs the PTEs and register space are split in the BAR */
	gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
		(pci_resource_len(dev->pdev, 0) / 2);
 
	dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
	if (!dev_priv->gtt.gsm) {
		DRM_ERROR("Failed to map the gtt page table\n");
		return -ENOMEM;
	}
 
	ret = setup_scratch_page(dev);
	if (ret)
		DRM_ERROR("Scratch setup failed\n");
 
	dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range;
	dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries;
 
	return ret;
}
 
static void gen6_gmch_remove(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	iounmap(dev_priv->gtt.gsm);
	teardown_scratch_page(dev_priv->dev);
}
 
static int i915_gmch_probe(struct drm_device *dev,
			   size_t *gtt_total,
			   size_t *stolen,
			   phys_addr_t *mappable_base,
			   unsigned long *mappable_end)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;
 
	ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
	if (!ret) {
		DRM_ERROR("failed to set up gmch\n");
		return -EIO;
	}
 
	intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
 
	dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
	dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range;
	dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries;
 
	return 0;
}
 
static void i915_gmch_remove(struct drm_device *dev)
{
//   intel_gmch_remove();
}
 
int i915_gem_gtt_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct i915_gtt *gtt = &dev_priv->gtt;
	int ret;
 
	if (INTEL_INFO(dev)->gen <= 5) {
		dev_priv->gtt.gtt_probe = i915_gmch_probe;
		dev_priv->gtt.gtt_remove = i915_gmch_remove;
	} else {
		dev_priv->gtt.gtt_probe = gen6_gmch_probe;
		dev_priv->gtt.gtt_remove = gen6_gmch_remove;
	}
 
	ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
				     &dev_priv->gtt.stolen_size,
				     >t->mappable_base,
				     >t->mappable_end);
	if (ret)
	return ret;
 
	/* GMADR is the PCI mmio aperture into the global GTT. */
	DRM_INFO("Memory usable by graphics device = %zdM\n",
		 dev_priv->gtt.total >> 20);
	DRM_DEBUG_DRIVER("GMADR size = %ldM\n",
			 dev_priv->gtt.mappable_end >> 20);
	DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n",
			 dev_priv->gtt.stolen_size >> 20);
 
	return 0;
}
 
struct scatterlist *sg_next(struct scatterlist *sg)
{
    if (sg_is_last(sg))
        return NULL;
 
    sg++;
    if (unlikely(sg_is_chain(sg)))
            sg = sg_chain_ptr(sg);
 
    return sg;
}
 
 
void __sg_free_table(struct sg_table *table, unsigned int max_ents,
                     sg_free_fn *free_fn)
{
    struct scatterlist *sgl, *next;
 
    if (unlikely(!table->sgl))
            return;
 
    sgl = table->sgl;
    while (table->orig_nents) {
        unsigned int alloc_size = table->orig_nents;
        unsigned int sg_size;
 
        /*
         * If we have more than max_ents segments left,
         * then assign 'next' to the sg table after the current one.
         * sg_size is then one less than alloc size, since the last
         * element is the chain pointer.
         */
        if (alloc_size > max_ents) {
                next = sg_chain_ptr(&sgl[max_ents - 1]);
                alloc_size = max_ents;
                sg_size = alloc_size - 1;
        } else {
                sg_size = alloc_size;
                next = NULL;
        }
 
        table->orig_nents -= sg_size;
        kfree(sgl);
        sgl = next;
    }
 
    table->sgl = NULL;
}
 
void sg_free_table(struct sg_table *table)
{
    __sg_free_table(table, SG_MAX_SINGLE_ALLOC, NULL);
}
 
int sg_alloc_table(struct sg_table *table, unsigned int nents, gfp_t gfp_mask)
{
    struct scatterlist *sg, *prv;
    unsigned int left;
    unsigned int max_ents = SG_MAX_SINGLE_ALLOC;
 
#ifndef ARCH_HAS_SG_CHAIN
    BUG_ON(nents > max_ents);
#endif
 
    memset(table, 0, sizeof(*table));
 
    left = nents;
    prv = NULL;
    do {
        unsigned int sg_size, alloc_size = left;
 
        if (alloc_size > max_ents) {
                alloc_size = max_ents;
                sg_size = alloc_size - 1;
        } else
                sg_size = alloc_size;
 
        left -= sg_size;
 
        sg = kmalloc(alloc_size * sizeof(struct scatterlist), gfp_mask);
        if (unlikely(!sg)) {
                /*
                 * Adjust entry count to reflect that the last
                 * entry of the previous table won't be used for
                 * linkage.  Without this, sg_kfree() may get
                 * confused.
                 */
                if (prv)
                        table->nents = ++table->orig_nents;
 
                goto err;
        }
 
        sg_init_table(sg, alloc_size);
        table->nents = table->orig_nents += sg_size;
 
        /*
         * If this is the first mapping, assign the sg table header.
         * If this is not the first mapping, chain previous part.
         */
        if (prv)
                sg_chain(prv, max_ents, sg);
        else
                table->sgl = sg;
 
        /*
         * If no more entries after this one, mark the end
         */
        if (!left)
                sg_mark_end(&sg[sg_size - 1]);
 
        prv = sg;
    } while (left);
 
    return 0;
 
err:
    __sg_free_table(table, SG_MAX_SINGLE_ALLOC, NULL);
 
    return -ENOMEM;
}
 
 
void sg_init_table(struct scatterlist *sgl, unsigned int nents)
{
    memset(sgl, 0, sizeof(*sgl) * nents);
#ifdef CONFIG_DEBUG_SG
    {
            unsigned int i;
            for (i = 0; i < nents; i++)
                    sgl[i].sg_magic = SG_MAGIC;
    }
#endif
    sg_mark_end(&sgl[nents - 1]);
}
 
 
void __sg_page_iter_start(struct sg_page_iter *piter,
              struct scatterlist *sglist, unsigned int nents,
              unsigned long pgoffset)
{
    piter->__pg_advance = 0;
    piter->__nents = nents;
 
    piter->sg = sglist;
    piter->sg_pgoffset = pgoffset;
}
 
static int sg_page_count(struct scatterlist *sg)
{
    return PAGE_ALIGN(sg->offset + sg->length) >> PAGE_SHIFT;
}
 
bool __sg_page_iter_next(struct sg_page_iter *piter)
{
    if (!piter->__nents || !piter->sg)
        return false;
 
    piter->sg_pgoffset += piter->__pg_advance;
    piter->__pg_advance = 1;
 
    while (piter->sg_pgoffset >= sg_page_count(piter->sg)) {
        piter->sg_pgoffset -= sg_page_count(piter->sg);
        piter->sg = sg_next(piter->sg);
        if (!--piter->__nents || !piter->sg)
            return false;
    }
 
    return true;
}
EXPORT_SYMBOL(__sg_page_iter_next);

Rev 3746	Rev 3764
1	/*	1	/*
2	* Copyright © 2010 Daniel Vetter	2	* Copyright © 2010 Daniel Vetter
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice (including the next	11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the	12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.	13	* Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21	* IN THE SOFTWARE.	21	* IN THE SOFTWARE.
22	*	22	*
23	*/	23	*/
24		24
25		25
26	#define AGP_NORMAL_MEMORY 0	26	#define AGP_NORMAL_MEMORY 0
27		27
28	#define AGP_USER_TYPES (1 << 16)	28	#define AGP_USER_TYPES (1 << 16)
29	#define AGP_USER_MEMORY (AGP_USER_TYPES)	29	#define AGP_USER_MEMORY (AGP_USER_TYPES)
30	#define AGP_USER_CACHED_MEMORY (AGP_USER_TYPES + 1)	30	#define AGP_USER_CACHED_MEMORY (AGP_USER_TYPES + 1)
31		31
32	#include	32	#include
33	#include	33	#include
34	#include "i915_drv.h"	34	#include "i915_drv.h"
35	#include "i915_trace.h"	35	#include "i915_trace.h"
36	#include "intel_drv.h"	36	#include "intel_drv.h"
37		37
38	typedef uint32_t gen6_gtt_pte_t;	38	typedef uint32_t gen6_gtt_pte_t;
39		39
40	/* PPGTT stuff */	40	/* PPGTT stuff */
41	#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) \| (((addr) >> 28) & 0xff0))	41	#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) \| (((addr) >> 28) & 0xff0))
42		42
43	#define GEN6_PDE_VALID (1 << 0)	43	#define GEN6_PDE_VALID (1 << 0)
44	/* gen6+ has bit 11-4 for physical addr bit 39-32 */	44	/* gen6+ has bit 11-4 for physical addr bit 39-32 */
45	#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)	45	#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
46		46
47	#define GEN6_PTE_VALID (1 << 0)	47	#define GEN6_PTE_VALID (1 << 0)
48	#define GEN6_PTE_UNCACHED (1 << 1)	48	#define GEN6_PTE_UNCACHED (1 << 1)
49	#define HSW_PTE_UNCACHED (0)	49	#define HSW_PTE_UNCACHED (0)
50	#define GEN6_PTE_CACHE_LLC (2 << 1)	50	#define GEN6_PTE_CACHE_LLC (2 << 1)
51	#define GEN6_PTE_CACHE_LLC_MLC (3 << 1)	51	#define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
52	#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)	52	#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
53		53
54	static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,	54	static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
55	dma_addr_t addr,	55	dma_addr_t addr,
56	enum i915_cache_level level)	56	enum i915_cache_level level)
57	{	57	{
58	gen6_gtt_pte_t pte = GEN6_PTE_VALID;	58	gen6_gtt_pte_t pte = GEN6_PTE_VALID;
59	pte \|= GEN6_PTE_ADDR_ENCODE(addr);	59	pte \|= GEN6_PTE_ADDR_ENCODE(addr);
60		60
61	switch (level) {	61	switch (level) {
62	case I915_CACHE_LLC_MLC:	62	case I915_CACHE_LLC_MLC:
63	/* Haswell doesn't set L3 this way */	63	/* Haswell doesn't set L3 this way */
64	if (IS_HASWELL(dev))	64	if (IS_HASWELL(dev))
65	pte \|= GEN6_PTE_CACHE_LLC;	65	pte \|= GEN6_PTE_CACHE_LLC;
66	else	66	else
67	pte \|= GEN6_PTE_CACHE_LLC_MLC;	67	pte \|= GEN6_PTE_CACHE_LLC_MLC;
68	break;	68	break;
69	case I915_CACHE_LLC:	69	case I915_CACHE_LLC:
70	pte \|= GEN6_PTE_CACHE_LLC;	70	pte \|= GEN6_PTE_CACHE_LLC;
71	break;	71	break;
72	case I915_CACHE_NONE:	72	case I915_CACHE_NONE:
73	if (IS_HASWELL(dev))	73	if (IS_HASWELL(dev))
74	pte \|= HSW_PTE_UNCACHED;	74	pte \|= HSW_PTE_UNCACHED;
75	else	75	else
76	pte \|= GEN6_PTE_UNCACHED;	76	pte \|= GEN6_PTE_UNCACHED;
77	break;	77	break;
78	default:	78	default:
79	BUG();	79	BUG();
80	}	80	}
81		81
82	return pte;	82	return pte;
83	}	83	}
84		84
85	static int gen6_ppgtt_enable(struct drm_device *dev)	85	static int gen6_ppgtt_enable(struct drm_device *dev)
86	{	86	{
87	drm_i915_private_t *dev_priv = dev->dev_private;	87	drm_i915_private_t *dev_priv = dev->dev_private;
88	uint32_t pd_offset;	88	uint32_t pd_offset;
89	struct intel_ring_buffer *ring;	89	struct intel_ring_buffer *ring;
90	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;	90	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
91	gen6_gtt_pte_t __iomem *pd_addr;	91	gen6_gtt_pte_t __iomem *pd_addr;
92	uint32_t pd_entry;	92	uint32_t pd_entry;
93	int i;	93	int i;
94		94
95	pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +	95	pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
96	ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);	96	ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
97	for (i = 0; i < ppgtt->num_pd_entries; i++) {	97	for (i = 0; i < ppgtt->num_pd_entries; i++) {
98	dma_addr_t pt_addr;	98	dma_addr_t pt_addr;
99		99
100	pt_addr = ppgtt->pt_dma_addr[i];	100	pt_addr = ppgtt->pt_dma_addr[i];
101	pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);	101	pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
102	pd_entry \|= GEN6_PDE_VALID;	102	pd_entry \|= GEN6_PDE_VALID;
103		103
104	writel(pd_entry, pd_addr + i);	104	writel(pd_entry, pd_addr + i);
105	}	105	}
106	readl(pd_addr);	106	readl(pd_addr);
107		107
108	pd_offset = ppgtt->pd_offset;	108	pd_offset = ppgtt->pd_offset;
109	pd_offset /= 64; /* in cachelines, */	109	pd_offset /= 64; /* in cachelines, */
110	pd_offset <<= 16;	110	pd_offset <<= 16;
111		111
112	if (INTEL_INFO(dev)->gen == 6) {	112	if (INTEL_INFO(dev)->gen == 6) {
113	uint32_t ecochk, gab_ctl, ecobits;	113	uint32_t ecochk, gab_ctl, ecobits;
114		114
115	ecobits = I915_READ(GAC_ECO_BITS);	115	ecobits = I915_READ(GAC_ECO_BITS);
116	I915_WRITE(GAC_ECO_BITS, ecobits \| ECOBITS_SNB_BIT \|	116	I915_WRITE(GAC_ECO_BITS, ecobits \| ECOBITS_SNB_BIT \|
117	ECOBITS_PPGTT_CACHE64B);	117	ECOBITS_PPGTT_CACHE64B);
118		118
119	gab_ctl = I915_READ(GAB_CTL);	119	gab_ctl = I915_READ(GAB_CTL);
120	I915_WRITE(GAB_CTL, gab_ctl \| GAB_CTL_CONT_AFTER_PAGEFAULT);	120	I915_WRITE(GAB_CTL, gab_ctl \| GAB_CTL_CONT_AFTER_PAGEFAULT);
121		121
122	ecochk = I915_READ(GAM_ECOCHK);	122	ecochk = I915_READ(GAM_ECOCHK);
123	I915_WRITE(GAM_ECOCHK, ecochk \| ECOCHK_SNB_BIT \|	123	I915_WRITE(GAM_ECOCHK, ecochk \| ECOCHK_SNB_BIT \|
124	ECOCHK_PPGTT_CACHE64B);	124	ECOCHK_PPGTT_CACHE64B);
125	I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));	125	I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
126	} else if (INTEL_INFO(dev)->gen >= 7) {	126	} else if (INTEL_INFO(dev)->gen >= 7) {
127	uint32_t ecochk, ecobits;	127	uint32_t ecochk, ecobits;
128		128
129	ecobits = I915_READ(GAC_ECO_BITS);	129	ecobits = I915_READ(GAC_ECO_BITS);
130	I915_WRITE(GAC_ECO_BITS, ecobits \| ECOBITS_PPGTT_CACHE64B);	130	I915_WRITE(GAC_ECO_BITS, ecobits \| ECOBITS_PPGTT_CACHE64B);
131		131
132	ecochk = I915_READ(GAM_ECOCHK);	132	ecochk = I915_READ(GAM_ECOCHK);
133	if (IS_HASWELL(dev)) {	133	if (IS_HASWELL(dev)) {
134	ecochk \|= ECOCHK_PPGTT_WB_HSW;	134	ecochk \|= ECOCHK_PPGTT_WB_HSW;
135	} else {	135	} else {
136	ecochk \|= ECOCHK_PPGTT_LLC_IVB;	136	ecochk \|= ECOCHK_PPGTT_LLC_IVB;
137	ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;	137	ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
138	}	138	}
139	I915_WRITE(GAM_ECOCHK, ecochk);	139	I915_WRITE(GAM_ECOCHK, ecochk);
140	/* GFX_MODE is per-ring on gen7+ */	140	/* GFX_MODE is per-ring on gen7+ */
141	}	141	}
142		142
143	for_each_ring(ring, dev_priv, i) {	143	for_each_ring(ring, dev_priv, i) {
144	if (INTEL_INFO(dev)->gen >= 7)	144	if (INTEL_INFO(dev)->gen >= 7)
145	I915_WRITE(RING_MODE_GEN7(ring),	145	I915_WRITE(RING_MODE_GEN7(ring),
146	_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));	146	_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
147		147
148	I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);	148	I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
149	I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);	149	I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
150	}	150	}
151	return 0;	151	return 0;
152	}	152	}
153		153
154	/* PPGTT support for Sandybdrige/Gen6 and later */	154	/* PPGTT support for Sandybdrige/Gen6 and later */
155	static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,	155	static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
156	unsigned first_entry,	156	unsigned first_entry,
157	unsigned num_entries)	157	unsigned num_entries)
158	{	158	{
159	gen6_gtt_pte_t *pt_vaddr, scratch_pte;	159	gen6_gtt_pte_t *pt_vaddr, scratch_pte;
160	unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;	160	unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
161	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;	161	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
162	unsigned last_pte, i;	162	unsigned last_pte, i;
163		163
164	scratch_pte = gen6_pte_encode(ppgtt->dev,	164	scratch_pte = gen6_pte_encode(ppgtt->dev,
165	ppgtt->scratch_page_dma_addr,	165	ppgtt->scratch_page_dma_addr,
166	I915_CACHE_LLC);	166	I915_CACHE_LLC);
167		167
168	pt_vaddr = AllocKernelSpace(4096);	168	pt_vaddr = AllocKernelSpace(4096);
169		169
170	if(pt_vaddr == NULL)	170	if(pt_vaddr == NULL)
171	return;	171	return;
172		172
173	while (num_entries) {	173	while (num_entries) {
174	last_pte = first_pte + num_entries;	174	last_pte = first_pte + num_entries;
175	if (last_pte > I915_PPGTT_PT_ENTRIES)	175	if (last_pte > I915_PPGTT_PT_ENTRIES)
176	last_pte = I915_PPGTT_PT_ENTRIES;	176	last_pte = I915_PPGTT_PT_ENTRIES;
177		177
178	MapPage(pt_vaddr,(addr_t)(ppgtt->pt_pages[act_pt]), 3);	178	MapPage(pt_vaddr,(addr_t)(ppgtt->pt_pages[act_pt]), 3);
179		179
180	for (i = first_pte; i < last_pte; i++)	180	for (i = first_pte; i < last_pte; i++)
181	pt_vaddr[i] = scratch_pte;	181	pt_vaddr[i] = scratch_pte;
182		182
183	num_entries -= last_pte - first_pte;	183	num_entries -= last_pte - first_pte;
184	first_pte = 0;	184	first_pte = 0;
185	act_pt++;	185	act_pt++;
186	};	186	};
187		187
188	FreeKernelSpace(pt_vaddr);	188	FreeKernelSpace(pt_vaddr);
189	}	189	}
190		190
191	static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,	191	static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
192	struct sg_table *pages,	192	struct sg_table *pages,
193	unsigned first_entry,	193	unsigned first_entry,
194	enum i915_cache_level cache_level)	194	enum i915_cache_level cache_level)
195	{	195	{
196	gen6_gtt_pte_t *pt_vaddr;	196	gen6_gtt_pte_t *pt_vaddr;
197	unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;	197	unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
198	unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;	198	unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
199	struct sg_page_iter sg_iter;	199	struct sg_page_iter sg_iter;
200	dma_addr_t page_addr;	200	dma_addr_t page_addr;
201		201
202		202
203	pt_vaddr = AllocKernelSpace(4096);	203	pt_vaddr = AllocKernelSpace(4096);
204		204
205	if(pt_vaddr == NULL)	205	if(pt_vaddr == NULL)
206	return;	206	return;
207		207
208	MapPage(pt_vaddr,(addr_t)(ppgtt->pt_pages[act_pt]), 3);	208	MapPage(pt_vaddr,(addr_t)(ppgtt->pt_pages[act_pt]), 3);
209	for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {	209	for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
210	dma_addr_t page_addr;	210	dma_addr_t page_addr;
211		211
212	page_addr = sg_page_iter_dma_address(&sg_iter);	212	page_addr = sg_page_iter_dma_address(&sg_iter);
213	pt_vaddr[act_pte] = gen6_pte_encode(ppgtt->dev, page_addr,	213	pt_vaddr[act_pte] = gen6_pte_encode(ppgtt->dev, page_addr,
214	cache_level);	214	cache_level);
215	if (++act_pte == I915_PPGTT_PT_ENTRIES) {	215	if (++act_pte == I915_PPGTT_PT_ENTRIES) {
216	act_pt++;	216	act_pt++;
217	MapPage(pt_vaddr,(addr_t)(ppgtt->pt_pages[act_pt]), 3);	217	MapPage(pt_vaddr,(addr_t)(ppgtt->pt_pages[act_pt]), 3);
218	act_pte = 0;	218	act_pte = 0;
219		219
220	}	220	}
221	}	221	}
222	FreeKernelSpace(pt_vaddr);	222	FreeKernelSpace(pt_vaddr);
223	}	223	}
224		224
225	static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)	225	static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)
226	{	226	{
227	int i;	227	int i;
228		228
229	if (ppgtt->pt_dma_addr) {	229	if (ppgtt->pt_dma_addr) {
230	for (i = 0; i < ppgtt->num_pd_entries; i++)	230	for (i = 0; i < ppgtt->num_pd_entries; i++)
231	pci_unmap_page(ppgtt->dev->pdev,	231	pci_unmap_page(ppgtt->dev->pdev,
232	ppgtt->pt_dma_addr[i],	232	ppgtt->pt_dma_addr[i],
233	4096, PCI_DMA_BIDIRECTIONAL);	233	4096, PCI_DMA_BIDIRECTIONAL);
234	}	234	}
235		235
236	kfree(ppgtt->pt_dma_addr);	236	kfree(ppgtt->pt_dma_addr);
237	for (i = 0; i < ppgtt->num_pd_entries; i++)	237	for (i = 0; i < ppgtt->num_pd_entries; i++)
238	__free_page(ppgtt->pt_pages[i]);	238	__free_page(ppgtt->pt_pages[i]);
239	kfree(ppgtt->pt_pages);	239	kfree(ppgtt->pt_pages);
240	kfree(ppgtt);	240	kfree(ppgtt);
241	}	241	}
242		242
243	static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)	243	static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
244	{	244	{
245	struct drm_device *dev = ppgtt->dev;	245	struct drm_device *dev = ppgtt->dev;
246	struct drm_i915_private *dev_priv = dev->dev_private;	246	struct drm_i915_private *dev_priv = dev->dev_private;
247	unsigned first_pd_entry_in_global_pt;	247	unsigned first_pd_entry_in_global_pt;
248	int i;	248	int i;
249	int ret = -ENOMEM;	249	int ret = -ENOMEM;
250		250
251	/* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024	251	/* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
252	* entries. For aliasing ppgtt support we just steal them at the end for	252	* entries. For aliasing ppgtt support we just steal them at the end for
253	* now. */	253	* now. */
254	first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt);	254	first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt);
255		255
256	ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;	256	ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
257	ppgtt->enable = gen6_ppgtt_enable;	257	ppgtt->enable = gen6_ppgtt_enable;
258	ppgtt->clear_range = gen6_ppgtt_clear_range;	258	ppgtt->clear_range = gen6_ppgtt_clear_range;
259	ppgtt->insert_entries = gen6_ppgtt_insert_entries;	259	ppgtt->insert_entries = gen6_ppgtt_insert_entries;
260	ppgtt->cleanup = gen6_ppgtt_cleanup;	260	ppgtt->cleanup = gen6_ppgtt_cleanup;
261	ppgtt->pt_pages = kzalloc(sizeof(struct page )ppgtt->num_pd_entries,	261	ppgtt->pt_pages = kzalloc(sizeof(struct page )ppgtt->num_pd_entries,
262	GFP_KERNEL);	262	GFP_KERNEL);
263	if (!ppgtt->pt_pages)	263	if (!ppgtt->pt_pages)
264	return -ENOMEM;	264	return -ENOMEM;
265		265
266	for (i = 0; i < ppgtt->num_pd_entries; i++) {	266	for (i = 0; i < ppgtt->num_pd_entries; i++) {
267	ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);	267	ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
268	if (!ppgtt->pt_pages[i])	268	if (!ppgtt->pt_pages[i])
269	goto err_pt_alloc;	269	goto err_pt_alloc;
270	}	270	}
271		271
272	ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,	272	ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
273	GFP_KERNEL);	273	GFP_KERNEL);
274	if (!ppgtt->pt_dma_addr)	274	if (!ppgtt->pt_dma_addr)
275	goto err_pt_alloc;	275	goto err_pt_alloc;
276		276
277	for (i = 0; i < ppgtt->num_pd_entries; i++) {	277	for (i = 0; i < ppgtt->num_pd_entries; i++) {
278	dma_addr_t pt_addr;	278	dma_addr_t pt_addr;
279		279
280	pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,	280	pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
281	PCI_DMA_BIDIRECTIONAL);	281	PCI_DMA_BIDIRECTIONAL);
282		282
283	ppgtt->pt_dma_addr[i] = pt_addr;	283	ppgtt->pt_dma_addr[i] = pt_addr;
284	}	284	}
285		285
286	ppgtt->clear_range(ppgtt, 0,	286	ppgtt->clear_range(ppgtt, 0,
287	ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);	287	ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
288		288
289	ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);	289	ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
290		290
291	return 0;	291	return 0;
292		292
293	err_pd_pin:	293	err_pd_pin:
294	if (ppgtt->pt_dma_addr) {	294	if (ppgtt->pt_dma_addr) {
295	for (i--; i >= 0; i--)	295	for (i--; i >= 0; i--)
296	pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],	296	pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
297	4096, PCI_DMA_BIDIRECTIONAL);	297	4096, PCI_DMA_BIDIRECTIONAL);
298	}	298	}
299	err_pt_alloc:	299	err_pt_alloc:
300	kfree(ppgtt->pt_dma_addr);	300	kfree(ppgtt->pt_dma_addr);
301	for (i = 0; i < ppgtt->num_pd_entries; i++) {	301	for (i = 0; i < ppgtt->num_pd_entries; i++) {
302	if (ppgtt->pt_pages[i])	302	if (ppgtt->pt_pages[i])
303	__free_page(ppgtt->pt_pages[i]);	303	__free_page(ppgtt->pt_pages[i]);
304	}	304	}
305	kfree(ppgtt->pt_pages);	305	kfree(ppgtt->pt_pages);
306		306
307	return ret;	307	return ret;
308	}	308	}
309		309
310	static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)	310	static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
311	{	311	{
312	struct drm_i915_private *dev_priv = dev->dev_private;	312	struct drm_i915_private *dev_priv = dev->dev_private;
313	struct i915_hw_ppgtt *ppgtt;	313	struct i915_hw_ppgtt *ppgtt;
314	int ret;	314	int ret;
315		315
316	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);	316	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
317	if (!ppgtt)	317	if (!ppgtt)
318	return -ENOMEM;	318	return -ENOMEM;
319		319
320	ppgtt->dev = dev;	320	ppgtt->dev = dev;
321	ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma;	321	ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma;
322		322
323	if (INTEL_INFO(dev)->gen < 8)	323	if (INTEL_INFO(dev)->gen < 8)
324	ret = gen6_ppgtt_init(ppgtt);	324	ret = gen6_ppgtt_init(ppgtt);
325	else	325	else
326	BUG();	326	BUG();
327		327
328	if (ret)	328	if (ret)
329	kfree(ppgtt);	329	kfree(ppgtt);
330	else	330	else
331	dev_priv->mm.aliasing_ppgtt = ppgtt;	331	dev_priv->mm.aliasing_ppgtt = ppgtt;
332		332
333	return ret;	333	return ret;
334	}	334	}
335		335
336	void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)	336	void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
337	{	337	{
338	struct drm_i915_private *dev_priv = dev->dev_private;	338	struct drm_i915_private *dev_priv = dev->dev_private;
339	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;	339	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
340		340
341	if (!ppgtt)	341	if (!ppgtt)
342	return;	342	return;
343		343
344	ppgtt->cleanup(ppgtt);	344	ppgtt->cleanup(ppgtt);
345	dev_priv->mm.aliasing_ppgtt = NULL;	345	dev_priv->mm.aliasing_ppgtt = NULL;
346	}	346	}
347		347
348	void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,	348	void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
349	struct drm_i915_gem_object *obj,	349	struct drm_i915_gem_object *obj,
350	enum i915_cache_level cache_level)	350	enum i915_cache_level cache_level)
351	{	351	{
352	ppgtt->insert_entries(ppgtt, obj->pages,	352	ppgtt->insert_entries(ppgtt, obj->pages,
353	obj->gtt_space->start >> PAGE_SHIFT,	353	obj->gtt_space->start >> PAGE_SHIFT,
354	cache_level);	354	cache_level);
355	}	355	}
356		356
357	void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,	357	void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
358	struct drm_i915_gem_object *obj)	358	struct drm_i915_gem_object *obj)
359	{	359	{
360	ppgtt->clear_range(ppgtt,	360	ppgtt->clear_range(ppgtt,
361	obj->gtt_space->start >> PAGE_SHIFT,	361	obj->gtt_space->start >> PAGE_SHIFT,
362	obj->base.size >> PAGE_SHIFT);	362	obj->base.size >> PAGE_SHIFT);
363	}	363	}
364		364
365	extern int intel_iommu_gfx_mapped;	365	extern int intel_iommu_gfx_mapped;
366	/* Certain Gen5 chipsets require require idling the GPU before	366	/* Certain Gen5 chipsets require require idling the GPU before
367	* unmapping anything from the GTT when VT-d is enabled.	367	* unmapping anything from the GTT when VT-d is enabled.
368	*/	368	*/
369	static inline bool needs_idle_maps(struct drm_device *dev)	369	static inline bool needs_idle_maps(struct drm_device *dev)
370	{	370	{
371	#ifdef CONFIG_INTEL_IOMMU	371	#ifdef CONFIG_INTEL_IOMMU
372	/* Query intel_iommu to see if we need the workaround. Presumably that	372	/* Query intel_iommu to see if we need the workaround. Presumably that
373	* was loaded first.	373	* was loaded first.
374	*/	374	*/
375	if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)	375	if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
376	return true;	376	return true;
377	#endif	377	#endif
378	return false;	378	return false;
379	}	379	}
380		380
381	static bool do_idling(struct drm_i915_private *dev_priv)	381	static bool do_idling(struct drm_i915_private *dev_priv)
382	{	382	{
383	bool ret = dev_priv->mm.interruptible;	383	bool ret = dev_priv->mm.interruptible;
384		384
385	if (unlikely(dev_priv->gtt.do_idle_maps)) {	385	if (unlikely(dev_priv->gtt.do_idle_maps)) {
386	dev_priv->mm.interruptible = false;	386	dev_priv->mm.interruptible = false;
387	if (i915_gpu_idle(dev_priv->dev)) {	387	if (i915_gpu_idle(dev_priv->dev)) {
388	DRM_ERROR("Couldn't idle GPU\n");	388	DRM_ERROR("Couldn't idle GPU\n");
389	/* Wait a bit, in hopes it avoids the hang */	389	/* Wait a bit, in hopes it avoids the hang */
390	udelay(10);	390	udelay(10);
391	}	391	}
392	}	392	}
393		393
394	return ret;	394	return ret;
395	}	395	}
396		396
397	static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)	397	static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
398	{	398	{
399	if (unlikely(dev_priv->gtt.do_idle_maps))	399	if (unlikely(dev_priv->gtt.do_idle_maps))
400	dev_priv->mm.interruptible = interruptible;	400	dev_priv->mm.interruptible = interruptible;
401	}	401	}
402		402
403	void i915_gem_restore_gtt_mappings(struct drm_device *dev)	403	void i915_gem_restore_gtt_mappings(struct drm_device *dev)
404	{	404	{
405	struct drm_i915_private *dev_priv = dev->dev_private;	405	struct drm_i915_private *dev_priv = dev->dev_private;
406	struct drm_i915_gem_object *obj;	406	struct drm_i915_gem_object *obj;
407		407
408	/* First fill our portion of the GTT with scratch pages */	408	/* First fill our portion of the GTT with scratch pages */
409	dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,	409	dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
410	dev_priv->gtt.total / PAGE_SIZE);	410	dev_priv->gtt.total / PAGE_SIZE);
411		411
412	list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {	412	list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
413	i915_gem_clflush_object(obj);	413	i915_gem_clflush_object(obj);
414	i915_gem_gtt_bind_object(obj, obj->cache_level);	414	i915_gem_gtt_bind_object(obj, obj->cache_level);
415	}	415	}
416		416
417	i915_gem_chipset_flush(dev);	417	i915_gem_chipset_flush(dev);
418	}	418	}
419		419
420	int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)	420	int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
421	{	421	{
422	if (obj->has_dma_mapping)	422	if (obj->has_dma_mapping)
423	return 0;	423	return 0;
424		424
425	if (!dma_map_sg(&obj->base.dev->pdev->dev,	425	if (!dma_map_sg(&obj->base.dev->pdev->dev,
426	obj->pages->sgl, obj->pages->nents,	426	obj->pages->sgl, obj->pages->nents,
427	PCI_DMA_BIDIRECTIONAL))	427	PCI_DMA_BIDIRECTIONAL))
428	return -ENOSPC;	428	return -ENOSPC;
429		429
430	return 0;	430	return 0;
431	}	431	}
432		432
433	/*	433	/*
434	* Binds an object into the global gtt with the specified cache level. The object	434	* Binds an object into the global gtt with the specified cache level. The object
435	* will be accessible to the GPU via commands whose operands reference offsets	435	* will be accessible to the GPU via commands whose operands reference offsets
436	* within the global GTT as well as accessible by the GPU through the GMADR	436	* within the global GTT as well as accessible by the GPU through the GMADR
437	* mapped BAR (dev_priv->mm.gtt->gtt).	437	* mapped BAR (dev_priv->mm.gtt->gtt).
438	*/	438	*/
439	static void gen6_ggtt_insert_entries(struct drm_device *dev,	439	static void gen6_ggtt_insert_entries(struct drm_device *dev,
440	struct sg_table *st,	440	struct sg_table *st,
441	unsigned int first_entry,	441	unsigned int first_entry,
442	enum i915_cache_level level)	442	enum i915_cache_level level)
443	{	443	{
444	struct drm_i915_private *dev_priv = dev->dev_private;	444	struct drm_i915_private *dev_priv = dev->dev_private;
445	gen6_gtt_pte_t __iomem *gtt_entries =	445	gen6_gtt_pte_t __iomem *gtt_entries =
446	(gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;	446	(gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
447	int i = 0;	447	int i = 0;
448	struct sg_page_iter sg_iter;	448	struct sg_page_iter sg_iter;
449	dma_addr_t addr;	449	dma_addr_t addr;
450		450
451	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {	451	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
452	addr = sg_page_iter_dma_address(&sg_iter);	452	addr = sg_page_iter_dma_address(&sg_iter);
453	iowrite32(gen6_pte_encode(dev, addr, level), >t_entries[i]);	453	iowrite32(gen6_pte_encode(dev, addr, level), >t_entries[i]);
454	i++;	454	i++;
455	}	455	}
456		456
457	/* XXX: This serves as a posting read to make sure that the PTE has	457	/* XXX: This serves as a posting read to make sure that the PTE has
458	* actually been updated. There is some concern that even though	458	* actually been updated. There is some concern that even though
459	* registers and PTEs are within the same BAR that they are potentially	459	* registers and PTEs are within the same BAR that they are potentially
460	* of NUMA access patterns. Therefore, even with the way we assume	460	* of NUMA access patterns. Therefore, even with the way we assume
461	* hardware should work, we must keep this posting read for paranoia.	461	* hardware should work, we must keep this posting read for paranoia.
462	*/	462	*/
463	if (i != 0)	463	if (i != 0)
464	WARN_ON(readl(>t_entries[i-1])	464	WARN_ON(readl(>t_entries[i-1])
465	!= gen6_pte_encode(dev, addr, level));	465	!= gen6_pte_encode(dev, addr, level));
466		466
467	/* This next bit makes the above posting read even more important. We	467	/* This next bit makes the above posting read even more important. We
468	* want to flush the TLBs only after we're certain all the PTE updates	468	* want to flush the TLBs only after we're certain all the PTE updates
469	* have finished.	469	* have finished.
470	*/	470	*/
471	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);	471	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
472	POSTING_READ(GFX_FLSH_CNTL_GEN6);	472	POSTING_READ(GFX_FLSH_CNTL_GEN6);
473	}	473	}
474		474
475	static void gen6_ggtt_clear_range(struct drm_device *dev,	475	static void gen6_ggtt_clear_range(struct drm_device *dev,
476	unsigned int first_entry,	476	unsigned int first_entry,
477	unsigned int num_entries)	477	unsigned int num_entries)
478	{	478	{
479	struct drm_i915_private *dev_priv = dev->dev_private;	479	struct drm_i915_private *dev_priv = dev->dev_private;
480	gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =	480	gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
481	(gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;	481	(gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
482	const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;	482	const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
483	int i;	483	int i;
484		484
485	// if (WARN(num_entries > max_entries,	485	// if (WARN(num_entries > max_entries,
486	// "First entry = %d; Num entries = %d (max=%d)\n",	486	// "First entry = %d; Num entries = %d (max=%d)\n",
487	// first_entry, num_entries, max_entries))	487	// first_entry, num_entries, max_entries))
488	if (num_entries > max_entries)	488	if (num_entries > max_entries)
489	num_entries = max_entries;	489	num_entries = max_entries;
490		490
491	scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma,	491	scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma,
492	I915_CACHE_LLC);	492	I915_CACHE_LLC);
493	for (i = 0; i < num_entries; i++)	493	for (i = 0; i < num_entries; i++)
494	iowrite32(scratch_pte, >t_base[i]);	494	iowrite32(scratch_pte, >t_base[i]);
495	readl(gtt_base);	495	readl(gtt_base);
496	}	496	}
497		497
498		498
499	static void i915_ggtt_insert_entries(struct drm_device *dev,	499	static void i915_ggtt_insert_entries(struct drm_device *dev,
500	struct sg_table *st,	500	struct sg_table *st,

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_gem_gtt.c – Rev 3746 → 3764