WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_gem_execbuffer.c


/*
 * Copyright © 2008,2010 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt 
 *    Chris Wilson 
 *
 */
 
#include 
#include 
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"
#include 
#include 
 
#define  __EXEC_OBJECT_HAS_PIN (1<<31)
#define  __EXEC_OBJECT_HAS_FENCE (1<<30)
#define  __EXEC_OBJECT_NEEDS_MAP (1<<29)
#define  __EXEC_OBJECT_NEEDS_BIAS (1<<28)
 
#define BATCH_OFFSET_BIAS (256*1024)
 
struct eb_vmas {
	struct list_head vmas;
	int and;
	union {
		struct i915_vma *lut[0];
		struct hlist_head buckets[0];
	};
};
 
static struct eb_vmas *
eb_create(struct drm_i915_gem_execbuffer2 *args)
{
	struct eb_vmas *eb = NULL;
 
	if (args->flags & I915_EXEC_HANDLE_LUT) {
		unsigned size = args->buffer_count;
		size *= sizeof(struct i915_vma *);
		size += sizeof(struct eb_vmas);
		eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
	}
 
	if (eb == NULL) {
		unsigned size = args->buffer_count;
		unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
		BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
		while (count > 2*size)
			count >>= 1;
		eb = kzalloc(count*sizeof(struct hlist_head) +
			     sizeof(struct eb_vmas),
			     GFP_TEMPORARY);
		if (eb == NULL)
			return eb;
 
		eb->and = count - 1;
	} else
		eb->and = -args->buffer_count;
 
	INIT_LIST_HEAD(&eb->vmas);
	return eb;
}
 
static void
eb_reset(struct eb_vmas *eb)
{
	if (eb->and >= 0)
		memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
}
 
static int
eb_lookup_vmas(struct eb_vmas *eb,
	       struct drm_i915_gem_exec_object2 *exec,
	       const struct drm_i915_gem_execbuffer2 *args,
	       struct i915_address_space *vm,
	       struct drm_file *file)
{
	struct drm_i915_gem_object *obj;
	struct list_head objects;
	int i, ret;
 
	INIT_LIST_HEAD(&objects);
	spin_lock(&file->table_lock);
	/* Grab a reference to the object and release the lock so we can lookup
	 * or create the VMA without using GFP_ATOMIC */
	for (i = 0; i < args->buffer_count; i++) {
		obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
		if (obj == NULL) {
			spin_unlock(&file->table_lock);
			DRM_DEBUG("Invalid object handle %d at index %d\n",
				   exec[i].handle, i);
			ret = -ENOENT;
			goto err;
		}
 
		if (!list_empty(&obj->obj_exec_link)) {
			spin_unlock(&file->table_lock);
			DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
				   obj, exec[i].handle, i);
			ret = -EINVAL;
			goto err;
		}
 
		drm_gem_object_reference(&obj->base);
		list_add_tail(&obj->obj_exec_link, &objects);
	}
	spin_unlock(&file->table_lock);
 
	i = 0;
	while (!list_empty(&objects)) {
		struct i915_vma *vma;
 
		obj = list_first_entry(&objects,
				       struct drm_i915_gem_object,
				       obj_exec_link);
 
		/*
		 * NOTE: We can leak any vmas created here when something fails
		 * later on. But that's no issue since vma_unbind can deal with
		 * vmas which are not actually bound. And since only
		 * lookup_or_create exists as an interface to get at the vma
		 * from the (obj, vm) we don't run the risk of creating
		 * duplicated vmas for the same vm.
		 */
		vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
		if (IS_ERR(vma)) {
			DRM_DEBUG("Failed to lookup VMA\n");
			ret = PTR_ERR(vma);
			goto err;
		}
 
		/* Transfer ownership from the objects list to the vmas list. */
		list_add_tail(&vma->exec_list, &eb->vmas);
		list_del_init(&obj->obj_exec_link);
 
		vma->exec_entry = &exec[i];
		if (eb->and < 0) {
			eb->lut[i] = vma;
		} else {
			uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
			vma->exec_handle = handle;
			hlist_add_head(&vma->exec_node,
				       &eb->buckets[handle & eb->and]);
		}
		++i;
	}
 
	return 0;
 
 
err:
	while (!list_empty(&objects)) {
		obj = list_first_entry(&objects,
				       struct drm_i915_gem_object,
				       obj_exec_link);
		list_del_init(&obj->obj_exec_link);
		drm_gem_object_unreference(&obj->base);
	}
	/*
	 * Objects already transfered to the vmas list will be unreferenced by
	 * eb_destroy.
	 */
 
	return ret;
}
 
static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
{
	if (eb->and < 0) {
		if (handle >= -eb->and)
			return NULL;
		return eb->lut[handle];
	} else {
		struct hlist_head *head;
 
 
 
 
		struct i915_vma *vma;
 
		head = &eb->buckets[handle & eb->and];
		hlist_for_each_entry(vma, head, exec_node) {
			if (vma->exec_handle == handle)
				return vma;
		}
		return NULL;
	}
}
 
static void
i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
{
	struct drm_i915_gem_exec_object2 *entry;
	struct drm_i915_gem_object *obj = vma->obj;
 
	if (!drm_mm_node_allocated(&vma->node))
		return;
 
	entry = vma->exec_entry;
 
	if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
		i915_gem_object_unpin_fence(obj);
 
	if (entry->flags & __EXEC_OBJECT_HAS_PIN)
		vma->pin_count--;
 
	entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
}
 
static void eb_destroy(struct eb_vmas *eb)
{
	while (!list_empty(&eb->vmas)) {
		struct i915_vma *vma;
 
		vma = list_first_entry(&eb->vmas,
				       struct i915_vma,
				       exec_list);
		list_del_init(&vma->exec_list);
		i915_gem_execbuffer_unreserve_vma(vma);
		drm_gem_object_unreference(&vma->obj->base);
	}
	kfree(eb);
}
 
static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
{
	return (HAS_LLC(obj->base.dev) ||
		obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
		obj->cache_level != I915_CACHE_NONE);
}
 
/* Used to convert any address to canonical form.
 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
 * addresses to be in a canonical form:
 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
 * canonical form [63:48] == [47]."
 */
#define GEN8_HIGH_ADDRESS_BIT 47
static inline uint64_t gen8_canonical_addr(uint64_t address)
{
	return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
}
 
static inline uint64_t gen8_noncanonical_addr(uint64_t address)
{
	return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1);
}
 
static inline uint64_t
relocation_target(struct drm_i915_gem_relocation_entry *reloc,
		  uint64_t target_offset)
{
	return gen8_canonical_addr((int)reloc->delta + target_offset);
}
 
static int
relocate_entry_cpu(struct drm_i915_gem_object *obj,
		   struct drm_i915_gem_relocation_entry *reloc,
		   uint64_t target_offset)
{
	struct drm_device *dev = obj->base.dev;
	uint32_t page_offset = offset_in_page(reloc->offset);
	uint64_t delta = relocation_target(reloc, target_offset);
	char *vaddr;
	int ret;
 
	ret = i915_gem_object_set_to_cpu_domain(obj, true);
	if (ret)
		return ret;
 
	vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
				reloc->offset >> PAGE_SHIFT));
	*(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta);
 
	if (INTEL_INFO(dev)->gen >= 8) {
		page_offset = offset_in_page(page_offset + sizeof(uint32_t));
 
		if (page_offset == 0) {
			kunmap_atomic(vaddr);
			vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
			    (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
		}
 
		*(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta);
	}
 
	kunmap_atomic(vaddr);
 
	return 0;
}
 
static int
relocate_entry_gtt(struct drm_i915_gem_object *obj,
		   struct drm_i915_gem_relocation_entry *reloc,
		   uint64_t target_offset)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint64_t delta = relocation_target(reloc, target_offset);
	uint64_t offset;
	void __iomem *reloc_page;
	int ret;
 
	ret = i915_gem_object_set_to_gtt_domain(obj, true);
	if (ret)
		return ret;
 
	ret = i915_gem_object_put_fence(obj);
	if (ret)
		return ret;
 
	/* Map the page containing the relocation we're going to perform.  */
	offset = i915_gem_obj_ggtt_offset(obj);
	offset += reloc->offset;
	reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
					      offset & PAGE_MASK);
 
	iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset));
 
	if (INTEL_INFO(dev)->gen >= 8) {
		offset += sizeof(uint32_t);
 
		if (offset_in_page(offset) == 0) {
			io_mapping_unmap_atomic(reloc_page);
			reloc_page =
				io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
							 offset);
		}
 
		iowrite32(upper_32_bits(delta),
			  reloc_page + offset_in_page(offset));
	}
 
	io_mapping_unmap_atomic(reloc_page);
 
	return 0;
}
 
static void
clflush_write32(void *addr, uint32_t value)
{
	/* This is not a fast path, so KISS. */
	drm_clflush_virt_range(addr, sizeof(uint32_t));
	*(uint32_t *)addr = value;
	drm_clflush_virt_range(addr, sizeof(uint32_t));
}
 
static int
relocate_entry_clflush(struct drm_i915_gem_object *obj,
		       struct drm_i915_gem_relocation_entry *reloc,
		       uint64_t target_offset)
{
	struct drm_device *dev = obj->base.dev;
	uint32_t page_offset = offset_in_page(reloc->offset);
	uint64_t delta = relocation_target(reloc, target_offset);
	char *vaddr;
	int ret;
 
	ret = i915_gem_object_set_to_gtt_domain(obj, true);
	if (ret)
		return ret;
 
	vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
				reloc->offset >> PAGE_SHIFT));
	clflush_write32(vaddr + page_offset, lower_32_bits(delta));
 
	if (INTEL_INFO(dev)->gen >= 8) {
		page_offset = offset_in_page(page_offset + sizeof(uint32_t));
 
		if (page_offset == 0) {
			kunmap_atomic(vaddr);
			vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
			    (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
		}
 
		clflush_write32(vaddr + page_offset, upper_32_bits(delta));
	}
 
	kunmap_atomic(vaddr);
 
	return 0;
}
 
static int
i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
				   struct eb_vmas *eb,
				   struct drm_i915_gem_relocation_entry *reloc)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_gem_object *target_obj;
	struct drm_i915_gem_object *target_i915_obj;
	struct i915_vma *target_vma;
	uint64_t target_offset;
	int ret;
 
	/* we've already hold a reference to all valid objects */
	target_vma = eb_get_vma(eb, reloc->target_handle);
	if (unlikely(target_vma == NULL))
		return -ENOENT;
	target_i915_obj = target_vma->obj;
	target_obj = &target_vma->obj->base;
 
	target_offset = gen8_canonical_addr(target_vma->node.start);
 
	/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
	 * pipe_control writes because the gpu doesn't properly redirect them
	 * through the ppgtt for non_secure batchbuffers. */
	if (unlikely(IS_GEN6(dev) &&
	    reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
		ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
				    PIN_GLOBAL);
		if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))
			return ret;
	}
 
	/* Validate that the target is in a valid r/w GPU domain */
	if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
		DRM_DEBUG("reloc with multiple write domains: "
			  "obj %p target %d offset %d "
			  "read %08x write %08x",
			  obj, reloc->target_handle,
			  (int) reloc->offset,
			  reloc->read_domains,
			  reloc->write_domain);
		return -EINVAL;
	}
	if (unlikely((reloc->write_domain | reloc->read_domains)
		     & ~I915_GEM_GPU_DOMAINS)) {
		DRM_DEBUG("reloc with read/write non-GPU domains: "
			  "obj %p target %d offset %d "
			  "read %08x write %08x",
			  obj, reloc->target_handle,
			  (int) reloc->offset,
			  reloc->read_domains,
			  reloc->write_domain);
		return -EINVAL;
	}
 
	target_obj->pending_read_domains |= reloc->read_domains;
	target_obj->pending_write_domain |= reloc->write_domain;
 
	/* If the relocation already has the right value in it, no
	 * more work needs to be done.
	 */
	if (target_offset == reloc->presumed_offset)
		return 0;
 
	/* Check that the relocation address is valid... */
	if (unlikely(reloc->offset >
		obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
		DRM_DEBUG("Relocation beyond object bounds: "
			  "obj %p target %d offset %d size %d.\n",
			  obj, reloc->target_handle,
			  (int) reloc->offset,
			  (int) obj->base.size);
		return -EINVAL;
	}
	if (unlikely(reloc->offset & 3)) {
		DRM_DEBUG("Relocation not 4-byte aligned: "
			  "obj %p target %d offset %d.\n",
			  obj, reloc->target_handle,
			  (int) reloc->offset);
		return -EINVAL;
	}
 
	/* We can't wait for rendering with pagefaults disabled */
 
	if (use_cpu_reloc(obj))
		ret = relocate_entry_cpu(obj, reloc, target_offset);
	else if (obj->map_and_fenceable)
		ret = relocate_entry_gtt(obj, reloc, target_offset);
	else if (1)
		ret = relocate_entry_clflush(obj, reloc, target_offset);
	else {
		WARN_ONCE(1, "Impossible case in relocation handling\n");
		ret = -ENODEV;
	}
 
	if (ret)
		return ret;
 
	/* and update the user's relocation entry */
	reloc->presumed_offset = target_offset;
 
	return 0;
}
 
static int
i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
				 struct eb_vmas *eb)
{
#define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
	struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(64)];
	struct drm_i915_gem_relocation_entry __user *user_relocs;
	struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
	int remain, ret;
 
	user_relocs = to_user_ptr(entry->relocs_ptr);
 
	remain = entry->relocation_count;
	while (remain) {
		struct drm_i915_gem_relocation_entry *r = stack_reloc;
		int count = remain;
		if (count > ARRAY_SIZE(stack_reloc))
			count = ARRAY_SIZE(stack_reloc);
		remain -= count;
 
		if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
			return -EFAULT;
 
		do {
			u64 offset = r->presumed_offset;
 
			ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r);
			if (ret)
				return ret;
 
 
			if (r->presumed_offset != offset &&
			    __copy_to_user_inatomic(&user_relocs->presumed_offset,
						    &r->presumed_offset,
						    sizeof(r->presumed_offset))) {
				return -EFAULT;
			}
 
			user_relocs++;
			r++;
		} while (--count);
	}
 
	return 0;
#undef N_RELOC
}
 
static int
i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
				      struct eb_vmas *eb,
				      struct drm_i915_gem_relocation_entry *relocs)
{
	const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
	int i, ret;
 
	for (i = 0; i < entry->relocation_count; i++) {
		ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]);
		if (ret)
			return ret;
	}
 
	return 0;
}
 
static int
i915_gem_execbuffer_relocate(struct eb_vmas *eb)
{
	struct i915_vma *vma;
	int ret = 0;
 
	/* This is the fast path and we cannot handle a pagefault whilst
	 * holding the struct mutex lest the user pass in the relocations
	 * contained within a mmaped bo. For in such a case we, the page
	 * fault handler would call i915_gem_fault() and we would try to
	 * acquire the struct mutex again. Obviously this is bad and so
	 * lockdep complains vehemently.
	 */
	pagefault_disable();
	list_for_each_entry(vma, &eb->vmas, exec_list) {
		ret = i915_gem_execbuffer_relocate_vma(vma, eb);
		if (ret)
			break;
	}
	pagefault_enable();
 
	return ret;
}
 
static bool only_mappable_for_reloc(unsigned int flags)
{
	return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) ==
		__EXEC_OBJECT_NEEDS_MAP;
}
 
static int
i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
				struct intel_engine_cs *ring,
				bool *need_reloc)
{
	struct drm_i915_gem_object *obj = vma->obj;
	struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
	uint64_t flags;
	int ret;
 
	flags = PIN_USER;
	if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
		flags |= PIN_GLOBAL;
 
	if (!drm_mm_node_allocated(&vma->node)) {
		/* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
		 * limit address to the first 4GBs for unflagged objects.
		 */
		if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0)
			flags |= PIN_ZONE_4G;
		if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
			flags |= PIN_GLOBAL | PIN_MAPPABLE;
		if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
			flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
		if (entry->flags & EXEC_OBJECT_PINNED)
			flags |= entry->offset | PIN_OFFSET_FIXED;
		if ((flags & PIN_MAPPABLE) == 0)
			flags |= PIN_HIGH;
	}
 
	ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags);
	if ((ret == -ENOSPC  || ret == -E2BIG) &&
	    only_mappable_for_reloc(entry->flags))
		ret = i915_gem_object_pin(obj, vma->vm,
					  entry->alignment,
					  flags & ~PIN_MAPPABLE);
	if (ret)
		return ret;
 
	entry->flags |= __EXEC_OBJECT_HAS_PIN;
 
	if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
		ret = i915_gem_object_get_fence(obj);
		if (ret)
			return ret;
 
		if (i915_gem_object_pin_fence(obj))
			entry->flags |= __EXEC_OBJECT_HAS_FENCE;
	}
 
	if (entry->offset != vma->node.start) {
		entry->offset = vma->node.start;
		*need_reloc = true;
	}
 
	if (entry->flags & EXEC_OBJECT_WRITE) {
		obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
		obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
	}
 
	return 0;
}
 
static bool
need_reloc_mappable(struct i915_vma *vma)
{
	struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 
	if (entry->relocation_count == 0)
		return false;
 
	if (!vma->is_ggtt)
		return false;
 
	/* See also use_cpu_reloc() */
	if (HAS_LLC(vma->obj->base.dev))
		return false;
 
	if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
		return false;
 
	return true;
}
 
static bool
eb_vma_misplaced(struct i915_vma *vma)
{
	struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
	struct drm_i915_gem_object *obj = vma->obj;
 
 
	WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && !vma->is_ggtt);
 
	if (entry->alignment &&
	    vma->node.start & (entry->alignment - 1))
		return true;
 
	if (entry->flags & EXEC_OBJECT_PINNED &&
	    vma->node.start != entry->offset)
		return true;
 
	if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
	    vma->node.start < BATCH_OFFSET_BIAS)
		return true;
 
	/* avoid costly ping-pong once a batch bo ended up non-mappable */
	if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable)
		return !only_mappable_for_reloc(entry->flags);
 
	if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 &&
	    (vma->node.start + vma->node.size - 1) >> 32)
		return true;
 
	return false;
}
 
static int
i915_gem_execbuffer_reserve(struct intel_engine_cs *ring,
			    struct list_head *vmas,
			    struct intel_context *ctx,
			    bool *need_relocs)
{
	struct drm_i915_gem_object *obj;
	struct i915_vma *vma;
	struct i915_address_space *vm;
	struct list_head ordered_vmas;
	struct list_head pinned_vmas;
	bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
	int retry;
 
	i915_gem_retire_requests_ring(ring);
 
	vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
 
	INIT_LIST_HEAD(&ordered_vmas);
	INIT_LIST_HEAD(&pinned_vmas);
	while (!list_empty(vmas)) {
		struct drm_i915_gem_exec_object2 *entry;
		bool need_fence, need_mappable;
 
		vma = list_first_entry(vmas, struct i915_vma, exec_list);
		obj = vma->obj;
		entry = vma->exec_entry;
 
		if (ctx->flags & CONTEXT_NO_ZEROMAP)
			entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
 
		if (!has_fenced_gpu_access)
			entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
		need_fence =
			entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
			obj->tiling_mode != I915_TILING_NONE;
		need_mappable = need_fence || need_reloc_mappable(vma);
 
		if (entry->flags & EXEC_OBJECT_PINNED)
			list_move_tail(&vma->exec_list, &pinned_vmas);
		else if (need_mappable) {
			entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
			list_move(&vma->exec_list, &ordered_vmas);
		} else
			list_move_tail(&vma->exec_list, &ordered_vmas);
 
		obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
		obj->base.pending_write_domain = 0;
	}
	list_splice(&ordered_vmas, vmas);
	list_splice(&pinned_vmas, vmas);
 
	/* Attempt to pin all of the buffers into the GTT.
	 * This is done in 3 phases:
	 *
	 * 1a. Unbind all objects that do not match the GTT constraints for
	 *     the execbuffer (fenceable, mappable, alignment etc).
	 * 1b. Increment pin count for already bound objects.
	 * 2.  Bind new objects.
	 * 3.  Decrement pin count.
	 *
	 * This avoid unnecessary unbinding of later objects in order to make
	 * room for the earlier objects *unless* we need to defragment.
	 */
	retry = 0;
	do {
		int ret = 0;
 
		/* Unbind any ill-fitting objects or pin. */
		list_for_each_entry(vma, vmas, exec_list) {
			if (!drm_mm_node_allocated(&vma->node))
				continue;
 
			if (eb_vma_misplaced(vma))
				ret = i915_vma_unbind(vma);
			else
				ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
			if (ret)
				goto err;
		}
 
		/* Bind fresh objects */
		list_for_each_entry(vma, vmas, exec_list) {
			if (drm_mm_node_allocated(&vma->node))
				continue;
 
			ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
			if (ret)
				goto err;
		}
 
err:
		if (ret != -ENOSPC || retry++)
			return ret;
 
		/* Decrement pin count for bound objects */
		list_for_each_entry(vma, vmas, exec_list)
			i915_gem_execbuffer_unreserve_vma(vma);
 
		ret = i915_gem_evict_vm(vm, true);
		if (ret)
			return ret;
	} while (1);
}
 
static int
i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
				  struct drm_i915_gem_execbuffer2 *args,
				  struct drm_file *file,
				  struct intel_engine_cs *ring,
				  struct eb_vmas *eb,
				  struct drm_i915_gem_exec_object2 *exec,
				  struct intel_context *ctx)
{
	struct drm_i915_gem_relocation_entry *reloc;
	struct i915_address_space *vm;
	struct i915_vma *vma;
	bool need_relocs;
	int *reloc_offset;
	int i, total, ret;
	unsigned count = args->buffer_count;
 
	vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
 
	/* We may process another execbuffer during the unlock... */
	while (!list_empty(&eb->vmas)) {
		vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
		list_del_init(&vma->exec_list);
		i915_gem_execbuffer_unreserve_vma(vma);
		drm_gem_object_unreference(&vma->obj->base);
	}
 
	mutex_unlock(&dev->struct_mutex);
 
	total = 0;
	for (i = 0; i < count; i++)
		total += exec[i].relocation_count;
 
    reloc_offset = __builtin_malloc(count * sizeof(*reloc_offset));
    reloc = __builtin_malloc(total * sizeof(*reloc));
	if (reloc == NULL || reloc_offset == NULL) {
        kfree(reloc);
        kfree(reloc_offset);
		mutex_lock(&dev->struct_mutex);
		return -ENOMEM;
	}
 
	total = 0;
	for (i = 0; i < count; i++) {
		struct drm_i915_gem_relocation_entry __user *user_relocs;
		u64 invalid_offset = (u64)-1;
		int j;
 
		user_relocs = to_user_ptr(exec[i].relocs_ptr);
 
		if (copy_from_user(reloc+total, user_relocs,
				   exec[i].relocation_count * sizeof(*reloc))) {
			ret = -EFAULT;
			mutex_lock(&dev->struct_mutex);
			goto err;
		}
 
		/* As we do not update the known relocation offsets after
		 * relocating (due to the complexities in lock handling),
		 * we need to mark them as invalid now so that we force the
		 * relocation processing next time. Just in case the target
		 * object is evicted and then rebound into its old
		 * presumed_offset before the next execbuffer - if that
		 * happened we would make the mistake of assuming that the
		 * relocations were valid.
		 */
		for (j = 0; j < exec[i].relocation_count; j++) {
			if (__copy_to_user(&user_relocs[j].presumed_offset,
					   &invalid_offset,
					   sizeof(invalid_offset))) {
				ret = -EFAULT;
				mutex_lock(&dev->struct_mutex);
				goto err;
			}
		}
 
		reloc_offset[i] = total;
		total += exec[i].relocation_count;
	}
 
	ret = i915_mutex_lock_interruptible(dev);
	if (ret) {
		mutex_lock(&dev->struct_mutex);
		goto err;
	}
 
	/* reacquire the objects */
	eb_reset(eb);
	ret = eb_lookup_vmas(eb, exec, args, vm, file);
	if (ret)
		goto err;
 
	need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
	ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs);
	if (ret)
		goto err;
 
	list_for_each_entry(vma, &eb->vmas, exec_list) {
		int offset = vma->exec_entry - exec;
		ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
							    reloc + reloc_offset[offset]);
		if (ret)
			goto err;
	}
 
	/* Leave the user relocations as are, this is the painfully slow path,
	 * and we want to avoid the complication of dropping the lock whilst
	 * having buffers reserved in the aperture and so causing spurious
	 * ENOSPC for random operations.
	 */
 
err:
    kfree(reloc);
    kfree(reloc_offset);
	return ret;
}
 
static int
i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
				struct list_head *vmas)
{
	const unsigned other_rings = ~intel_ring_flag(req->ring);
	struct i915_vma *vma;
	uint32_t flush_domains = 0;
	bool flush_chipset = false;
	int ret;
 
	list_for_each_entry(vma, vmas, exec_list) {
		struct drm_i915_gem_object *obj = vma->obj;
 
		if (obj->active & other_rings) {
			ret = i915_gem_object_sync(obj, req->ring, &req);
			if (ret)
				return ret;
		}
 
		if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
			flush_chipset |= i915_gem_clflush_object(obj, false);
 
		flush_domains |= obj->base.write_domain;
	}
 
	if (flush_chipset)
		i915_gem_chipset_flush(req->ring->dev);
 
	if (flush_domains & I915_GEM_DOMAIN_GTT)
		wmb();
 
	/* Unconditionally invalidate gpu caches and ensure that we do flush
	 * any residual writes from the previous batch.
	 */
	return intel_ring_invalidate_all_caches(req);
}
 
static bool
i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
{
	if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
		return false;
 
	/* Kernel clipping was a DRI1 misfeature */
	if (exec->num_cliprects || exec->cliprects_ptr)
		return false;
 
	if (exec->DR4 == 0xffffffff) {
		DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
		exec->DR4 = 0;
	}
	if (exec->DR1 || exec->DR4)
		return false;
 
	if ((exec->batch_start_offset | exec->batch_len) & 0x7)
		return false;
 
	return true;
}
 
static int
validate_exec_list(struct drm_device *dev,
		   struct drm_i915_gem_exec_object2 *exec,
		   int count)
{
	unsigned relocs_total = 0;
	unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
	unsigned invalid_flags;
	int i;
 
	invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
	if (USES_FULL_PPGTT(dev))
		invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
 
	for (i = 0; i < count; i++) {
		char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
		int length; /* limited by fault_in_pages_readable() */
 
		if (exec[i].flags & invalid_flags)
			return -EINVAL;
 
		/* Offset can be used as input (EXEC_OBJECT_PINNED), reject
		 * any non-page-aligned or non-canonical addresses.
		 */
		if (exec[i].flags & EXEC_OBJECT_PINNED) {
			if (exec[i].offset !=
			    gen8_canonical_addr(exec[i].offset & PAGE_MASK))
				return -EINVAL;
 
			/* From drm_mm perspective address space is continuous,
			 * so from this point we're always using non-canonical
			 * form internally.
			 */
			exec[i].offset = gen8_noncanonical_addr(exec[i].offset);
		}
 
		if (exec[i].alignment && !is_power_of_2(exec[i].alignment))
			return -EINVAL;
 
		/* First check for malicious input causing overflow in
		 * the worst case where we need to allocate the entire
		 * relocation tree as a single array.
		 */
		if (exec[i].relocation_count > relocs_max - relocs_total)
			return -EINVAL;
		relocs_total += exec[i].relocation_count;
 
		length = exec[i].relocation_count *
			sizeof(struct drm_i915_gem_relocation_entry);
		/*
		 * We must check that the entire relocation array is safe
		 * to read, but since we may need to update the presumed
		 * offsets during execution, check for full write access.
		 */
	}
 
	return 0;
}
 
static struct intel_context *
i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
			  struct intel_engine_cs *ring, const u32 ctx_id)
{
	struct intel_context *ctx = NULL;
	struct i915_ctx_hang_stats *hs;
 
	if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE)
		return ERR_PTR(-EINVAL);
 
	ctx = i915_gem_context_get(file->driver_priv, ctx_id);
	if (IS_ERR(ctx))
		return ctx;
 
	hs = &ctx->hang_stats;
	if (hs->banned) {
		DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
		return ERR_PTR(-EIO);
	}
 
	if (i915.enable_execlists && !ctx->engine[ring->id].state) {
		int ret = intel_lr_context_deferred_alloc(ctx, ring);
		if (ret) {
			DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret);
			return ERR_PTR(ret);
		}
	}
 
	return ctx;
}
 
void
i915_gem_execbuffer_move_to_active(struct list_head *vmas,
				   struct drm_i915_gem_request *req)
{
	struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
	struct i915_vma *vma;
 
	list_for_each_entry(vma, vmas, exec_list) {
		struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
		struct drm_i915_gem_object *obj = vma->obj;
		u32 old_read = obj->base.read_domains;
		u32 old_write = obj->base.write_domain;
 
		obj->dirty = 1; /* be paranoid  */
		obj->base.write_domain = obj->base.pending_write_domain;
		if (obj->base.write_domain == 0)
			obj->base.pending_read_domains |= obj->base.read_domains;
		obj->base.read_domains = obj->base.pending_read_domains;
 
		i915_vma_move_to_active(vma, req);
		if (obj->base.write_domain) {
			i915_gem_request_assign(&obj->last_write_req, req);
 
			intel_fb_obj_invalidate(obj, ORIGIN_CS);
 
			/* update for the implicit flush after a batch */
			obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
		}
		if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
			i915_gem_request_assign(&obj->last_fenced_req, req);
			if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
				struct drm_i915_private *dev_priv = to_i915(ring->dev);
				list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
					       &dev_priv->mm.fence_list);
			}
		}
 
		trace_i915_gem_object_change_domain(obj, old_read, old_write);
	}
}
 
void
i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
{
	/* Unconditionally force add_request to emit a full flush. */
	params->ring->gpu_caches_dirty = true;
 
	/* Add a breadcrumb for the completion of the batch buffer */
	__i915_add_request(params->request, params->batch_obj, true);
}
 
static int
i915_reset_gen7_sol_offsets(struct drm_device *dev,
			    struct drm_i915_gem_request *req)
{
	struct intel_engine_cs *ring = req->ring;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret, i;
 
	if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) {
		DRM_DEBUG("sol reset is gen7/rcs only\n");
		return -EINVAL;
	}
 
	ret = intel_ring_begin(req, 4 * 3);
	if (ret)
		return ret;
 
	for (i = 0; i < 4; i++) {
		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
		intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i));
		intel_ring_emit(ring, 0);
	}
 
	intel_ring_advance(ring);
 
	return 0;
}
 
static struct drm_i915_gem_object*
i915_gem_execbuffer_parse(struct intel_engine_cs *ring,
			  struct drm_i915_gem_exec_object2 *shadow_exec_entry,
			  struct eb_vmas *eb,
			  struct drm_i915_gem_object *batch_obj,
			  u32 batch_start_offset,
			  u32 batch_len,
			  bool is_master)
{
	struct drm_i915_gem_object *shadow_batch_obj;
	struct i915_vma *vma;
	int ret;
 
	shadow_batch_obj = i915_gem_batch_pool_get(&ring->batch_pool,
						   PAGE_ALIGN(batch_len));
	if (IS_ERR(shadow_batch_obj))
		return shadow_batch_obj;
 
	ret = i915_parse_cmds(ring,
			      batch_obj,
			      shadow_batch_obj,
			      batch_start_offset,
			      batch_len,
			      is_master);
	if (ret)
		goto err;
 
	ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0);
	if (ret)
		goto err;
 
	i915_gem_object_unpin_pages(shadow_batch_obj);
 
	memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
 
	vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
	vma->exec_entry = shadow_exec_entry;
	vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
	drm_gem_object_reference(&shadow_batch_obj->base);
	list_add_tail(&vma->exec_list, &eb->vmas);
 
	shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND;
 
	return shadow_batch_obj;
 
err:
	i915_gem_object_unpin_pages(shadow_batch_obj);
	if (ret == -EACCES) /* unhandled chained batch */
		return batch_obj;
	else
		return ERR_PTR(ret);
}
 
int
i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
			       struct drm_i915_gem_execbuffer2 *args,
			       struct list_head *vmas)
{
	struct drm_device *dev = params->dev;
	struct intel_engine_cs *ring = params->ring;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u64 exec_start, exec_len;
	int instp_mode;
	u32 instp_mask;
	int ret;
 
	ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);
	if (ret)
		return ret;
 
	ret = i915_switch_context(params->request);
	if (ret)
		return ret;
 
	WARN(params->ctx->ppgtt && params->ctx->ppgtt->pd_dirty_rings & (1<id),
	     "%s didn't clear reload\n", ring->name);
 
	instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
	instp_mask = I915_EXEC_CONSTANTS_MASK;
	switch (instp_mode) {
	case I915_EXEC_CONSTANTS_REL_GENERAL:
	case I915_EXEC_CONSTANTS_ABSOLUTE:
	case I915_EXEC_CONSTANTS_REL_SURFACE:
		if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
			DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
			return -EINVAL;
		}
 
		if (instp_mode != dev_priv->relative_constants_mode) {
			if (INTEL_INFO(dev)->gen < 4) {
				DRM_DEBUG("no rel constants on pre-gen4\n");
				return -EINVAL;
			}
 
			if (INTEL_INFO(dev)->gen > 5 &&
			    instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
				DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
				return -EINVAL;
			}
 
			/* The HW changed the meaning on this bit on gen6 */
			if (INTEL_INFO(dev)->gen >= 6)
				instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
		}
		break;
	default:
		DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
		return -EINVAL;
	}
 
	if (ring == &dev_priv->ring[RCS] &&
	    instp_mode != dev_priv->relative_constants_mode) {
		ret = intel_ring_begin(params->request, 4);
		if (ret)
			return ret;
 
		intel_ring_emit(ring, MI_NOOP);
		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
		intel_ring_emit_reg(ring, INSTPM);
		intel_ring_emit(ring, instp_mask << 16 | instp_mode);
		intel_ring_advance(ring);
 
		dev_priv->relative_constants_mode = instp_mode;
	}
 
	if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
		ret = i915_reset_gen7_sol_offsets(dev, params->request);
		if (ret)
			return ret;
	}
 
	exec_len   = args->batch_len;
	exec_start = params->batch_obj_vm_offset +
		     params->args_batch_start_offset;
 
	if (exec_len == 0)
		exec_len = params->batch_obj->base.size;
 
	ret = ring->dispatch_execbuffer(params->request,
					exec_start, exec_len,
					params->dispatch_flags);
	if (ret)
		return ret;
 
	trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
 
	i915_gem_execbuffer_move_to_active(vmas, params->request);
	i915_gem_execbuffer_retire_commands(params);
 
	return 0;
}
 
/**
 * Find one BSD ring to dispatch the corresponding BSD command.
 * The ring index is returned.
 */
static unsigned int
gen8_dispatch_bsd_ring(struct drm_i915_private *dev_priv, struct drm_file *file)
{
 
	struct drm_i915_file_private *file_priv = file->driver_priv;
 
	/* Check whether the file_priv has already selected one ring. */
 
 
	if ((int)file_priv->bsd_ring < 0) {
 
 
		/* If not, use the ping-pong mechanism to select one. */
		mutex_lock(&dev_priv->dev->struct_mutex);
 
		file_priv->bsd_ring = dev_priv->mm.bsd_ring_dispatch_index;
 
 
 
 
 
		dev_priv->mm.bsd_ring_dispatch_index ^= 1;
 
		mutex_unlock(&dev_priv->dev->struct_mutex);
	}
 
	return file_priv->bsd_ring;
}
 
static struct drm_i915_gem_object *
eb_get_batch(struct eb_vmas *eb)
{
	struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list);
 
	/*
	 * SNA is doing fancy tricks with compressing batch buffers, which leads
	 * to negative relocation deltas. Usually that works out ok since the
	 * relocate address is still positive, except when the batch is placed
	 * very low in the GTT. Ensure this doesn't happen.
	 *
	 * Note that actual hangs have only been observed on gen7, but for
	 * paranoia do it everywhere.
	 */
	if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0)
		vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
 
	return vma->obj;
}
 
#define I915_USER_RINGS (4)
 
static const enum intel_ring_id user_ring_map[I915_USER_RINGS + 1] = {
	[I915_EXEC_DEFAULT]	= RCS,
	[I915_EXEC_RENDER]	= RCS,
	[I915_EXEC_BLT]		= BCS,
	[I915_EXEC_BSD]		= VCS,
	[I915_EXEC_VEBOX]	= VECS
};
 
static int
eb_select_ring(struct drm_i915_private *dev_priv,
	       struct drm_file *file,
	       struct drm_i915_gem_execbuffer2 *args,
	       struct intel_engine_cs **ring)
{
	unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
 
	if (user_ring_id > I915_USER_RINGS) {
		DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
		return -EINVAL;
	}
 
	if ((user_ring_id != I915_EXEC_BSD) &&
	    ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
		DRM_DEBUG("execbuf with non bsd ring but with invalid "
			  "bsd dispatch flags: %d\n", (int)(args->flags));
		return -EINVAL;
	}
 
	if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
		unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
 
		if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
			bsd_idx = gen8_dispatch_bsd_ring(dev_priv, file);
		} else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
			   bsd_idx <= I915_EXEC_BSD_RING2) {
			bsd_idx >>= I915_EXEC_BSD_SHIFT;
			bsd_idx--;
		} else {
			DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
				  bsd_idx);
			return -EINVAL;
		}
 
		*ring = &dev_priv->ring[_VCS(bsd_idx)];
	} else {
		*ring = &dev_priv->ring[user_ring_map[user_ring_id]];
	}
 
	if (!intel_ring_initialized(*ring)) {
		DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
		return -EINVAL;
	}
 
	return 0;
}
 
static int
i915_gem_do_execbuffer(struct drm_device *dev, void *data,
		       struct drm_file *file,
		       struct drm_i915_gem_execbuffer2 *args,
		       struct drm_i915_gem_exec_object2 *exec)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_request *req = NULL;
	struct eb_vmas *eb;
	struct drm_i915_gem_object *batch_obj;
	struct drm_i915_gem_exec_object2 shadow_exec_entry;
	struct intel_engine_cs *ring;
	struct intel_context *ctx;
	struct i915_address_space *vm;
	struct i915_execbuffer_params params_master; /* XXX: will be removed later */
	struct i915_execbuffer_params *params = ¶ms_master;
	const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
	u32 dispatch_flags;
	int ret;
	bool need_relocs;
 
	if (!i915_gem_check_execbuffer(args))
		return -EINVAL;
 
	ret = validate_exec_list(dev, exec, args->buffer_count);
	if (ret)
		return ret;
 
	dispatch_flags = 0;
	if (args->flags & I915_EXEC_SECURE) {
 
		dispatch_flags |= I915_DISPATCH_SECURE;
	}
	if (args->flags & I915_EXEC_IS_PINNED)
		dispatch_flags |= I915_DISPATCH_PINNED;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
	ret = eb_select_ring(dev_priv, file, args, &ring);
 
 
 
 
 
 
 
 
 
 
 
 
 
	if (ret)
 
		return ret;
 
	if (args->buffer_count < 1) {
		DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
		return -EINVAL;
	}
 
	if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
		if (!HAS_RESOURCE_STREAMER(dev)) {
			DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
			return -EINVAL;
		}
		if (ring->id != RCS) {
			DRM_DEBUG("RS is not available on %s\n",
				 ring->name);
			return -EINVAL;
		}
 
		dispatch_flags |= I915_DISPATCH_RS;
	}
 
	intel_runtime_pm_get(dev_priv);
 
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		goto pre_mutex_err;
 
	ctx = i915_gem_validate_context(dev, file, ring, ctx_id);
	if (IS_ERR(ctx)) {
		mutex_unlock(&dev->struct_mutex);
		ret = PTR_ERR(ctx);
		goto pre_mutex_err;
	}
 
	i915_gem_context_reference(ctx);
 
	if (ctx->ppgtt)
		vm = &ctx->ppgtt->base;
	else
		vm = &dev_priv->gtt.base;
 
	memset(¶ms_master, 0x00, sizeof(params_master));
 
	eb = eb_create(args);
	if (eb == NULL) {
		i915_gem_context_unreference(ctx);
		mutex_unlock(&dev->struct_mutex);
		ret = -ENOMEM;
		goto pre_mutex_err;
	}
 
	/* Look up object handles */
	ret = eb_lookup_vmas(eb, exec, args, vm, file);
	if (ret)
		goto err;
 
	/* take note of the batch buffer before we might reorder the lists */
	batch_obj = eb_get_batch(eb);
 
	/* Move the objects en-masse into the GTT, evicting if necessary. */
	need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
	ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs);
	if (ret)
		goto err;
 
	/* The objects are in their final locations, apply the relocations. */
	if (need_relocs)
		ret = i915_gem_execbuffer_relocate(eb);
	if (ret) {
		if (ret == -EFAULT) {
			ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
								eb, exec, ctx);
			BUG_ON(!mutex_is_locked(&dev->struct_mutex));
		}
		if (ret)
			goto err;
	}
 
	/* Set the pending read domains for the batch buffer to COMMAND */
	if (batch_obj->base.pending_write_domain) {
		DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
		ret = -EINVAL;
		goto err;
	}
 
	params->args_batch_start_offset = args->batch_start_offset;
 
#if 0
	if (i915_needs_cmd_parser(ring) && args->batch_len) {
		struct drm_i915_gem_object *parsed_batch_obj;
 
		parsed_batch_obj = i915_gem_execbuffer_parse(ring,
						      &shadow_exec_entry,
						      eb,
						      batch_obj,
						      args->batch_start_offset,
						      args->batch_len,
						      file->is_master);
		if (IS_ERR(parsed_batch_obj)) {
			ret = PTR_ERR(parsed_batch_obj);
			goto err;
		}
 
		/*
		 * parsed_batch_obj == batch_obj means batch not fully parsed:
		 * Accept, but don't promote to secure.
		 */
 
		if (parsed_batch_obj != batch_obj) {
			/*
			 * Batch parsed and accepted:
			 *
			 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
			 * bit from MI_BATCH_BUFFER_START commands issued in
			 * the dispatch_execbuffer implementations. We
			 * specifically don't want that set on batches the
			 * command parser has accepted.
			 */
			dispatch_flags |= I915_DISPATCH_SECURE;
			params->args_batch_start_offset = 0;
			batch_obj = parsed_batch_obj;
		}
	}
#endif
 
	batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
 
	/* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
	 * batch" bit. Hence we need to pin secure batches into the global gtt.
	 * hsw should have this fixed, but bdw mucks it up again. */
	if (dispatch_flags & I915_DISPATCH_SECURE) {
		/*
		 * So on first glance it looks freaky that we pin the batch here
		 * outside of the reservation loop. But:
		 * - The batch is already pinned into the relevant ppgtt, so we
		 *   already have the backing storage fully allocated.
		 * - No other BO uses the global gtt (well contexts, but meh),
		 *   so we don't really have issues with multiple objects not
		 *   fitting due to fragmentation.
		 * So this is actually safe.
		 */
		ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0);
		if (ret)
			goto err;
 
		params->batch_obj_vm_offset = i915_gem_obj_ggtt_offset(batch_obj);
	} else
		params->batch_obj_vm_offset = i915_gem_obj_offset(batch_obj, vm);
 
	/* Allocate a request for this batch buffer nice and early. */
	req = i915_gem_request_alloc(ring, ctx);
	if (IS_ERR(req)) {
		ret = PTR_ERR(req);
		goto err_batch_unpin;
	}
 
	ret = i915_gem_request_add_to_client(req, file);
	if (ret)
		goto err_batch_unpin;
 
	/*
	 * Save assorted stuff away to pass through to *_submission().
	 * NB: This data should be 'persistent' and not local as it will
	 * kept around beyond the duration of the IOCTL once the GPU
	 * scheduler arrives.
	 */
	params->dev                     = dev;
	params->file                    = file;
	params->ring                    = ring;
	params->dispatch_flags          = dispatch_flags;
	params->batch_obj               = batch_obj;
	params->ctx                     = ctx;
	params->request                 = req;
 
	ret = dev_priv->gt.execbuf_submit(params, args, &eb->vmas);
 
err_batch_unpin:
	/*
	 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
	 * batch vma for correctness. For less ugly and less fragility this
	 * needs to be adjusted to also track the ggtt batch vma properly as
	 * active.
	 */
	if (dispatch_flags & I915_DISPATCH_SECURE)
		i915_gem_object_ggtt_unpin(batch_obj);
 
err:
	/* the request owns the ref now */
	i915_gem_context_unreference(ctx);
	eb_destroy(eb);
 
	/*
	 * If the request was created but not successfully submitted then it
	 * must be freed again. If it was submitted then it is being tracked
	 * on the active request list and no clean up is required here.
	 */
	if (ret && !IS_ERR_OR_NULL(req))
		i915_gem_request_cancel(req);
 
	mutex_unlock(&dev->struct_mutex);
 
pre_mutex_err:
	/* intel_gpu_busy should also get a ref, so it will free when the device
	 * is really idle. */
	intel_runtime_pm_put(dev_priv);
	return ret;
}
 
#if 0
/*
 * Legacy execbuffer just creates an exec2 list from the original exec object
 * list array and passes it to the real function.
 */
int
i915_gem_execbuffer(struct drm_device *dev, void *data,
		    struct drm_file *file)
{
	struct drm_i915_gem_execbuffer *args = data;
	struct drm_i915_gem_execbuffer2 exec2;
	struct drm_i915_gem_exec_object *exec_list = NULL;
	struct drm_i915_gem_exec_object2 *exec2_list = NULL;
	int ret, i;
 
	if (args->buffer_count < 1) {
		DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
		return -EINVAL;
	}
 
	/* Copy in the exec list from userland */
	exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
	exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
	if (exec_list == NULL || exec2_list == NULL) {
		DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
			  args->buffer_count);
		drm_free_large(exec_list);
		drm_free_large(exec2_list);
		return -ENOMEM;
	}
	ret = copy_from_user(exec_list,
			     to_user_ptr(args->buffers_ptr),
			     sizeof(*exec_list) * args->buffer_count);
	if (ret != 0) {
		DRM_DEBUG("copy %d exec entries failed %d\n",
			  args->buffer_count, ret);
		drm_free_large(exec_list);
		drm_free_large(exec2_list);
		return -EFAULT;
	}
 
	for (i = 0; i < args->buffer_count; i++) {
		exec2_list[i].handle = exec_list[i].handle;
		exec2_list[i].relocation_count = exec_list[i].relocation_count;
		exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
		exec2_list[i].alignment = exec_list[i].alignment;
		exec2_list[i].offset = exec_list[i].offset;
		if (INTEL_INFO(dev)->gen < 4)
			exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
		else
			exec2_list[i].flags = 0;
	}
 
	exec2.buffers_ptr = args->buffers_ptr;
	exec2.buffer_count = args->buffer_count;
	exec2.batch_start_offset = args->batch_start_offset;
	exec2.batch_len = args->batch_len;
	exec2.DR1 = args->DR1;
	exec2.DR4 = args->DR4;
	exec2.num_cliprects = args->num_cliprects;
	exec2.cliprects_ptr = args->cliprects_ptr;
	exec2.flags = I915_EXEC_RENDER;
	i915_execbuffer2_set_context_id(exec2, 0);
 
	ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
	if (!ret) {
		struct drm_i915_gem_exec_object __user *user_exec_list =
			to_user_ptr(args->buffers_ptr);
 
		/* Copy the new buffer offsets back to the user's exec list. */
		for (i = 0; i < args->buffer_count; i++) {
			exec2_list[i].offset =
				gen8_canonical_addr(exec2_list[i].offset);
			ret = __copy_to_user(&user_exec_list[i].offset,
					     &exec2_list[i].offset,
					     sizeof(user_exec_list[i].offset));
			if (ret) {
				ret = -EFAULT;
				DRM_DEBUG("failed to copy %d exec entries "
					  "back to user (%d)\n",
					  args->buffer_count, ret);
				break;
			}
		}
	}
 
	drm_free_large(exec_list);
	drm_free_large(exec2_list);
	return ret;
}
#endif
 
int
i915_gem_execbuffer2(struct drm_device *dev, void *data,
		     struct drm_file *file)
{
	struct drm_i915_gem_execbuffer2 *args = data;
	struct drm_i915_gem_exec_object2 *exec2_list = NULL;
	int ret;
 
	if (args->buffer_count < 1 ||
	    args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
		DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
		return -EINVAL;
	}
 
	if (args->rsvd2 != 0) {
		DRM_DEBUG("dirty rvsd2 field\n");
		return -EINVAL;
	}
 
	exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
			     GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
	if (exec2_list == NULL) {
		DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
			  args->buffer_count);
		return -ENOMEM;
	}
	ret = copy_from_user(exec2_list,
			     to_user_ptr(args->buffers_ptr),
			     sizeof(*exec2_list) * args->buffer_count);
	if (ret != 0) {
		DRM_DEBUG("copy %d exec entries failed %d\n",
			  args->buffer_count, ret);
        kfree(exec2_list);
        FAIL();
		return -EFAULT;
	}
 
	ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
	if (!ret) {
		/* Copy the new buffer offsets back to the user's exec list. */
		struct drm_i915_gem_exec_object2 __user *user_exec_list =
				   to_user_ptr(args->buffers_ptr);
		int i;
 
		for (i = 0; i < args->buffer_count; i++) {
			exec2_list[i].offset =
				gen8_canonical_addr(exec2_list[i].offset);
			ret = __copy_to_user(&user_exec_list[i].offset,
					     &exec2_list[i].offset,
					     sizeof(user_exec_list[i].offset));
			if (ret) {
				ret = -EFAULT;
				DRM_DEBUG("failed to copy %d exec entries "
					  "back to user\n",
					  args->buffer_count);
				break;
			}
		}
	}
 
    kfree(exec2_list);
	return ret;
}
 
#define>
 
#define>
#define>
#define>
#define>
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Rev 6937	Rev 7144
1	/*	1	/*
2	* Copyright © 2008,2010 Intel Corporation	2	* Copyright © 2008,2010 Intel Corporation
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice (including the next	11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the	12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.	13	* Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21	* IN THE SOFTWARE.	21	* IN THE SOFTWARE.
22	*	22	*
23	* Authors:	23	* Authors:
24	* Eric Anholt	24	* Eric Anholt
25	* Chris Wilson	25	* Chris Wilson
26	*	26	*
27	*/	27	*/
28		28
29	#include	29	#include
30	#include	30	#include
31	#include "i915_drv.h"	31	#include "i915_drv.h"
32	#include "i915_trace.h"	32	#include "i915_trace.h"
33	#include "intel_drv.h"	33	#include "intel_drv.h"
34	#include	34	#include
35	#include	35	#include
36		36
37	#define __EXEC_OBJECT_HAS_PIN (1<<31)	37	#define __EXEC_OBJECT_HAS_PIN (1<<31)
38	#define __EXEC_OBJECT_HAS_FENCE (1<<30)	38	#define __EXEC_OBJECT_HAS_FENCE (1<<30)
39	#define __EXEC_OBJECT_NEEDS_MAP (1<<29)	39	#define __EXEC_OBJECT_NEEDS_MAP (1<<29)
40	#define __EXEC_OBJECT_NEEDS_BIAS (1<<28)	40	#define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
41		41
42	#define BATCH_OFFSET_BIAS (256*1024)	42	#define BATCH_OFFSET_BIAS (256*1024)
43		43
44	struct eb_vmas {	44	struct eb_vmas {
45	struct list_head vmas;	45	struct list_head vmas;
46	int and;	46	int and;
47	union {	47	union {
48	struct i915_vma *lut[0];	48	struct i915_vma *lut[0];
49	struct hlist_head buckets[0];	49	struct hlist_head buckets[0];
50	};	50	};
51	};	51	};
52		52
53	static struct eb_vmas *	53	static struct eb_vmas *
54	eb_create(struct drm_i915_gem_execbuffer2 *args)	54	eb_create(struct drm_i915_gem_execbuffer2 *args)
55	{	55	{
56	struct eb_vmas *eb = NULL;	56	struct eb_vmas *eb = NULL;
57		57
58	if (args->flags & I915_EXEC_HANDLE_LUT) {	58	if (args->flags & I915_EXEC_HANDLE_LUT) {
59	unsigned size = args->buffer_count;	59	unsigned size = args->buffer_count;
60	size = sizeof(struct i915_vma );	60	size = sizeof(struct i915_vma );
61	size += sizeof(struct eb_vmas);	61	size += sizeof(struct eb_vmas);
62	eb = kmalloc(size, GFP_TEMPORARY \| __GFP_NOWARN \| __GFP_NORETRY);	62	eb = kmalloc(size, GFP_TEMPORARY \| __GFP_NOWARN \| __GFP_NORETRY);
63	}	63	}
64		64
65	if (eb == NULL) {	65	if (eb == NULL) {
66	unsigned size = args->buffer_count;	66	unsigned size = args->buffer_count;
67	unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;	67	unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
68	BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));	68	BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
69	while (count > 2*size)	69	while (count > 2*size)
70	count >>= 1;	70	count >>= 1;
71	eb = kzalloc(count*sizeof(struct hlist_head) +	71	eb = kzalloc(count*sizeof(struct hlist_head) +
72	sizeof(struct eb_vmas),	72	sizeof(struct eb_vmas),
73	GFP_TEMPORARY);	73	GFP_TEMPORARY);
74	if (eb == NULL)	74	if (eb == NULL)
75	return eb;	75	return eb;
76		76
77	eb->and = count - 1;	77	eb->and = count - 1;
78	} else	78	} else
79	eb->and = -args->buffer_count;	79	eb->and = -args->buffer_count;
80		80
81	INIT_LIST_HEAD(&eb->vmas);	81	INIT_LIST_HEAD(&eb->vmas);
82	return eb;	82	return eb;
83	}	83	}
84		84
85	static void	85	static void
86	eb_reset(struct eb_vmas *eb)	86	eb_reset(struct eb_vmas *eb)
87	{	87	{
88	if (eb->and >= 0)	88	if (eb->and >= 0)
89	memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));	89	memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
90	}	90	}
91		91
92	static int	92	static int
93	eb_lookup_vmas(struct eb_vmas *eb,	93	eb_lookup_vmas(struct eb_vmas *eb,
94	struct drm_i915_gem_exec_object2 *exec,	94	struct drm_i915_gem_exec_object2 *exec,
95	const struct drm_i915_gem_execbuffer2 *args,	95	const struct drm_i915_gem_execbuffer2 *args,
96	struct i915_address_space *vm,	96	struct i915_address_space *vm,
97	struct drm_file *file)	97	struct drm_file *file)
98	{	98	{
99	struct drm_i915_gem_object *obj;	99	struct drm_i915_gem_object *obj;
100	struct list_head objects;	100	struct list_head objects;
101	int i, ret;	101	int i, ret;
102		102
103	INIT_LIST_HEAD(&objects);	103	INIT_LIST_HEAD(&objects);
104	spin_lock(&file->table_lock);	104	spin_lock(&file->table_lock);
105	/* Grab a reference to the object and release the lock so we can lookup	105	/* Grab a reference to the object and release the lock so we can lookup
106	* or create the VMA without using GFP_ATOMIC */	106	* or create the VMA without using GFP_ATOMIC */
107	for (i = 0; i < args->buffer_count; i++) {	107	for (i = 0; i < args->buffer_count; i++) {
108	obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));	108	obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
109	if (obj == NULL) {	109	if (obj == NULL) {
110	spin_unlock(&file->table_lock);	110	spin_unlock(&file->table_lock);
111	DRM_DEBUG("Invalid object handle %d at index %d\n",	111	DRM_DEBUG("Invalid object handle %d at index %d\n",
112	exec[i].handle, i);	112	exec[i].handle, i);
113	ret = -ENOENT;	113	ret = -ENOENT;
114	goto err;	114	goto err;
115	}	115	}
116		116
117	if (!list_empty(&obj->obj_exec_link)) {	117	if (!list_empty(&obj->obj_exec_link)) {
118	spin_unlock(&file->table_lock);	118	spin_unlock(&file->table_lock);
119	DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",	119	DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
120	obj, exec[i].handle, i);	120	obj, exec[i].handle, i);
121	ret = -EINVAL;	121	ret = -EINVAL;
122	goto err;	122	goto err;
123	}	123	}
124		124
125	drm_gem_object_reference(&obj->base);	125	drm_gem_object_reference(&obj->base);
126	list_add_tail(&obj->obj_exec_link, &objects);	126	list_add_tail(&obj->obj_exec_link, &objects);
127	}	127	}
128	spin_unlock(&file->table_lock);	128	spin_unlock(&file->table_lock);
129		129
130	i = 0;	130	i = 0;
131	while (!list_empty(&objects)) {	131	while (!list_empty(&objects)) {
132	struct i915_vma *vma;	132	struct i915_vma *vma;
133		133
134	obj = list_first_entry(&objects,	134	obj = list_first_entry(&objects,
135	struct drm_i915_gem_object,	135	struct drm_i915_gem_object,
136	obj_exec_link);	136	obj_exec_link);
137		137
138	/*	138	/*
139	* NOTE: We can leak any vmas created here when something fails	139	* NOTE: We can leak any vmas created here when something fails
140	* later on. But that's no issue since vma_unbind can deal with	140	* later on. But that's no issue since vma_unbind can deal with
141	* vmas which are not actually bound. And since only	141	* vmas which are not actually bound. And since only
142	* lookup_or_create exists as an interface to get at the vma	142	* lookup_or_create exists as an interface to get at the vma
143	* from the (obj, vm) we don't run the risk of creating	143	* from the (obj, vm) we don't run the risk of creating
144	* duplicated vmas for the same vm.	144	* duplicated vmas for the same vm.
145	*/	145	*/
146	vma = i915_gem_obj_lookup_or_create_vma(obj, vm);	146	vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
147	if (IS_ERR(vma)) {	147	if (IS_ERR(vma)) {
148	DRM_DEBUG("Failed to lookup VMA\n");	148	DRM_DEBUG("Failed to lookup VMA\n");
149	ret = PTR_ERR(vma);	149	ret = PTR_ERR(vma);
150	goto err;	150	goto err;
151	}	151	}
152		152
153	/* Transfer ownership from the objects list to the vmas list. */	153	/* Transfer ownership from the objects list to the vmas list. */
154	list_add_tail(&vma->exec_list, &eb->vmas);	154	list_add_tail(&vma->exec_list, &eb->vmas);
155	list_del_init(&obj->obj_exec_link);	155	list_del_init(&obj->obj_exec_link);
156		156
157	vma->exec_entry = &exec[i];	157	vma->exec_entry = &exec[i];
158	if (eb->and < 0) {	158	if (eb->and < 0) {
159	eb->lut[i] = vma;	159	eb->lut[i] = vma;
160	} else {	160	} else {
161	uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;	161	uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
162	vma->exec_handle = handle;	162	vma->exec_handle = handle;
163	hlist_add_head(&vma->exec_node,	163	hlist_add_head(&vma->exec_node,
164	&eb->buckets[handle & eb->and]);	164	&eb->buckets[handle & eb->and]);
165	}	165	}
166	++i;	166	++i;
167	}	167	}
168		168
169	return 0;	169	return 0;
170		170
171		171
172	err:	172	err:
173	while (!list_empty(&objects)) {	173	while (!list_empty(&objects)) {
174	obj = list_first_entry(&objects,	174	obj = list_first_entry(&objects,
175	struct drm_i915_gem_object,	175	struct drm_i915_gem_object,
176	obj_exec_link);	176	obj_exec_link);
177	list_del_init(&obj->obj_exec_link);	177	list_del_init(&obj->obj_exec_link);
178	drm_gem_object_unreference(&obj->base);	178	drm_gem_object_unreference(&obj->base);
179	}	179	}
180	/*	180	/*
181	* Objects already transfered to the vmas list will be unreferenced by	181	* Objects already transfered to the vmas list will be unreferenced by
182	* eb_destroy.	182	* eb_destroy.
183	*/	183	*/
184		184
185	return ret;	185	return ret;
186	}	186	}
187		187
188	static struct i915_vma eb_get_vma(struct eb_vmas eb, unsigned long handle)	188	static struct i915_vma eb_get_vma(struct eb_vmas eb, unsigned long handle)
189	{	189	{
190	if (eb->and < 0) {	190	if (eb->and < 0) {
191	if (handle >= -eb->and)	191	if (handle >= -eb->and)
192	return NULL;	192	return NULL;
193	return eb->lut[handle];	193	return eb->lut[handle];
194	} else {	194	} else {
195	struct hlist_head *head;	195	struct hlist_head *head;
196	struct hlist_node *node;	-
197		-
198	head = &eb->buckets[handle & eb->and];	-
199	hlist_for_each(node, head) {	-
200	struct i915_vma *vma;	196	struct i915_vma *vma;
-		197
201		198	head = &eb->buckets[handle & eb->and];
202	vma = hlist_entry(node, struct i915_vma, exec_node);	199	hlist_for_each_entry(vma, head, exec_node) {
203	if (vma->exec_handle == handle)	200	if (vma->exec_handle == handle)
204	return vma;	201	return vma;
205	}	202	}
206	return NULL;	203	return NULL;
207	}	204	}
208	}	205	}
209		206
210	static void	207	static void
211	i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)	208	i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
212	{	209	{
213	struct drm_i915_gem_exec_object2 *entry;	210	struct drm_i915_gem_exec_object2 *entry;
214	struct drm_i915_gem_object *obj = vma->obj;	211	struct drm_i915_gem_object *obj = vma->obj;
215		212
216	if (!drm_mm_node_allocated(&vma->node))	213	if (!drm_mm_node_allocated(&vma->node))
217	return;	214	return;
218		215
219	entry = vma->exec_entry;	216	entry = vma->exec_entry;
220		217
221	if (entry->flags & __EXEC_OBJECT_HAS_FENCE)	218	if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
222	i915_gem_object_unpin_fence(obj);	219	i915_gem_object_unpin_fence(obj);
223		220
224	if (entry->flags & __EXEC_OBJECT_HAS_PIN)	221	if (entry->flags & __EXEC_OBJECT_HAS_PIN)
225	vma->pin_count--;	222	vma->pin_count--;
226		223
227	entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE \| __EXEC_OBJECT_HAS_PIN);	224	entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE \| __EXEC_OBJECT_HAS_PIN);
228	}	225	}
229		226
230	static void eb_destroy(struct eb_vmas *eb)	227	static void eb_destroy(struct eb_vmas *eb)
231	{	228	{
232	while (!list_empty(&eb->vmas)) {	229	while (!list_empty(&eb->vmas)) {
233	struct i915_vma *vma;	230	struct i915_vma *vma;
234		231
235	vma = list_first_entry(&eb->vmas,	232	vma = list_first_entry(&eb->vmas,
236	struct i915_vma,	233	struct i915_vma,
237	exec_list);	234	exec_list);
238	list_del_init(&vma->exec_list);	235	list_del_init(&vma->exec_list);
239	i915_gem_execbuffer_unreserve_vma(vma);	236	i915_gem_execbuffer_unreserve_vma(vma);
240	drm_gem_object_unreference(&vma->obj->base);	237	drm_gem_object_unreference(&vma->obj->base);
241	}	238	}
242	kfree(eb);	239	kfree(eb);
243	}	240	}
244		241
245	static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)	242	static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
246	{	243	{
247	return (HAS_LLC(obj->base.dev) \|\|	244	return (HAS_LLC(obj->base.dev) \|\|
248	obj->base.write_domain == I915_GEM_DOMAIN_CPU \|\|	245	obj->base.write_domain == I915_GEM_DOMAIN_CPU \|\|
249	obj->cache_level != I915_CACHE_NONE);	246	obj->cache_level != I915_CACHE_NONE);
250	}	247	}
251		248
252	/* Used to convert any address to canonical form.	249	/* Used to convert any address to canonical form.
253	* Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,	250	* Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
254	* MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the	251	* MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
255	* addresses to be in a canonical form:	252	* addresses to be in a canonical form:
256	* "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct	253	* "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
257	* canonical form [63:48] == [47]."	254	* canonical form [63:48] == [47]."
258	*/	255	*/
259	#define GEN8_HIGH_ADDRESS_BIT 47	256	#define GEN8_HIGH_ADDRESS_BIT 47
260	static inline uint64_t gen8_canonical_addr(uint64_t address)	257	static inline uint64_t gen8_canonical_addr(uint64_t address)
261	{	258	{
262	return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);	259	return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
263	}	260	}
264		261
265	static inline uint64_t gen8_noncanonical_addr(uint64_t address)	262	static inline uint64_t gen8_noncanonical_addr(uint64_t address)
266	{	263	{
267	return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1);	264	return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1);
268	}	265	}
269		266
270	static inline uint64_t	267	static inline uint64_t
271	relocation_target(struct drm_i915_gem_relocation_entry *reloc,	268	relocation_target(struct drm_i915_gem_relocation_entry *reloc,
272	uint64_t target_offset)	269	uint64_t target_offset)
273	{	270	{
274	return gen8_canonical_addr((int)reloc->delta + target_offset);	271	return gen8_canonical_addr((int)reloc->delta + target_offset);
275	}	272	}
276		273
277	static int	274	static int
278	relocate_entry_cpu(struct drm_i915_gem_object *obj,	275	relocate_entry_cpu(struct drm_i915_gem_object *obj,
279	struct drm_i915_gem_relocation_entry *reloc,	276	struct drm_i915_gem_relocation_entry *reloc,
280	uint64_t target_offset)	277	uint64_t target_offset)
281	{	278	{
282	struct drm_device *dev = obj->base.dev;	279	struct drm_device *dev = obj->base.dev;
283	uint32_t page_offset = offset_in_page(reloc->offset);	280	uint32_t page_offset = offset_in_page(reloc->offset);
284	uint64_t delta = relocation_target(reloc, target_offset);	281	uint64_t delta = relocation_target(reloc, target_offset);
285	char *vaddr;	282	char *vaddr;
286	int ret;	283	int ret;
287		284
288	ret = i915_gem_object_set_to_cpu_domain(obj, true);	285	ret = i915_gem_object_set_to_cpu_domain(obj, true);
289	if (ret)	286	if (ret)
290	return ret;	287	return ret;
291		288
292	vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,	289	vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
293	reloc->offset >> PAGE_SHIFT));	290	reloc->offset >> PAGE_SHIFT));
294	(uint32_t )(vaddr + page_offset) = lower_32_bits(delta);	291	(uint32_t )(vaddr + page_offset) = lower_32_bits(delta);
295		292
296	if (INTEL_INFO(dev)->gen >= 8) {	293	if (INTEL_INFO(dev)->gen >= 8) {
297	page_offset = offset_in_page(page_offset + sizeof(uint32_t));	294	page_offset = offset_in_page(page_offset + sizeof(uint32_t));
298		295
299	if (page_offset == 0) {	296	if (page_offset == 0) {
300	kunmap_atomic(vaddr);	297	kunmap_atomic(vaddr);
301	vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,	298	vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
302	(reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));	299	(reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
303	}	300	}
304		301
305	(uint32_t )(vaddr + page_offset) = upper_32_bits(delta);	302	(uint32_t )(vaddr + page_offset) = upper_32_bits(delta);
306	}	303	}
307		304
308	kunmap_atomic(vaddr);	305	kunmap_atomic(vaddr);
309		306
310	return 0;	307	return 0;
311	}	308	}
312		309
313	static int	310	static int
314	relocate_entry_gtt(struct drm_i915_gem_object *obj,	311	relocate_entry_gtt(struct drm_i915_gem_object *obj,
315	struct drm_i915_gem_relocation_entry *reloc,	312	struct drm_i915_gem_relocation_entry *reloc,
316	uint64_t target_offset)	313	uint64_t target_offset)
317	{	314	{
318	struct drm_device *dev = obj->base.dev;	315	struct drm_device *dev = obj->base.dev;
319	struct drm_i915_private *dev_priv = dev->dev_private;	316	struct drm_i915_private *dev_priv = dev->dev_private;
320	uint64_t delta = relocation_target(reloc, target_offset);	317	uint64_t delta = relocation_target(reloc, target_offset);
321	uint64_t offset;	318	uint64_t offset;
322	void __iomem *reloc_page;	319	void __iomem *reloc_page;
323	int ret;	320	int ret;
324		321
325	ret = i915_gem_object_set_to_gtt_domain(obj, true);	322	ret = i915_gem_object_set_to_gtt_domain(obj, true);
326	if (ret)	323	if (ret)
327	return ret;	324	return ret;
328		325
329	ret = i915_gem_object_put_fence(obj);	326	ret = i915_gem_object_put_fence(obj);
330	if (ret)	327	if (ret)
331	return ret;	328	return ret;
332		329
333	/* Map the page containing the relocation we're going to perform. */	330	/* Map the page containing the relocation we're going to perform. */
334	offset = i915_gem_obj_ggtt_offset(obj);	331	offset = i915_gem_obj_ggtt_offset(obj);
335	offset += reloc->offset;	332	offset += reloc->offset;
336	MapPage(dev_priv->gtt.mappable,dev_priv->gtt.mappable_base +	333	reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
337	(offset & PAGE_MASK), PG_SW);	334	offset & PAGE_MASK);
338	reloc_page = dev_priv->gtt.mappable;	-
339	iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset));	335	iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset));
-		336
-		337	if (INTEL_INFO(dev)->gen >= 8) {
-		338	offset += sizeof(uint32_t);
-		339
340		340	if (offset_in_page(offset) == 0) {
-		341	io_mapping_unmap_atomic(reloc_page);
-		342	reloc_page =
-		343	io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
-		344	offset);
-		345	}
-		346
-		347	iowrite32(upper_32_bits(delta),
-		348	reloc_page + offset_in_page(offset));
-		349	}
-		350
341	// io_mapping_unmap_atomic(reloc_page);	351	io_mapping_unmap_atomic(reloc_page);
342		352
343	return 0;	353	return 0;
344	}	354	}
345		355
346	static void	356	static void
347	clflush_write32(void *addr, uint32_t value)	357	clflush_write32(void *addr, uint32_t value)
348	{	358	{
349	/* This is not a fast path, so KISS. */	359	/* This is not a fast path, so KISS. */
350	drm_clflush_virt_range(addr, sizeof(uint32_t));	360	drm_clflush_virt_range(addr, sizeof(uint32_t));
351	(uint32_t )addr = value;	361	(uint32_t )addr = value;
352	drm_clflush_virt_range(addr, sizeof(uint32_t));	362	drm_clflush_virt_range(addr, sizeof(uint32_t));
353	}	363	}
354		364
355	static int	365	static int
356	relocate_entry_clflush(struct drm_i915_gem_object *obj,	366	relocate_entry_clflush(struct drm_i915_gem_object *obj,
357	struct drm_i915_gem_relocation_entry *reloc,	367	struct drm_i915_gem_relocation_entry *reloc,
358	uint64_t target_offset)	368	uint64_t target_offset)
359	{	369	{
360	struct drm_device *dev = obj->base.dev;	370	struct drm_device *dev = obj->base.dev;
361	uint32_t page_offset = offset_in_page(reloc->offset);	371	uint32_t page_offset = offset_in_page(reloc->offset);
362	uint64_t delta = relocation_target(reloc, target_offset);	372	uint64_t delta = relocation_target(reloc, target_offset);
363	char *vaddr;	373	char *vaddr;
364	int ret;	374	int ret;
365		375
366	ret = i915_gem_object_set_to_gtt_domain(obj, true);	376	ret = i915_gem_object_set_to_gtt_domain(obj, true);
367	if (ret)	377	if (ret)
368	return ret;	378	return ret;
369		379
370	vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,	380	vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
371	reloc->offset >> PAGE_SHIFT));	381	reloc->offset >> PAGE_SHIFT));
372	clflush_write32(vaddr + page_offset, lower_32_bits(delta));	382	clflush_write32(vaddr + page_offset, lower_32_bits(delta));
373		383
374	if (INTEL_INFO(dev)->gen >= 8) {	384	if (INTEL_INFO(dev)->gen >= 8) {
375	page_offset = offset_in_page(page_offset + sizeof(uint32_t));	385	page_offset = offset_in_page(page_offset + sizeof(uint32_t));
376		386
377	if (page_offset == 0) {	387	if (page_offset == 0) {
378	kunmap_atomic(vaddr);	388	kunmap_atomic(vaddr);
379	vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,	389	vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
380	(reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));	390	(reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
381	}	391	}
382		392
383	clflush_write32(vaddr + page_offset, upper_32_bits(delta));	393	clflush_write32(vaddr + page_offset, upper_32_bits(delta));
384	}	394	}
385		395
386	kunmap_atomic(vaddr);	396	kunmap_atomic(vaddr);
387		397
388	return 0;	398	return 0;
389	}	399	}
390		400
391	static int	401	static int
392	i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,	402	i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
393	struct eb_vmas *eb,	403	struct eb_vmas *eb,
394	struct drm_i915_gem_relocation_entry *reloc)	404	struct drm_i915_gem_relocation_entry *reloc)
395	{	405	{
396	struct drm_device *dev = obj->base.dev;	406	struct drm_device *dev = obj->base.dev;
397	struct drm_gem_object *target_obj;	407	struct drm_gem_object *target_obj;
398	struct drm_i915_gem_object *target_i915_obj;	408	struct drm_i915_gem_object *target_i915_obj;
399	struct i915_vma *target_vma;	409	struct i915_vma *target_vma;
400	uint64_t target_offset;	410	uint64_t target_offset;
401	int ret;	411	int ret;
402		412
403	/* we've already hold a reference to all valid objects */	413	/* we've already hold a reference to all valid objects */
404	target_vma = eb_get_vma(eb, reloc->target_handle);	414	target_vma = eb_get_vma(eb, reloc->target_handle);
405	if (unlikely(target_vma == NULL))	415	if (unlikely(target_vma == NULL))
406	return -ENOENT;	416	return -ENOENT;
407	target_i915_obj = target_vma->obj;	417	target_i915_obj = target_vma->obj;
408	target_obj = &target_vma->obj->base;	418	target_obj = &target_vma->obj->base;
409		419
410	target_offset = gen8_canonical_addr(target_vma->node.start);	420	target_offset = gen8_canonical_addr(target_vma->node.start);
411		421
412	/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and	422	/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
413	* pipe_control writes because the gpu doesn't properly redirect them	423	* pipe_control writes because the gpu doesn't properly redirect them
414	* through the ppgtt for non_secure batchbuffers. */	424	* through the ppgtt for non_secure batchbuffers. */
415	if (unlikely(IS_GEN6(dev) &&	425	if (unlikely(IS_GEN6(dev) &&
416	reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {	426	reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
417	ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,	427	ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
418	PIN_GLOBAL);	428	PIN_GLOBAL);
419	if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))	429	if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))
420	return ret;	430	return ret;
421	}	431	}
422		432
423	/* Validate that the target is in a valid r/w GPU domain */	433	/* Validate that the target is in a valid r/w GPU domain */
424	if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {	434	if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
425	DRM_DEBUG("reloc with multiple write domains: "	435	DRM_DEBUG("reloc with multiple write domains: "
426	"obj %p target %d offset %d "	436	"obj %p target %d offset %d "
427	"read %08x write %08x",	437	"read %08x write %08x",
428	obj, reloc->target_handle,	438	obj, reloc->target_handle,
429	(int) reloc->offset,	439	(int) reloc->offset,
430	reloc->read_domains,	440	reloc->read_domains,
431	reloc->write_domain);	441	reloc->write_domain);
432	return -EINVAL;	442	return -EINVAL;
433	}	443	}
434	if (unlikely((reloc->write_domain \| reloc->read_domains)	444	if (unlikely((reloc->write_domain \| reloc->read_domains)
435	& ~I915_GEM_GPU_DOMAINS)) {	445	& ~I915_GEM_GPU_DOMAINS)) {
436	DRM_DEBUG("reloc with read/write non-GPU domains: "	446	DRM_DEBUG("reloc with read/write non-GPU domains: "
437	"obj %p target %d offset %d "	447	"obj %p target %d offset %d "
438	"read %08x write %08x",	448	"read %08x write %08x",
439	obj, reloc->target_handle,	449	obj, reloc->target_handle,
440	(int) reloc->offset,	450	(int) reloc->offset,
441	reloc->read_domains,	451	reloc->read_domains,
442	reloc->write_domain);	452	reloc->write_domain);
443	return -EINVAL;	453	return -EINVAL;
444	}	454	}
445		455
446	target_obj->pending_read_domains \|= reloc->read_domains;	456	target_obj->pending_read_domains \|= reloc->read_domains;
447	target_obj->pending_write_domain \|= reloc->write_domain;	457	target_obj->pending_write_domain \|= reloc->write_domain;
448		458
449	/* If the relocation already has the right value in it, no	459	/* If the relocation already has the right value in it, no
450	* more work needs to be done.	460	* more work needs to be done.
451	*/	461	*/
452	if (target_offset == reloc->presumed_offset)	462	if (target_offset == reloc->presumed_offset)
453	return 0;	463	return 0;
454		464
455	/* Check that the relocation address is valid... */	465	/* Check that the relocation address is valid... */
456	if (unlikely(reloc->offset >	466	if (unlikely(reloc->offset >
457	obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {	467	obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
458	DRM_DEBUG("Relocation beyond object bounds: "	468	DRM_DEBUG("Relocation beyond object bounds: "
459	"obj %p target %d offset %d size %d.\n",	469	"obj %p target %d offset %d size %d.\n",
460	obj, reloc->target_handle,	470	obj, reloc->target_handle,
461	(int) reloc->offset,	471	(int) reloc->offset,
462	(int) obj->base.size);	472	(int) obj->base.size);
463	return -EINVAL;	473	return -EINVAL;
464	}	474	}
465	if (unlikely(reloc->offset & 3)) {	475	if (unlikely(reloc->offset & 3)) {
466	DRM_DEBUG("Relocation not 4-byte aligned: "	476	DRM_DEBUG("Relocation not 4-byte aligned: "
467	"obj %p target %d offset %d.\n",	477	"obj %p target %d offset %d.\n",
468	obj, reloc->target_handle,	478	obj, reloc->target_handle,
469	(int) reloc->offset);	479	(int) reloc->offset);
470	return -EINVAL;	480	return -EINVAL;
471	}	481	}
472		482
473	/* We can't wait for rendering with pagefaults disabled */	483	/* We can't wait for rendering with pagefaults disabled */
474		484
475	if (use_cpu_reloc(obj))	485	if (use_cpu_reloc(obj))
476	ret = relocate_entry_cpu(obj, reloc, target_offset);	486	ret = relocate_entry_cpu(obj, reloc, target_offset);
477	else if (obj->map_and_fenceable)	487	else if (obj->map_and_fenceable)
478	ret = relocate_entry_gtt(obj, reloc, target_offset);	488	ret = relocate_entry_gtt(obj, reloc, target_offset);
479	else if (1)	489	else if (1)
480	ret = relocate_entry_clflush(obj, reloc, target_offset);	490	ret = relocate_entry_clflush(obj, reloc, target_offset);
481	else {	491	else {
482	WARN_ONCE(1, "Impossible case in relocation handling\n");	492	WARN_ONCE(1, "Impossible case in relocation handling\n");
483	ret = -ENODEV;	493	ret = -ENODEV;
484	}	494	}
485		495

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(root)/drivers/video/drm/i915/i915_gem_execbuffer.c @ 4106 – Rev 6937 → 7144