WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_gem_execbuffer.c

 #include "intel_drv.h"
 #include
 #define  __EXEC_OBJECT_HAS_PIN (1<<31)
+#define  __EXEC_OBJECT_HAS_FENCE (1<<30)
-#define  __EXEC_OBJECT_HAS_FENCE (1<<30)
+#define  __EXEC_OBJECT_NEEDS_MAP (1<<29)
 #define  __EXEC_OBJECT_NEEDS_BIAS (1<<28)
 		  struct drm_i915_gem_exec_object2 *exec,
 		  const struct drm_i915_gem_execbuffer2 *args,
 	       struct i915_address_space *vm,
 		  struct drm_file *file)
+{
-	struct drm_i915_private *dev_priv = vm->dev->dev_private;
 	struct drm_i915_gem_object *obj;
 	struct list_head objects;
 	int i, ret;
 	spin_unlock(&file->table_lock);
 	i = 0;
 	while (!list_empty(&objects)) {
-		struct i915_vma *vma;
-		struct i915_address_space *bind_vm = vm;
-		if (exec[i].flags & EXEC_OBJECT_NEEDS_GTT &&
-		    USES_FULL_PPGTT(vm->dev)) {
-			ret = -EINVAL;
-			goto err;
-		}
-		/* If we have secure dispatch, or the userspace assures us that
-		 * they know what they're doing, use the GGTT VM.
-		 */
-		if (((args->flags & I915_EXEC_SECURE) &&
-		    (i == (args->buffer_count - 1))))
-			bind_vm = &dev_priv->gtt.base;
+		struct i915_vma *vma;
 		obj = list_first_entry(&objects,
 		 * vmas which are not actually bound. And since only
 		 * lookup_or_create exists as an interface to get at the vma
 		 * from the (obj, vm) we don't run the risk of creating
 		 * duplicated vmas for the same vm.
 		 */
-		vma = i915_gem_obj_lookup_or_create_vma(obj, bind_vm);
+		vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
 		if (IS_ERR(vma)) {
 			DRM_DEBUG("Failed to lookup VMA\n");
 			ret = PTR_ERR(vma);
 			goto err;
+		}
 relocate_entry_cpu(struct drm_i915_gem_object *obj,
 		   struct drm_i915_gem_relocation_entry *reloc,
 		   uint64_t target_offset)
+{
     struct drm_device *dev = obj->base.dev;
-    struct drm_i915_private *dev_priv = dev->dev_private;
     uint32_t page_offset = offset_in_page(reloc->offset);
 	uint64_t delta = reloc->delta + target_offset;
 	char *vaddr;
 	int ret;
 	ret = i915_gem_object_set_to_cpu_domain(obj, true);
 	if (ret)
 		return ret;
-	vaddr = (char*)dev_priv->gtt.mappable+4096;
+	vaddr = kmap_atomic(i915_gem_object_get_page(obj,
-	MapPage(vaddr,(addr_t)i915_gem_object_get_page(obj,reloc->offset >> PAGE_SHIFT), PG_SW);
+				reloc->offset >> PAGE_SHIFT));
 	*(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta);
+	if (INTEL_INFO(dev)->gen >= 8) {
-	if (INTEL_INFO(dev)->gen >= 8) {
+		page_offset = offset_in_page(page_offset + sizeof(uint32_t));
-		page_offset = offset_in_page(page_offset + sizeof(uint32_t));
 		if (page_offset == 0) {
-		if (page_offset == 0) {
+			kunmap_atomic(vaddr);
-			MapPage(vaddr,(addr_t)i915_gem_object_get_page(obj,
+			vaddr = kmap_atomic(i915_gem_object_get_page(obj,
+			    (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
+		}
 			    (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT), PG_SW);
 		*(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta);
+	}
 		*(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta);
 		   uint64_t target_offset)
+{
 	struct drm_device *dev = obj->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint64_t delta = reloc->delta + target_offset;
-	uint32_t __iomem *reloc_entry;
+	uint64_t offset;
 	void __iomem *reloc_page;
 	int ret;
 	ret = i915_gem_object_set_to_gtt_domain(obj, true);
 	ret = i915_gem_object_put_fence(obj);
 	if (ret)
 		return ret;
 	/* Map the page containing the relocation we're going to perform.  */
+	offset = i915_gem_obj_ggtt_offset(obj);
-	reloc->offset += i915_gem_obj_ggtt_offset(obj);
+	offset += reloc->offset;
     MapPage(dev_priv->gtt.mappable,dev_priv->gtt.mappable_base +
-                                 (reloc->offset & PAGE_MASK), PG_SW);
+                                 (offset & PAGE_MASK), PG_SW);
-	reloc_page = dev_priv->gtt.mappable;
-	reloc_entry = (uint32_t __iomem *)
-		(reloc_page + offset_in_page(reloc->offset));
+	reloc_page = dev_priv->gtt.mappable;
+	iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset));
 	iowrite32(lower_32_bits(delta), reloc_entry);
 	/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
 	 * pipe_control writes because the gpu doesn't properly redirect them
 	 * through the ppgtt for non_secure batchbuffers. */
 	if (unlikely(IS_GEN6(dev) &&
 	    reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
-	    !target_i915_obj->has_global_gtt_mapping)) {
+	    !(target_vma->bound & GLOBAL_BIND)))
-		struct i915_vma *vma =
-			list_first_entry(&target_i915_obj->vma_list,
+		target_vma->bind_vma(target_vma, target_i915_obj->cache_level,
-					 typeof(*vma), vma_link);
+				GLOBAL_BIND);
-		vma->bind_vma(vma, target_i915_obj->cache_level, GLOBAL_BIND);
-	}
 	/* Validate that the target is in a valid r/w GPU domain */
 	if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
 		DRM_DEBUG("reloc with multiple write domains: "
 	return ret;
+}
-static int
-need_reloc_mappable(struct i915_vma *vma)
-{
-	struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
-	return entry->relocation_count && !use_cpu_reloc(vma->obj) &&
-		i915_is_ggtt(vma->vm);
-}
 static int
 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
 				struct intel_engine_cs *ring,
 				   bool *need_reloc)
+{
-	struct drm_i915_gem_object *obj = vma->obj;
-	struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
-	bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
+	struct drm_i915_gem_object *obj = vma->obj;
-	bool need_fence;
+	struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 	uint64_t flags;
-	int ret;
-	flags = 0;
+	int ret;
-	need_fence =
-		has_fenced_gpu_access &&
-		entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
-		obj->tiling_mode != I915_TILING_NONE;
-	if (need_fence || need_reloc_mappable(vma))
+	flags = 0;
-		flags |= PIN_MAPPABLE;
+	if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
 		flags |= PIN_GLOBAL | PIN_MAPPABLE;
 	if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
 	if (ret)
 		return ret;
-	entry->flags |= __EXEC_OBJECT_HAS_PIN;
 	entry->flags |= __EXEC_OBJECT_HAS_PIN;
 	if (has_fenced_gpu_access) {
 		if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
 			ret = i915_gem_object_get_fence(obj);
 			if (ret)
 				return ret;
-			if (i915_gem_object_pin_fence(obj))
-				entry->flags |= __EXEC_OBJECT_HAS_FENCE;
-			obj->pending_fenced_gpu_access = true;
+			if (i915_gem_object_pin_fence(obj))
 				entry->flags |= __EXEC_OBJECT_HAS_FENCE;
+	}
 	return 0;
+}
 static bool
-eb_vma_misplaced(struct i915_vma *vma, bool has_fenced_gpu_access)
+need_reloc_mappable(struct i915_vma *vma)
-{
-	struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
+{
-	struct drm_i915_gem_object *obj = vma->obj;
+	struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
-	bool need_fence, need_mappable;
+	if (entry->relocation_count == 0)
+		return false;
+	if (!i915_is_ggtt(vma->vm))
-	need_fence =
+		return false;
+	/* See also use_cpu_reloc() */
-		has_fenced_gpu_access &&
+	if (HAS_LLC(vma->obj->base.dev))
+		return false;
+	if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
+		return false;
+	return true;
+}
+static bool
+eb_vma_misplaced(struct i915_vma *vma)
-		entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
+{
-		obj->tiling_mode != I915_TILING_NONE;
+	struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
-	need_mappable = need_fence || need_reloc_mappable(vma);
+	struct drm_i915_gem_object *obj = vma->obj;
-	WARN_ON((need_mappable || need_fence) &&
+	WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
 	       !i915_is_ggtt(vma->vm));
 	if (entry->alignment &&
 	    vma->node.start & (entry->alignment - 1))
 		return true;
 	struct i915_address_space *vm;
 	struct list_head ordered_vmas;
 	bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
 	int retry;
-	if (list_empty(vmas))
-		return 0;
 	i915_gem_retire_requests_ring(ring);
 		vma = list_first_entry(vmas, struct i915_vma, exec_list);
 		obj = vma->obj;
+		entry = vma->exec_entry;
-		entry = vma->exec_entry;
+		if (!has_fenced_gpu_access)
-		need_fence =
+			entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
-			has_fenced_gpu_access &&
+		need_fence =
 			entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 			obj->tiling_mode != I915_TILING_NONE;
+		need_mappable = need_fence || need_reloc_mappable(vma);
 		need_mappable = need_fence || need_reloc_mappable(vma);
+		if (need_mappable) {
-		if (need_mappable)
+			entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
 			list_move(&vma->exec_list, &ordered_vmas);
-		else
+		} else
-			list_move_tail(&vma->exec_list, &ordered_vmas);
 			list_move_tail(&vma->exec_list, &ordered_vmas);
 		obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
-		obj->base.pending_write_domain = 0;
+		obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
-		obj->pending_fenced_gpu_access = false;
+		obj->base.pending_write_domain = 0;
 		/* Unbind any ill-fitting objects or pin. */
 		list_for_each_entry(vma, vmas, exec_list) {
 			if (!drm_mm_node_allocated(&vma->node))
 				continue;
-			if (eb_vma_misplaced(vma, has_fenced_gpu_access))
+			if (eb_vma_misplaced(vma))
 				ret = i915_vma_unbind(vma);
 			else
 				ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
 			if (ret)
 	bool need_relocs;
 	int *reloc_offset;
 	int i, total, ret;
 	unsigned count = args->buffer_count;
-	if (WARN_ON(list_empty(&eb->vmas)))
-		return 0;
 	vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
 	/* We may process another execbuffer during the unlock... */
 	return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
+}
+static int
-static int
+validate_exec_list(struct drm_device *dev,
-validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
+		   struct drm_i915_gem_exec_object2 *exec,
-		   int count)
 		   int count)
 	int i;
+	unsigned relocs_total = 0;
+	unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
+	unsigned invalid_flags;
+	int i;
+	invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
-	unsigned relocs_total = 0;
+	if (USES_FULL_PPGTT(dev))
-	unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
+		invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
 	for (i = 0; i < count; i++) {
 		char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
 		int length; /* limited by fault_in_pages_readable() */
-		if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS)
+		if (exec[i].flags & invalid_flags)
 	if (hs->banned) {
 		DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
 		return ERR_PTR(-EIO);
+	}
+	if (i915.enable_execlists && !ctx->engine[ring->id].state) {
+		int ret = intel_lr_context_deferred_create(ctx, ring);
+		if (ret) {
+			DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret);
+			return ERR_PTR(ret);
+		}
+	}
 	return ctx;
 }
-static void
+void
 i915_gem_execbuffer_move_to_active(struct list_head *vmas,
+				   struct intel_engine_cs *ring)
 				   struct intel_engine_cs *ring)
 	u32 seqno = intel_ring_get_seqno(ring);
+	struct i915_vma *vma;
 	struct i915_vma *vma;
 	list_for_each_entry(vma, vmas, exec_list) {
-	list_for_each_entry(vma, vmas, exec_list) {
+		struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 		struct drm_i915_gem_object *obj = vma->obj;
 		u32 old_read = obj->base.read_domains;
 		u32 old_write = obj->base.write_domain;
-		obj->base.write_domain = obj->base.pending_write_domain;
-		if (obj->base.write_domain == 0)
+		obj->base.write_domain = obj->base.pending_write_domain;
-			obj->base.pending_read_domains |= obj->base.read_domains;
+		if (obj->base.write_domain == 0)
-		obj->base.read_domains = obj->base.pending_read_domains;
+			obj->base.pending_read_domains |= obj->base.read_domains;
-		obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
+		obj->base.read_domains = obj->base.pending_read_domains;
 		i915_vma_move_to_active(vma, ring);
 		if (obj->base.write_domain) {
 			obj->dirty = 1;
+			obj->last_write_seqno = seqno;
+			intel_fb_obj_invalidate(obj, ring);
+			/* update for the implicit flush after a batch */
+			obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
+		}
+		if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
-			obj->last_write_seqno = intel_ring_get_seqno(ring);
+			obj->last_fenced_seqno = seqno;
 			if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
-			intel_fb_obj_invalidate(obj, ring);
+				struct drm_i915_private *dev_priv = to_i915(ring->dev);
+				list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
-			/* update for the implicit flush after a batch */
+					       &dev_priv->mm.fence_list);
 			obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
+		}
 		trace_i915_gem_object_change_domain(obj, old_read, old_write);
 	return 0;
+}
+static int
+i915_emit_box(struct intel_engine_cs *ring,
+	      struct drm_clip_rect *box,
+	      int DR1, int DR4)
+{
+	int ret;
+	if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
+	    box->y2 <= 0 || box->x2 <= 0) {
+		DRM_ERROR("Bad box %d,%d..%d,%d\n",
+			  box->x1, box->y1, box->x2, box->y2);
+		return -EINVAL;
+	}
+	if (INTEL_INFO(ring->dev)->gen >= 4) {
+		ret = intel_ring_begin(ring, 4);
+		if (ret)
+			return ret;
+		intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO_I965);
+		intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16);
+		intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16);
+		intel_ring_emit(ring, DR4);
+	} else {
+		ret = intel_ring_begin(ring, 6);
+		if (ret)
+			return ret;
+		intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO);
+		intel_ring_emit(ring, DR1);
+		intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16);
+		intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16);
+		intel_ring_emit(ring, DR4);
+		intel_ring_emit(ring, 0);
+	}
+	intel_ring_advance(ring);
+	return 0;
+}
-static int
+int
-legacy_ringbuffer_submission(struct drm_device *dev, struct drm_file *file,
+i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file,
 			     struct intel_engine_cs *ring,
 			     struct intel_context *ctx,
 			     struct drm_i915_gem_execbuffer2 *args,
+	}
 	exec_len = args->batch_len;
 	if (cliprects) {
 		for (i = 0; i < args->num_cliprects; i++) {
-			ret = i915_emit_box(dev, &cliprects[i],
+			ret = i915_emit_box(ring, &cliprects[i],
 					    args->DR1, args->DR4);
 			if (ret)
 				goto error;
 	bool need_relocs;
 	if (!i915_gem_check_execbuffer(args))
 		return -EINVAL;
-	ret = validate_exec_list(exec, args->buffer_count);
+	ret = validate_exec_list(dev, exec, args->buffer_count);
 	if (ret)
 		return ret;
 	ret = i915_mutex_lock_interruptible(dev);
 	if (ret)
-		goto pre_mutex_err;
-	if (dev_priv->ums.mm_suspended) {
-		mutex_unlock(&dev->struct_mutex);
-		ret = -EBUSY;
-		goto pre_mutex_err;
 		goto pre_mutex_err;
 	ctx = i915_gem_validate_context(dev, file, ring, ctx_id);
 	if (IS_ERR(ctx)) {
 		mutex_unlock(&dev->struct_mutex);
 		ret = PTR_ERR(ctx);
 		goto pre_mutex_err;
 	}
+	i915_gem_context_reference(ctx);
 	i915_gem_context_reference(ctx);
 	if (ctx->ppgtt)
-	vm = ctx->vm;
+		vm = &ctx->ppgtt->base;
-	if (!USES_FULL_PPGTT(dev))
+	else
+	}
 #endif
 	/* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
 	 * batch" bit. Hence we need to pin secure batches into the global gtt.
 	 * hsw should have this fixed, but bdw mucks it up again. */
-	if (flags & I915_DISPATCH_SECURE &&
+	if (flags & I915_DISPATCH_SECURE) {
+		/*
+		 * So on first glance it looks freaky that we pin the batch here
-	    !batch_obj->has_global_gtt_mapping) {
+		 * outside of the reservation loop. But:
-		/* When we have multiple VMs, we'll need to make sure that we
+		 * - The batch is already pinned into the relevant ppgtt, so we
-		 * allocate space first */
+		 *   already have the backing storage fully allocated.
-		struct i915_vma *vma = i915_gem_obj_to_ggtt(batch_obj);
+		 * - No other BO uses the global gtt (well contexts, but meh),
+		 *   so we don't really have issues with mutliple objects not
-		BUG_ON(!vma);
+		 *   fitting due to fragmentation.
-		vma->bind_vma(vma, batch_obj->cache_level, GLOBAL_BIND);
+		 * So this is actually safe.
-	}
+		 */
+		ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0);
+		if (ret)
+			goto err;
 	if (flags & I915_DISPATCH_SECURE)
 		exec_start += i915_gem_obj_ggtt_offset(batch_obj);
-	else
+	} else
 		exec_start += i915_gem_obj_offset(batch_obj, vm);
-	ret = legacy_ringbuffer_submission(dev, file, ring, ctx,
-			args, &eb->vmas, batch_obj, exec_start, flags);
+	ret = dev_priv->gt.do_execbuf(dev, file, ring, ctx, args,
+				      &eb->vmas, batch_obj, exec_start, flags);
+	/*
+	 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
+	 * batch vma for correctness. For less ugly and less fragility this
+	 * needs to be adjusted to also track the ggtt batch vma properly as
+	 * active.
-   	if (ret)
+	 */
-		goto err;
+	if (flags & I915_DISPATCH_SECURE)
 		i915_gem_object_ggtt_unpin(batch_obj);
 err:

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_gem_execbuffer.c – Rev 5060 → 5354