WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_gem_context.c


/*
 * Copyright © 2011-2012 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Ben Widawsky 
 *
 */
 
/*
 * This file implements HW context support. On gen5+ a HW context consists of an
 * opaque GPU object which is referenced at times of context saves and restores.
 * With RC6 enabled, the context is also referenced as the GPU enters and exists
 * from RC6 (GPU has it's own internal power context, except on gen5). Though
 * something like a context does exist for the media ring, the code only
 * supports contexts for the render ring.
 *
 * In software, there is a distinction between contexts created by the user,
 * and the default HW context. The default HW context is used by GPU clients
 * that do not request setup of their own hardware context. The default
 * context's state is never restored to help prevent programming errors. This
 * would happen if a client ran and piggy-backed off another clients GPU state.
 * The default context only exists to give the GPU some offset to load as the
 * current to invoke a save of the context we actually care about. In fact, the
 * code could likely be constructed, albeit in a more complicated fashion, to
 * never use the default context, though that limits the driver's ability to
 * swap out, and/or destroy other contexts.
 *
 * All other contexts are created as a request by the GPU client. These contexts
 * store GPU state, and thus allow GPU clients to not re-emit state (and
 * potentially query certain state) at any time. The kernel driver makes
 * certain that the appropriate commands are inserted.
 *
 * The context life cycle is semi-complicated in that context BOs may live
 * longer than the context itself because of the way the hardware, and object
 * tracking works. Below is a very crude representation of the state machine
 * describing the context life.
 *                                         refcount     pincount     active
 * S0: initial state                          0            0           0
 * S1: context created                        1            0           0
 * S2: context is currently running           2            1           X
 * S3: GPU referenced, but not current        2            0           1
 * S4: context is current, but destroyed      1            1           0
 * S5: like S3, but destroyed                 1            0           1
 *
 * The most common (but not all) transitions:
 * S0->S1: client creates a context
 * S1->S2: client submits execbuf with context
 * S2->S3: other clients submits execbuf with context
 * S3->S1: context object was retired
 * S3->S2: clients submits another execbuf
 * S2->S4: context destroy called with current context
 * S3->S5->S0: destroy path
 * S4->S5->S0: destroy path on current context
 *
 * There are two confusing terms used above:
 *  The "current context" means the context which is currently running on the
 *  GPU. The GPU has loaded its state already and has stored away the gtt
 *  offset of the BO. The GPU is not actively referencing the data at this
 *  offset, but it will on the next context switch. The only way to avoid this
 *  is to do a GPU reset.
 *
 *  An "active context' is one which was previously the "current context" and is
 *  on the active list waiting for the next context switch to occur. Until this
 *  happens, the object must remain at the same gtt offset. It is therefore
 *  possible to destroy a context, but it is still active.
 *
 */
 
#include 
#include 
#include "i915_drv.h"
#include "i915_trace.h"
 
/* This is a HW constraint. The value below is the largest known requirement
 * I've seen in a spec to date, and that was a workaround for a non-shipping
 * part. It should be safe to decrease this, but it's more future proof as is.
 */
#define GEN6_CONTEXT_ALIGN (64<<10)
#define GEN7_CONTEXT_ALIGN 4096
 
static size_t get_context_alignment(struct drm_device *dev)
{
	if (IS_GEN6(dev))
		return GEN6_CONTEXT_ALIGN;
 
	return GEN7_CONTEXT_ALIGN;
}
 
static int get_context_size(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;
	u32 reg;
 
	switch (INTEL_INFO(dev)->gen) {
	case 6:
		reg = I915_READ(CXT_SIZE);
		ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
		break;
	case 7:
		reg = I915_READ(GEN7_CXT_SIZE);
		if (IS_HASWELL(dev))
			ret = HSW_CXT_TOTAL_SIZE;
		else
			ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
		break;
	case 8:
		ret = GEN8_CXT_TOTAL_SIZE;
		break;
	default:
		BUG();
	}
 
	return ret;
}
 
static void i915_gem_context_clean(struct intel_context *ctx)
{
	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
	struct i915_vma *vma, *next;
 
	if (!ppgtt)
		return;
 
	list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list,
				 vm_link) {
		if (WARN_ON(__i915_vma_unbind_no_wait(vma)))
			break;
	}
}
 
void i915_gem_context_free(struct kref *ctx_ref)
{
	struct intel_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
 
	trace_i915_context_free(ctx);
 
	if (i915.enable_execlists)
		intel_lr_context_free(ctx);
 
	/*
	 * This context is going away and we need to remove all VMAs still
	 * around. This is to handle imported shared objects for which
	 * destructor did not run when their handles were closed.
	 */
	i915_gem_context_clean(ctx);
 
	i915_ppgtt_put(ctx->ppgtt);
 
	if (ctx->legacy_hw_ctx.rcs_state)
		drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base);
	list_del(&ctx->link);
	kfree(ctx);
}
 
struct drm_i915_gem_object *
i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
{
	struct drm_i915_gem_object *obj;
	int ret;
 
	obj = i915_gem_alloc_object(dev, size);
	if (obj == NULL)
		return ERR_PTR(-ENOMEM);
 
	/*
	 * Try to make the context utilize L3 as well as LLC.
	 *
	 * On VLV we don't have L3 controls in the PTEs so we
	 * shouldn't touch the cache level, especially as that
	 * would make the object snooped which might have a
	 * negative performance impact.
	 *
	 * Snooping is required on non-llc platforms in execlist
	 * mode, but since all GGTT accesses use PAT entry 0 we
	 * get snooping anyway regardless of cache_level.
	 *
	 * This is only applicable for Ivy Bridge devices since
	 * later platforms don't have L3 control bits in the PTE.
	 */
	if (IS_IVYBRIDGE(dev)) {
		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
		/* Failure shouldn't ever happen this early */
		if (WARN_ON(ret)) {
			drm_gem_object_unreference(&obj->base);
			return ERR_PTR(ret);
		}
	}
 
	return obj;
}
 
static struct intel_context *
__create_hw_context(struct drm_device *dev,
		    struct drm_i915_file_private *file_priv)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_context *ctx;
	int ret;
 
	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
	if (ctx == NULL)
		return ERR_PTR(-ENOMEM);
 
	kref_init(&ctx->ref);
	list_add_tail(&ctx->link, &dev_priv->context_list);
	ctx->i915 = dev_priv;
 
	if (dev_priv->hw_context_size) {
		struct drm_i915_gem_object *obj =
				i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size);
		if (IS_ERR(obj)) {
			ret = PTR_ERR(obj);
			goto err_out;
		}
		ctx->legacy_hw_ctx.rcs_state = obj;
	}
 
	/* Default context will never have a file_priv */
	if (file_priv != NULL) {
		ret = idr_alloc(&file_priv->context_idr, ctx,
				DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
		if (ret < 0)
			goto err_out;
	} else
		ret = DEFAULT_CONTEXT_HANDLE;
 
	ctx->file_priv = file_priv;
	ctx->user_handle = ret;
	/* NB: Mark all slices as needing a remap so that when the context first
	 * loads it will restore whatever remap state already exists. If there
	 * is no remap info, it will be a NOP. */
	ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1;
 
	ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;
 
	return ctx;
 
err_out:
	i915_gem_context_unreference(ctx);
	return ERR_PTR(ret);
}
 
/**
 * The default context needs to exist per ring that uses contexts. It stores the
 * context state of the GPU for applications that don't utilize HW contexts, as
 * well as an idle case.
 */
static struct intel_context *
i915_gem_create_context(struct drm_device *dev,
			struct drm_i915_file_private *file_priv)
{
	const bool is_global_default_ctx = file_priv == NULL;
	struct intel_context *ctx;
	int ret = 0;
 
	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
 
	ctx = __create_hw_context(dev, file_priv);
	if (IS_ERR(ctx))
		return ctx;
 
	if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) {
		/* We may need to do things with the shrinker which
		 * require us to immediately switch back to the default
		 * context. This can cause a problem as pinning the
		 * default context also requires GTT space which may not
		 * be available. To avoid this we always pin the default
		 * context.
		 */
		ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state,
					    get_context_alignment(dev), 0);
		if (ret) {
			DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
			goto err_destroy;
		}
	}
 
	if (USES_FULL_PPGTT(dev)) {
		struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv);
 
		if (IS_ERR_OR_NULL(ppgtt)) {
			DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
					 PTR_ERR(ppgtt));
			ret = PTR_ERR(ppgtt);
			goto err_unpin;
		}
 
		ctx->ppgtt = ppgtt;
	}
 
	trace_i915_context_create(ctx);
 
	return ctx;
 
err_unpin:
	if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state)
		i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state);
err_destroy:
	idr_remove(&file_priv->context_idr, ctx->user_handle);
	i915_gem_context_unreference(ctx);
	return ERR_PTR(ret);
}
 
static void i915_gem_context_unpin(struct intel_context *ctx,
				   struct intel_engine_cs *engine)
{
	if (i915.enable_execlists) {
		intel_lr_context_unpin(ctx, engine);
	} else {
		if (engine->id == RCS && ctx->legacy_hw_ctx.rcs_state)
			i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state);
		i915_gem_context_unreference(ctx);
	}
}
 
void i915_gem_context_reset(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;
 
	if (i915.enable_execlists) {
		struct intel_context *ctx;
 
		list_for_each_entry(ctx, &dev_priv->context_list, link)
			intel_lr_context_reset(dev, ctx);
	}
 
 
 
 
	for (i = 0; i < I915_NUM_RINGS; i++) {
 
 
 
 
 
		struct intel_engine_cs *ring = &dev_priv->ring[i];
 
		if (ring->last_context) {
			i915_gem_context_unpin(ring->last_context, ring);
			ring->last_context = NULL;
		}
 
	}
 
 
	/* Force the GPU state to be reinitialised on enabling */
	dev_priv->kernel_context->legacy_hw_ctx.initialized = false;
}
 
int i915_gem_context_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_context *ctx;
 
 
	/* Init should only be called once per module load. Eventually the
	 * restriction on the context_disabled check can be loosened. */
	if (WARN_ON(dev_priv->kernel_context))
		return 0;
 
	if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) {
		if (!i915.enable_execlists) {
			DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
			return -EINVAL;
		}
	}
 
	if (i915.enable_execlists) {
		/* NB: intentionally left blank. We will allocate our own
		 * backing objects as we need them, thank you very much */
		dev_priv->hw_context_size = 0;
	} else if (HAS_HW_CONTEXTS(dev)) {
		dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
		if (dev_priv->hw_context_size > (1<<20)) {
			DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
					 dev_priv->hw_context_size);
			dev_priv->hw_context_size = 0;
		}
	}
 
	ctx = i915_gem_create_context(dev, NULL);
	if (IS_ERR(ctx)) {
		DRM_ERROR("Failed to create default global context (error %ld)\n",
			  PTR_ERR(ctx));
		return PTR_ERR(ctx);
	}
 
 
 
 
 
 
	dev_priv->kernel_context = ctx;
 
	DRM_DEBUG_DRIVER("%s context support initialized\n",
			i915.enable_execlists ? "LR" :
			dev_priv->hw_context_size ? "HW" : "fake");
	return 0;
}
 
void i915_gem_context_fini(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_context *dctx = dev_priv->kernel_context;
	int i;
 
	if (dctx->legacy_hw_ctx.rcs_state) {
		/* The only known way to stop the gpu from accessing the hw context is
		 * to reset it. Do this as the very last operation to avoid confusing
		 * other code, leading to spurious errors. */
		intel_gpu_reset(dev);
 
		/* When default context is created and switched to, base object refcount
		 * will be 2 (+1 from object creation and +1 from do_switch()).
		 * i915_gem_context_fini() will be called after gpu_idle() has switched
		 * to default context. So we need to unreference the base object once
		 * to offset the do_switch part, so that i915_gem_context_unreference()
		 * can then free the base object correctly. */
		WARN_ON(!dev_priv->ring[RCS].last_context);
 
 
 
 
 
 
 
 
		i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state);
	}
 
	for (i = I915_NUM_RINGS; --i >= 0;) {
		struct intel_engine_cs *ring = &dev_priv->ring[i];
 
 
 
		if (ring->last_context) {
			i915_gem_context_unpin(ring->last_context, ring);
			ring->last_context = NULL;
		}
	}
 
	i915_gem_context_unreference(dctx);
	dev_priv->kernel_context = NULL;
}
 
int i915_gem_context_enable(struct drm_i915_gem_request *req)
{
	struct intel_engine_cs *ring = req->ring;
	int ret;
 
	if (i915.enable_execlists) {
		if (ring->init_context == NULL)
			return 0;
 
		ret = ring->init_context(req);
	} else
		ret = i915_switch_context(req);
 
	if (ret) {
		DRM_ERROR("ring init context: %d\n", ret);
		return ret;
	}
 
	return 0;
}
 
static int context_idr_cleanup(int id, void *p, void *data)
{
	struct intel_context *ctx = p;
 
	i915_gem_context_unreference(ctx);
	return 0;
}
 
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
{
	struct drm_i915_file_private *file_priv = file->driver_priv;
	struct intel_context *ctx;
 
	idr_init(&file_priv->context_idr);
 
	mutex_lock(&dev->struct_mutex);
	ctx = i915_gem_create_context(dev, file_priv);
	mutex_unlock(&dev->struct_mutex);
 
	if (IS_ERR(ctx)) {
		idr_destroy(&file_priv->context_idr);
		return PTR_ERR(ctx);
	}
 
	return 0;
}
 
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
{
	struct drm_i915_file_private *file_priv = file->driver_priv;
 
	idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
	idr_destroy(&file_priv->context_idr);
}
 
struct intel_context *
i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
{
	struct intel_context *ctx;
 
	ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id);
	if (!ctx)
		return ERR_PTR(-ENOENT);
 
	return ctx;
}
 
static inline int
mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
{
	struct intel_engine_cs *ring = req->ring;
	u32 flags = hw_flags | MI_MM_SPACE_GTT;
	const int num_rings =
		/* Use an extended w/a on ivb+ if signalling from other rings */
		i915_semaphore_is_enabled(ring->dev) ?
		hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 :
		0;
	int len, i, ret;
 
	/* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
	 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
	 * explicitly, so we rely on the value at ring init, stored in
	 * itlb_before_ctx_switch.
	 */
	if (IS_GEN6(ring->dev)) {
		ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0);
		if (ret)
			return ret;
	}
 
	/* These flags are for resource streamer on HSW+ */
	if (IS_HASWELL(ring->dev) || INTEL_INFO(ring->dev)->gen >= 8)
		flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
	else if (INTEL_INFO(ring->dev)->gen < 8)
		flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
 
 
	len = 4;
	if (INTEL_INFO(ring->dev)->gen >= 7)
		len += 2 + (num_rings ? 4*num_rings + 2 : 0);
 
	ret = intel_ring_begin(req, len);
	if (ret)
		return ret;
 
	/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
	if (INTEL_INFO(ring->dev)->gen >= 7) {
		intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
		if (num_rings) {
			struct intel_engine_cs *signaller;
 
			intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
			for_each_ring(signaller, to_i915(ring->dev), i) {
				if (signaller == ring)
					continue;
 
				intel_ring_emit_reg(ring, RING_PSMI_CTL(signaller->mmio_base));
				intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
			}
		}
	}
 
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_emit(ring, MI_SET_CONTEXT);
	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(req->ctx->legacy_hw_ctx.rcs_state) |
			flags);
	/*
	 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
	 * WaMiSetContext_Hang:snb,ivb,vlv
	 */
	intel_ring_emit(ring, MI_NOOP);
 
	if (INTEL_INFO(ring->dev)->gen >= 7) {
		if (num_rings) {
			struct intel_engine_cs *signaller;
 
			intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
			for_each_ring(signaller, to_i915(ring->dev), i) {
				if (signaller == ring)
					continue;
 
				intel_ring_emit_reg(ring, RING_PSMI_CTL(signaller->mmio_base));
				intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
			}
		}
		intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
	}
 
	intel_ring_advance(ring);
 
	return ret;
}
 
static inline bool should_skip_switch(struct intel_engine_cs *ring,
				      struct intel_context *from,
				      struct intel_context *to)
{
	if (to->remap_slice)
		return false;
 
	if (to->ppgtt && from == to &&
	    !(intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings))
		return true;
 
	return false;
}
 
static bool
needs_pd_load_pre(struct intel_engine_cs *ring, struct intel_context *to)
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
 
	if (!to->ppgtt)
		return false;
 
	if (INTEL_INFO(ring->dev)->gen < 8)
		return true;
 
	if (ring != &dev_priv->ring[RCS])
		return true;
 
	return false;
}
 
static bool
needs_pd_load_post(struct intel_engine_cs *ring, struct intel_context *to,
		u32 hw_flags)
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
 
	if (!to->ppgtt)
		return false;
 
	if (!IS_GEN8(ring->dev))
		return false;
 
	if (ring != &dev_priv->ring[RCS])
		return false;
 
	if (hw_flags & MI_RESTORE_INHIBIT)
		return true;
 
	return false;
}
 
static int do_switch(struct drm_i915_gem_request *req)
{
	struct intel_context *to = req->ctx;
	struct intel_engine_cs *ring = req->ring;
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
	struct intel_context *from = ring->last_context;
	u32 hw_flags = 0;
	bool uninitialized = false;
	int ret, i;
 
	if (from != NULL && ring == &dev_priv->ring[RCS]) {
		BUG_ON(from->legacy_hw_ctx.rcs_state == NULL);
		BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state));
	}
 
	if (should_skip_switch(ring, from, to))
		return 0;
 
	/* Trying to pin first makes error handling easier. */
	if (ring == &dev_priv->ring[RCS]) {
		ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state,
					    get_context_alignment(ring->dev), 0);
		if (ret)
			return ret;
	}
 
	/*
	 * Pin can switch back to the default context if we end up calling into
	 * evict_everything - as a last ditch gtt defrag effort that also
	 * switches to the default context. Hence we need to reload from here.
	 */
	from = ring->last_context;
 
	if (needs_pd_load_pre(ring, to)) {
		/* Older GENs and non render rings still want the load first,
		 * "PP_DCLV followed by PP_DIR_BASE register through Load
		 * Register Immediate commands in Ring Buffer before submitting
		 * a context."*/
		trace_switch_mm(ring, to);
		ret = to->ppgtt->switch_mm(to->ppgtt, req);
		if (ret)
			goto unpin_out;
 
		/* Doing a PD load always reloads the page dirs */
		to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring);
	}
 
	if (ring != &dev_priv->ring[RCS]) {
		if (from)
			i915_gem_context_unreference(from);
		goto done;
	}
 
	/*
	 * Clear this page out of any CPU caches for coherent swap-in/out. Note
	 * that thanks to write = false in this call and us not setting any gpu
	 * write domains when putting a context object onto the active list
	 * (when switching away from it), this won't block.
	 *
	 * XXX: We need a real interface to do this instead of trickery.
	 */
	ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false);
	if (ret)
		goto unpin_out;
 
	if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to)) {
		hw_flags |= MI_RESTORE_INHIBIT;
		/* NB: If we inhibit the restore, the context is not allowed to
		 * die because future work may end up depending on valid address
		 * space. This means we must enforce that a page table load
		 * occur when this occurs. */
	} else if (to->ppgtt &&
		   (intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) {
		hw_flags |= MI_FORCE_RESTORE;
		to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring);
	}
 
	/* We should never emit switch_mm more than once */
	WARN_ON(needs_pd_load_pre(ring, to) &&
		needs_pd_load_post(ring, to, hw_flags));
 
	ret = mi_set_context(req, hw_flags);
	if (ret)
		goto unpin_out;
 
	/* GEN8 does *not* require an explicit reload if the PDPs have been
	 * setup, and we do not wish to move them.
	 */
	if (needs_pd_load_post(ring, to, hw_flags)) {
		trace_switch_mm(ring, to);
		ret = to->ppgtt->switch_mm(to->ppgtt, req);
		/* The hardware context switch is emitted, but we haven't
		 * actually changed the state - so it's probably safe to bail
		 * here. Still, let the user know something dangerous has
		 * happened.
		 */
		if (ret) {
			DRM_ERROR("Failed to change address space on context switch\n");
			goto unpin_out;
		}
	}
 
	for (i = 0; i < MAX_L3_SLICES; i++) {
		if (!(to->remap_slice & (1<
			continue;
 
		ret = i915_gem_l3_remap(req, i);
		/* If it failed, try again next round */
		if (ret)
			DRM_DEBUG_DRIVER("L3 remapping failed\n");
		else
			to->remap_slice &= ~(1<
	}
 
	/* The backing object for the context is done after switching to the
	 * *next* context. Therefore we cannot retire the previous context until
	 * the next context has already started running. In fact, the below code
	 * is a bit suboptimal because the retiring can occur simply after the
	 * MI_SET_CONTEXT instead of when the next seqno has completed.
	 */
	if (from != NULL) {
		from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
		i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), req);
		/* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
		 * whole damn pipeline, we don't need to explicitly mark the
		 * object dirty. The only exception is that the context must be
		 * correct in case the object gets swapped out. Ideally we'd be
		 * able to defer doing this until we know the object would be
		 * swapped, but there is no way to do that yet.
		 */
		from->legacy_hw_ctx.rcs_state->dirty = 1;
 
		/* obj is kept alive until the next request by its active ref */
		i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state);
		i915_gem_context_unreference(from);
	}
 
	uninitialized = !to->legacy_hw_ctx.initialized;
	to->legacy_hw_ctx.initialized = true;
 
done:
	i915_gem_context_reference(to);
	ring->last_context = to;
 
	if (uninitialized) {
		if (ring->init_context) {
			ret = ring->init_context(req);
			if (ret)
				DRM_ERROR("ring init context: %d\n", ret);
		}
	}
 
	return 0;
 
unpin_out:
	if (ring->id == RCS)
		i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state);
	return ret;
}
 
/**
 * i915_switch_context() - perform a GPU context switch.
 * @req: request for which we'll execute the context switch
 *
 * The context life cycle is simple. The context refcount is incremented and
 * decremented by 1 and create and destroy. If the context is in use by the GPU,
 * it will have a refcount > 1. This allows us to destroy the context abstract
 * object while letting the normal object tracking destroy the backing BO.
 *
 * This function should not be used in execlists mode.  Instead the context is
 * switched by writing to the ELSP and requests keep a reference to their
 * context.
 */
int i915_switch_context(struct drm_i915_gem_request *req)
{
	struct intel_engine_cs *ring = req->ring;
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
 
	WARN_ON(i915.enable_execlists);
	WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
 
	if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */
		if (req->ctx != ring->last_context) {
			i915_gem_context_reference(req->ctx);
			if (ring->last_context)
				i915_gem_context_unreference(ring->last_context);
			ring->last_context = req->ctx;
		}
		return 0;
	}
 
	return do_switch(req);
}
 
static bool contexts_enabled(struct drm_device *dev)
{
	return i915.enable_execlists || to_i915(dev)->hw_context_size;
}
 
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file)
{
	struct drm_i915_gem_context_create *args = data;
	struct drm_i915_file_private *file_priv = file->driver_priv;
	struct intel_context *ctx;
	int ret;
 
	if (!contexts_enabled(dev))
		return -ENODEV;
 
	if (args->pad != 0)
		return -EINVAL;
 
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
 
	ctx = i915_gem_create_context(dev, file_priv);
	mutex_unlock(&dev->struct_mutex);
	if (IS_ERR(ctx))
		return PTR_ERR(ctx);
 
	args->ctx_id = ctx->user_handle;
	DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
 
	return 0;
}
 
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
				   struct drm_file *file)
{
	struct drm_i915_gem_context_destroy *args = data;
	struct drm_i915_file_private *file_priv = file->driver_priv;
	struct intel_context *ctx;
	int ret;
 
	if (args->pad != 0)
		return -EINVAL;
 
	if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
		return -ENOENT;
 
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
 
	ctx = i915_gem_context_get(file_priv, args->ctx_id);
	if (IS_ERR(ctx)) {
		mutex_unlock(&dev->struct_mutex);
		return PTR_ERR(ctx);
	}
 
	idr_remove(&ctx->file_priv->context_idr, ctx->user_handle);
	i915_gem_context_unreference(ctx);
	mutex_unlock(&dev->struct_mutex);
 
	DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
	return 0;
}
 
int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file)
{
	struct drm_i915_file_private *file_priv = file->driver_priv;
	struct drm_i915_gem_context_param *args = data;
	struct intel_context *ctx;
	int ret;
 
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
 
	ctx = i915_gem_context_get(file_priv, args->ctx_id);
	if (IS_ERR(ctx)) {
		mutex_unlock(&dev->struct_mutex);
		return PTR_ERR(ctx);
	}
 
	args->size = 0;
	switch (args->param) {
	case I915_CONTEXT_PARAM_BAN_PERIOD:
		args->value = ctx->hang_stats.ban_period_seconds;
		break;
	case I915_CONTEXT_PARAM_NO_ZEROMAP:
		args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
		break;
	case I915_CONTEXT_PARAM_GTT_SIZE:
		if (ctx->ppgtt)
			args->value = ctx->ppgtt->base.total;
		else if (to_i915(dev)->mm.aliasing_ppgtt)
			args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total;
		else
			args->value = to_i915(dev)->gtt.base.total;
		break;
	default:
		ret = -EINVAL;
		break;
	}
	mutex_unlock(&dev->struct_mutex);
 
	return ret;
}
 
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file)
{
	struct drm_i915_file_private *file_priv = file->driver_priv;
	struct drm_i915_gem_context_param *args = data;
	struct intel_context *ctx;
	int ret;
 
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
 
	ctx = i915_gem_context_get(file_priv, args->ctx_id);
	if (IS_ERR(ctx)) {
		mutex_unlock(&dev->struct_mutex);
		return PTR_ERR(ctx);
	}
 
	switch (args->param) {
	case I915_CONTEXT_PARAM_BAN_PERIOD:
		if (args->size)
			ret = -EINVAL;
		else if (args->value < ctx->hang_stats.ban_period_seconds &&
			 !capable(CAP_SYS_ADMIN))
			ret = -EPERM;
		else
			ctx->hang_stats.ban_period_seconds = args->value;
		break;
	case I915_CONTEXT_PARAM_NO_ZEROMAP:
		if (args->size) {
			ret = -EINVAL;
		} else {
			ctx->flags &= ~CONTEXT_NO_ZEROMAP;
			ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
		}
		break;
	default:
		ret = -EINVAL;
		break;
	}
	mutex_unlock(&dev->struct_mutex);
 
	return ret;
}
>
>
>
>
#define>
#define>

Rev 6937	Rev 7144
1	/*	1	/*
2	* Copyright © 2011-2012 Intel Corporation	2	* Copyright © 2011-2012 Intel Corporation
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice (including the next	11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the	12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.	13	* Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21	* IN THE SOFTWARE.	21	* IN THE SOFTWARE.
22	*	22	*
23	* Authors:	23	* Authors:
24	* Ben Widawsky	24	* Ben Widawsky
25	*	25	*
26	*/	26	*/
27		27
28	/*	28	/*
29	* This file implements HW context support. On gen5+ a HW context consists of an	29	* This file implements HW context support. On gen5+ a HW context consists of an
30	* opaque GPU object which is referenced at times of context saves and restores.	30	* opaque GPU object which is referenced at times of context saves and restores.
31	* With RC6 enabled, the context is also referenced as the GPU enters and exists	31	* With RC6 enabled, the context is also referenced as the GPU enters and exists
32	* from RC6 (GPU has it's own internal power context, except on gen5). Though	32	* from RC6 (GPU has it's own internal power context, except on gen5). Though
33	* something like a context does exist for the media ring, the code only	33	* something like a context does exist for the media ring, the code only
34	* supports contexts for the render ring.	34	* supports contexts for the render ring.
35	*	35	*
36	* In software, there is a distinction between contexts created by the user,	36	* In software, there is a distinction between contexts created by the user,
37	* and the default HW context. The default HW context is used by GPU clients	37	* and the default HW context. The default HW context is used by GPU clients
38	* that do not request setup of their own hardware context. The default	38	* that do not request setup of their own hardware context. The default
39	* context's state is never restored to help prevent programming errors. This	39	* context's state is never restored to help prevent programming errors. This
40	* would happen if a client ran and piggy-backed off another clients GPU state.	40	* would happen if a client ran and piggy-backed off another clients GPU state.
41	* The default context only exists to give the GPU some offset to load as the	41	* The default context only exists to give the GPU some offset to load as the
42	* current to invoke a save of the context we actually care about. In fact, the	42	* current to invoke a save of the context we actually care about. In fact, the
43	* code could likely be constructed, albeit in a more complicated fashion, to	43	* code could likely be constructed, albeit in a more complicated fashion, to
44	* never use the default context, though that limits the driver's ability to	44	* never use the default context, though that limits the driver's ability to
45	* swap out, and/or destroy other contexts.	45	* swap out, and/or destroy other contexts.
46	*	46	*
47	* All other contexts are created as a request by the GPU client. These contexts	47	* All other contexts are created as a request by the GPU client. These contexts
48	* store GPU state, and thus allow GPU clients to not re-emit state (and	48	* store GPU state, and thus allow GPU clients to not re-emit state (and
49	* potentially query certain state) at any time. The kernel driver makes	49	* potentially query certain state) at any time. The kernel driver makes
50	* certain that the appropriate commands are inserted.	50	* certain that the appropriate commands are inserted.
51	*	51	*
52	* The context life cycle is semi-complicated in that context BOs may live	52	* The context life cycle is semi-complicated in that context BOs may live
53	* longer than the context itself because of the way the hardware, and object	53	* longer than the context itself because of the way the hardware, and object
54	* tracking works. Below is a very crude representation of the state machine	54	* tracking works. Below is a very crude representation of the state machine
55	* describing the context life.	55	* describing the context life.
56	* refcount pincount active	56	* refcount pincount active
57	* S0: initial state 0 0 0	57	* S0: initial state 0 0 0
58	* S1: context created 1 0 0	58	* S1: context created 1 0 0
59	* S2: context is currently running 2 1 X	59	* S2: context is currently running 2 1 X
60	* S3: GPU referenced, but not current 2 0 1	60	* S3: GPU referenced, but not current 2 0 1
61	* S4: context is current, but destroyed 1 1 0	61	* S4: context is current, but destroyed 1 1 0
62	* S5: like S3, but destroyed 1 0 1	62	* S5: like S3, but destroyed 1 0 1
63	*	63	*
64	* The most common (but not all) transitions:	64	* The most common (but not all) transitions:
65	* S0->S1: client creates a context	65	* S0->S1: client creates a context
66	* S1->S2: client submits execbuf with context	66	* S1->S2: client submits execbuf with context
67	* S2->S3: other clients submits execbuf with context	67	* S2->S3: other clients submits execbuf with context
68	* S3->S1: context object was retired	68	* S3->S1: context object was retired
69	* S3->S2: clients submits another execbuf	69	* S3->S2: clients submits another execbuf
70	* S2->S4: context destroy called with current context	70	* S2->S4: context destroy called with current context
71	* S3->S5->S0: destroy path	71	* S3->S5->S0: destroy path
72	* S4->S5->S0: destroy path on current context	72	* S4->S5->S0: destroy path on current context
73	*	73	*
74	* There are two confusing terms used above:	74	* There are two confusing terms used above:
75	* The "current context" means the context which is currently running on the	75	* The "current context" means the context which is currently running on the
76	* GPU. The GPU has loaded its state already and has stored away the gtt	76	* GPU. The GPU has loaded its state already and has stored away the gtt
77	* offset of the BO. The GPU is not actively referencing the data at this	77	* offset of the BO. The GPU is not actively referencing the data at this
78	* offset, but it will on the next context switch. The only way to avoid this	78	* offset, but it will on the next context switch. The only way to avoid this
79	* is to do a GPU reset.	79	* is to do a GPU reset.
80	*	80	*
81	* An "active context' is one which was previously the "current context" and is	81	* An "active context' is one which was previously the "current context" and is
82	* on the active list waiting for the next context switch to occur. Until this	82	* on the active list waiting for the next context switch to occur. Until this
83	* happens, the object must remain at the same gtt offset. It is therefore	83	* happens, the object must remain at the same gtt offset. It is therefore
84	* possible to destroy a context, but it is still active.	84	* possible to destroy a context, but it is still active.
85	*	85	*
86	*/	86	*/
87		87
88	#include	88	#include
89	#include	89	#include
90	#include "i915_drv.h"	90	#include "i915_drv.h"
91	#include "i915_trace.h"	91	#include "i915_trace.h"
92		92
93	/* This is a HW constraint. The value below is the largest known requirement	93	/* This is a HW constraint. The value below is the largest known requirement
94	* I've seen in a spec to date, and that was a workaround for a non-shipping	94	* I've seen in a spec to date, and that was a workaround for a non-shipping
95	* part. It should be safe to decrease this, but it's more future proof as is.	95	* part. It should be safe to decrease this, but it's more future proof as is.
96	*/	96	*/
97	#define GEN6_CONTEXT_ALIGN (64<<10)	97	#define GEN6_CONTEXT_ALIGN (64<<10)
98	#define GEN7_CONTEXT_ALIGN 4096	98	#define GEN7_CONTEXT_ALIGN 4096
99		99
100	static size_t get_context_alignment(struct drm_device *dev)	100	static size_t get_context_alignment(struct drm_device *dev)
101	{	101	{
102	if (IS_GEN6(dev))	102	if (IS_GEN6(dev))
103	return GEN6_CONTEXT_ALIGN;	103	return GEN6_CONTEXT_ALIGN;
104		104
105	return GEN7_CONTEXT_ALIGN;	105	return GEN7_CONTEXT_ALIGN;
106	}	106	}
107		107
108	static int get_context_size(struct drm_device *dev)	108	static int get_context_size(struct drm_device *dev)
109	{	109	{
110	struct drm_i915_private *dev_priv = dev->dev_private;	110	struct drm_i915_private *dev_priv = dev->dev_private;
111	int ret;	111	int ret;
112	u32 reg;	112	u32 reg;
113		113
114	switch (INTEL_INFO(dev)->gen) {	114	switch (INTEL_INFO(dev)->gen) {
115	case 6:	115	case 6:
116	reg = I915_READ(CXT_SIZE);	116	reg = I915_READ(CXT_SIZE);
117	ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;	117	ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
118	break;	118	break;
119	case 7:	119	case 7:
120	reg = I915_READ(GEN7_CXT_SIZE);	120	reg = I915_READ(GEN7_CXT_SIZE);
121	if (IS_HASWELL(dev))	121	if (IS_HASWELL(dev))
122	ret = HSW_CXT_TOTAL_SIZE;	122	ret = HSW_CXT_TOTAL_SIZE;
123	else	123	else
124	ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;	124	ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
125	break;	125	break;
126	case 8:	126	case 8:
127	ret = GEN8_CXT_TOTAL_SIZE;	127	ret = GEN8_CXT_TOTAL_SIZE;
128	break;	128	break;
129	default:	129	default:
130	BUG();	130	BUG();
131	}	131	}
132		132
133	return ret;	133	return ret;
134	}	134	}
135		135
136	static void i915_gem_context_clean(struct intel_context *ctx)	136	static void i915_gem_context_clean(struct intel_context *ctx)
137	{	137	{
138	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;	138	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
139	struct i915_vma vma, next;	139	struct i915_vma vma, next;
140		140
141	if (!ppgtt)	141	if (!ppgtt)
142	return;	142	return;
143		143
144	list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list,	144	list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list,
145	mm_list) {	145	vm_link) {
146	if (WARN_ON(__i915_vma_unbind_no_wait(vma)))	146	if (WARN_ON(__i915_vma_unbind_no_wait(vma)))
147	break;	147	break;
148	}	148	}
149	}	149	}
150		150
151	void i915_gem_context_free(struct kref *ctx_ref)	151	void i915_gem_context_free(struct kref *ctx_ref)
152	{	152	{
153	struct intel_context ctx = container_of(ctx_ref, typeof(ctx), ref);	153	struct intel_context ctx = container_of(ctx_ref, typeof(ctx), ref);
154		154
155	trace_i915_context_free(ctx);	155	trace_i915_context_free(ctx);
156		156
157	if (i915.enable_execlists)	157	if (i915.enable_execlists)
158	intel_lr_context_free(ctx);	158	intel_lr_context_free(ctx);
159		159
160	/*	160	/*
161	* This context is going away and we need to remove all VMAs still	161	* This context is going away and we need to remove all VMAs still
162	* around. This is to handle imported shared objects for which	162	* around. This is to handle imported shared objects for which
163	* destructor did not run when their handles were closed.	163	* destructor did not run when their handles were closed.
164	*/	164	*/
165	i915_gem_context_clean(ctx);	165	i915_gem_context_clean(ctx);
166		166
167	i915_ppgtt_put(ctx->ppgtt);	167	i915_ppgtt_put(ctx->ppgtt);
168		168
169	if (ctx->legacy_hw_ctx.rcs_state)	169	if (ctx->legacy_hw_ctx.rcs_state)
170	drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base);	170	drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base);
171	list_del(&ctx->link);	171	list_del(&ctx->link);
172	kfree(ctx);	172	kfree(ctx);
173	}	173	}
174		174
175	struct drm_i915_gem_object *	175	struct drm_i915_gem_object *
176	i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)	176	i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
177	{	177	{
178	struct drm_i915_gem_object *obj;	178	struct drm_i915_gem_object *obj;
179	int ret;	179	int ret;
180		180
181	obj = i915_gem_alloc_object(dev, size);	181	obj = i915_gem_alloc_object(dev, size);
182	if (obj == NULL)	182	if (obj == NULL)
183	return ERR_PTR(-ENOMEM);	183	return ERR_PTR(-ENOMEM);
184		184
185	/*	185	/*
186	* Try to make the context utilize L3 as well as LLC.	186	* Try to make the context utilize L3 as well as LLC.
187	*	187	*
188	* On VLV we don't have L3 controls in the PTEs so we	188	* On VLV we don't have L3 controls in the PTEs so we
189	* shouldn't touch the cache level, especially as that	189	* shouldn't touch the cache level, especially as that
190	* would make the object snooped which might have a	190	* would make the object snooped which might have a
191	* negative performance impact.	191	* negative performance impact.
192	*	192	*
193	* Snooping is required on non-llc platforms in execlist	193	* Snooping is required on non-llc platforms in execlist
194	* mode, but since all GGTT accesses use PAT entry 0 we	194	* mode, but since all GGTT accesses use PAT entry 0 we
195	* get snooping anyway regardless of cache_level.	195	* get snooping anyway regardless of cache_level.
196	*	196	*
197	* This is only applicable for Ivy Bridge devices since	197	* This is only applicable for Ivy Bridge devices since
198	* later platforms don't have L3 control bits in the PTE.	198	* later platforms don't have L3 control bits in the PTE.
199	*/	199	*/
200	if (IS_IVYBRIDGE(dev)) {	200	if (IS_IVYBRIDGE(dev)) {
201	ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);	201	ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
202	/* Failure shouldn't ever happen this early */	202	/* Failure shouldn't ever happen this early */
203	if (WARN_ON(ret)) {	203	if (WARN_ON(ret)) {
204	drm_gem_object_unreference(&obj->base);	204	drm_gem_object_unreference(&obj->base);
205	return ERR_PTR(ret);	205	return ERR_PTR(ret);
206	}	206	}
207	}	207	}
208		208
209	return obj;	209	return obj;
210	}	210	}
211		211
212	static struct intel_context *	212	static struct intel_context *
213	__create_hw_context(struct drm_device *dev,	213	__create_hw_context(struct drm_device *dev,
214	struct drm_i915_file_private *file_priv)	214	struct drm_i915_file_private *file_priv)
215	{	215	{
216	struct drm_i915_private *dev_priv = dev->dev_private;	216	struct drm_i915_private *dev_priv = dev->dev_private;
217	struct intel_context *ctx;	217	struct intel_context *ctx;
218	int ret;	218	int ret;
219		219
220	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);	220	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
221	if (ctx == NULL)	221	if (ctx == NULL)
222	return ERR_PTR(-ENOMEM);	222	return ERR_PTR(-ENOMEM);
223		223
224	kref_init(&ctx->ref);	224	kref_init(&ctx->ref);
225	list_add_tail(&ctx->link, &dev_priv->context_list);	225	list_add_tail(&ctx->link, &dev_priv->context_list);
226	ctx->i915 = dev_priv;	226	ctx->i915 = dev_priv;
227		227
228	if (dev_priv->hw_context_size) {	228	if (dev_priv->hw_context_size) {
229	struct drm_i915_gem_object *obj =	229	struct drm_i915_gem_object *obj =
230	i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size);	230	i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size);
231	if (IS_ERR(obj)) {	231	if (IS_ERR(obj)) {
232	ret = PTR_ERR(obj);	232	ret = PTR_ERR(obj);
233	goto err_out;	233	goto err_out;
234	}	234	}
235	ctx->legacy_hw_ctx.rcs_state = obj;	235	ctx->legacy_hw_ctx.rcs_state = obj;
236	}	236	}
237		237
238	/* Default context will never have a file_priv */	238	/* Default context will never have a file_priv */
239	if (file_priv != NULL) {	239	if (file_priv != NULL) {
240	ret = idr_alloc(&file_priv->context_idr, ctx,	240	ret = idr_alloc(&file_priv->context_idr, ctx,
241	DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);	241	DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
242	if (ret < 0)	242	if (ret < 0)
243	goto err_out;	243	goto err_out;
244	} else	244	} else
245	ret = DEFAULT_CONTEXT_HANDLE;	245	ret = DEFAULT_CONTEXT_HANDLE;
246		246
247	ctx->file_priv = file_priv;	247	ctx->file_priv = file_priv;
248	ctx->user_handle = ret;	248	ctx->user_handle = ret;
249	/* NB: Mark all slices as needing a remap so that when the context first	249	/* NB: Mark all slices as needing a remap so that when the context first
250	* loads it will restore whatever remap state already exists. If there	250	* loads it will restore whatever remap state already exists. If there
251	* is no remap info, it will be a NOP. */	251	* is no remap info, it will be a NOP. */
252	ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1;	252	ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1;
253		253
254	ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;	254	ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;
255		255
256	return ctx;	256	return ctx;
257		257
258	err_out:	258	err_out:
259	i915_gem_context_unreference(ctx);	259	i915_gem_context_unreference(ctx);
260	return ERR_PTR(ret);	260	return ERR_PTR(ret);
261	}	261	}
262		262
263	/**	263	/**
264	* The default context needs to exist per ring that uses contexts. It stores the	264	* The default context needs to exist per ring that uses contexts. It stores the
265	* context state of the GPU for applications that don't utilize HW contexts, as	265	* context state of the GPU for applications that don't utilize HW contexts, as
266	* well as an idle case.	266	* well as an idle case.
267	*/	267	*/
268	static struct intel_context *	268	static struct intel_context *
269	i915_gem_create_context(struct drm_device *dev,	269	i915_gem_create_context(struct drm_device *dev,
270	struct drm_i915_file_private *file_priv)	270	struct drm_i915_file_private *file_priv)
271	{	271	{
272	const bool is_global_default_ctx = file_priv == NULL;	272	const bool is_global_default_ctx = file_priv == NULL;
273	struct intel_context *ctx;	273	struct intel_context *ctx;
274	int ret = 0;	274	int ret = 0;
275		275
276	BUG_ON(!mutex_is_locked(&dev->struct_mutex));	276	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
277		277
278	ctx = __create_hw_context(dev, file_priv);	278	ctx = __create_hw_context(dev, file_priv);
279	if (IS_ERR(ctx))	279	if (IS_ERR(ctx))
280	return ctx;	280	return ctx;
281		281
282	if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) {	282	if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) {
283	/* We may need to do things with the shrinker which	283	/* We may need to do things with the shrinker which
284	* require us to immediately switch back to the default	284	* require us to immediately switch back to the default
285	* context. This can cause a problem as pinning the	285	* context. This can cause a problem as pinning the
286	* default context also requires GTT space which may not	286	* default context also requires GTT space which may not
287	* be available. To avoid this we always pin the default	287	* be available. To avoid this we always pin the default
288	* context.	288	* context.
289	*/	289	*/
290	ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state,	290	ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state,
291	get_context_alignment(dev), 0);	291	get_context_alignment(dev), 0);
292	if (ret) {	292	if (ret) {
293	DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);	293	DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
294	goto err_destroy;	294	goto err_destroy;
295	}	295	}
296	}	296	}
297		297
298	if (USES_FULL_PPGTT(dev)) {	298	if (USES_FULL_PPGTT(dev)) {
299	struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv);	299	struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv);
300		300
301	if (IS_ERR_OR_NULL(ppgtt)) {	301	if (IS_ERR_OR_NULL(ppgtt)) {
302	DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",	302	DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
303	PTR_ERR(ppgtt));	303	PTR_ERR(ppgtt));
304	ret = PTR_ERR(ppgtt);	304	ret = PTR_ERR(ppgtt);
305	goto err_unpin;	305	goto err_unpin;
306	}	306	}
307		307
308	ctx->ppgtt = ppgtt;	308	ctx->ppgtt = ppgtt;
309	}	309	}
310		310
311	trace_i915_context_create(ctx);	311	trace_i915_context_create(ctx);
312		312
313	return ctx;	313	return ctx;
314		314
315	err_unpin:	315	err_unpin:
316	if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state)	316	if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state)
317	i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state);	317	i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state);
318	err_destroy:	318	err_destroy:
319	idr_remove(&file_priv->context_idr, ctx->user_handle);	319	idr_remove(&file_priv->context_idr, ctx->user_handle);
320	i915_gem_context_unreference(ctx);	320	i915_gem_context_unreference(ctx);
321	return ERR_PTR(ret);	321	return ERR_PTR(ret);
322	}	322	}
-		323
-		324	static void i915_gem_context_unpin(struct intel_context *ctx,
-		325	struct intel_engine_cs *engine)
-		326	{
-		327	if (i915.enable_execlists) {
-		328	intel_lr_context_unpin(ctx, engine);
-		329	} else {
-		330	if (engine->id == RCS && ctx->legacy_hw_ctx.rcs_state)
-		331	i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state);
-		332	i915_gem_context_unreference(ctx);
-		333	}
-		334	}
323		335
324	void i915_gem_context_reset(struct drm_device *dev)	336	void i915_gem_context_reset(struct drm_device *dev)
325	{	337	{
326	struct drm_i915_private *dev_priv = dev->dev_private;	338	struct drm_i915_private *dev_priv = dev->dev_private;
327	int i;	339	int i;
328		340
329	if (i915.enable_execlists) {	341	if (i915.enable_execlists) {
330	struct intel_context *ctx;	342	struct intel_context *ctx;
331		343
332	list_for_each_entry(ctx, &dev_priv->context_list, link) {	344	list_for_each_entry(ctx, &dev_priv->context_list, link)
333	intel_lr_context_reset(dev, ctx);	345	intel_lr_context_reset(dev, ctx);
334	}	346	}
335		-
336	return;	-
337	}	-
338		347
339	for (i = 0; i < I915_NUM_RINGS; i++) {	348	for (i = 0; i < I915_NUM_RINGS; i++) {
340	struct intel_engine_cs *ring = &dev_priv->ring[i];	-
341	struct intel_context *lctx = ring->last_context;	-
342		-
343	if (lctx) {	-
344	if (lctx->legacy_hw_ctx.rcs_state && i == RCS)	-
-		349	struct intel_engine_cs *ring = &dev_priv->ring[i];
345	i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state);	350
346		351	if (ring->last_context) {
347	i915_gem_context_unreference(lctx);	352	i915_gem_context_unpin(ring->last_context, ring);
-		353	ring->last_context = NULL;
348	ring->last_context = NULL;	354	}
349	}	-
350		355	}
351	/* Force the GPU state to be reinitialised on enabling */	-
352	if (ring->default_context)	356
353	ring->default_context->legacy_hw_ctx.initialized = false;	357	/* Force the GPU state to be reinitialised on enabling */
354	}	358	dev_priv->kernel_context->legacy_hw_ctx.initialized = false;
355	}	359	}
356		360
357	int i915_gem_context_init(struct drm_device *dev)	361	int i915_gem_context_init(struct drm_device *dev)
358	{	362	{
359	struct drm_i915_private *dev_priv = dev->dev_private;	363	struct drm_i915_private *dev_priv = dev->dev_private;
360	struct intel_context *ctx;	364	struct intel_context *ctx;
361	int i;	-
362		365
363	/* Init should only be called once per module load. Eventually the	366	/* Init should only be called once per module load. Eventually the
364	* restriction on the context_disabled check can be loosened. */	367	* restriction on the context_disabled check can be loosened. */
365	if (WARN_ON(dev_priv->ring[RCS].default_context))	368	if (WARN_ON(dev_priv->kernel_context))
366	return 0;	369	return 0;
367		370
368	if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) {	371	if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) {
369	if (!i915.enable_execlists) {	372	if (!i915.enable_execlists) {
370	DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");	373	DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
371	return -EINVAL;	374	return -EINVAL;
372	}	375	}
373	}	376	}
374		377
375	if (i915.enable_execlists) {	378	if (i915.enable_execlists) {
376	/* NB: intentionally left blank. We will allocate our own	379	/* NB: intentionally left blank. We will allocate our own
377	* backing objects as we need them, thank you very much */	380	* backing objects as we need them, thank you very much */
378	dev_priv->hw_context_size = 0;	381	dev_priv->hw_context_size = 0;
379	} else if (HAS_HW_CONTEXTS(dev)) {	382	} else if (HAS_HW_CONTEXTS(dev)) {
380	dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);	383	dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
381	if (dev_priv->hw_context_size > (1<<20)) {	384	if (dev_priv->hw_context_size > (1<<20)) {
382	DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",	385	DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
383	dev_priv->hw_context_size);	386	dev_priv->hw_context_size);
384	dev_priv->hw_context_size = 0;	387	dev_priv->hw_context_size = 0;
385	}	388	}
386	}	389	}
387		390
388	ctx = i915_gem_create_context(dev, NULL);	391	ctx = i915_gem_create_context(dev, NULL);
389	if (IS_ERR(ctx)) {	392	if (IS_ERR(ctx)) {
390	DRM_ERROR("Failed to create default global context (error %ld)\n",	393	DRM_ERROR("Failed to create default global context (error %ld)\n",
391	PTR_ERR(ctx));	394	PTR_ERR(ctx));
392	return PTR_ERR(ctx);	395	return PTR_ERR(ctx);
393	}	396	}
394		-
395	for (i = 0; i < I915_NUM_RINGS; i++) {	-
396	struct intel_engine_cs *ring = &dev_priv->ring[i];	-
397		-
398	/* NB: RCS will hold a ref for all rings */	397
399	ring->default_context = ctx;	-
400	}	398	dev_priv->kernel_context = ctx;
401		399
402	DRM_DEBUG_DRIVER("%s context support initialized\n",	400	DRM_DEBUG_DRIVER("%s context support initialized\n",
403	i915.enable_execlists ? "LR" :	401	i915.enable_execlists ? "LR" :
404	dev_priv->hw_context_size ? "HW" : "fake");	402	dev_priv->hw_context_size ? "HW" : "fake");
405	return 0;	403	return 0;
406	}	404	}
407		405
408	void i915_gem_context_fini(struct drm_device *dev)	406	void i915_gem_context_fini(struct drm_device *dev)
409	{	407	{
410	struct drm_i915_private *dev_priv = dev->dev_private;	408	struct drm_i915_private *dev_priv = dev->dev_private;
411	struct intel_context *dctx = dev_priv->ring[RCS].default_context;	409	struct intel_context *dctx = dev_priv->kernel_context;
412	int i;	410	int i;
413		411
414	if (dctx->legacy_hw_ctx.rcs_state) {	412	if (dctx->legacy_hw_ctx.rcs_state) {
415	/* The only known way to stop the gpu from accessing the hw context is	413	/* The only known way to stop the gpu from accessing the hw context is
416	* to reset it. Do this as the very last operation to avoid confusing	414	* to reset it. Do this as the very last operation to avoid confusing
417	* other code, leading to spurious errors. */	415	* other code, leading to spurious errors. */
418	intel_gpu_reset(dev);	416	intel_gpu_reset(dev);
419		417
420	/* When default context is created and switched to, base object refcount	418	/* When default context is created and switched to, base object refcount
421	* will be 2 (+1 from object creation and +1 from do_switch()).	419	* will be 2 (+1 from object creation and +1 from do_switch()).
422	* i915_gem_context_fini() will be called after gpu_idle() has switched	420	* i915_gem_context_fini() will be called after gpu_idle() has switched
423	* to default context. So we need to unreference the base object once	421	* to default context. So we need to unreference the base object once
424	* to offset the do_switch part, so that i915_gem_context_unreference()	422	* to offset the do_switch part, so that i915_gem_context_unreference()
425	* can then free the base object correctly. */	423	* can then free the base object correctly. */
426	WARN_ON(!dev_priv->ring[RCS].last_context);	424	WARN_ON(!dev_priv->ring[RCS].last_context);
427	if (dev_priv->ring[RCS].last_context == dctx) {	-
428	/* Fake switch to NULL context */	-
429	WARN_ON(dctx->legacy_hw_ctx.rcs_state->active);	-
430	i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state);	-
431	i915_gem_context_unreference(dctx);	-
432	dev_priv->ring[RCS].last_context = NULL;	-
433	}	-
434		425
435	i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state);	426	i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state);
436	}	427	}
437		428
438	for (i = 0; i < I915_NUM_RINGS; i++) {	429	for (i = I915_NUM_RINGS; --i >= 0;) {
439	struct intel_engine_cs *ring = &dev_priv->ring[i];	430	struct intel_engine_cs *ring = &dev_priv->ring[i];
440		431
441	if (ring->last_context)	-
442	i915_gem_context_unreference(ring->last_context);	-
443		432	if (ring->last_context) {
444	ring->default_context = NULL;	433	i915_gem_context_unpin(ring->last_context, ring);
-		434	ring->last_context = NULL;
445	ring->last_context = NULL;	435	}
-		436	}
446	}	437
447		438	i915_gem_context_unreference(dctx);
448	i915_gem_context_unreference(dctx);	439	dev_priv->kernel_context = NULL;
449	}	440	}
450		441
451	int i915_gem_context_enable(struct drm_i915_gem_request *req)	442	int i915_gem_context_enable(struct drm_i915_gem_request *req)
452	{	443	{
453	struct intel_engine_cs *ring = req->ring;	444	struct intel_engine_cs *ring = req->ring;
454	int ret;	445	int ret;
455		446
456	if (i915.enable_execlists) {	447	if (i915.enable_execlists) {
457	if (ring->init_context == NULL)	448	if (ring->init_context == NULL)
458	return 0;	449	return 0;
459		450
460	ret = ring->init_context(req);	451	ret = ring->init_context(req);
461	} else	452	} else
462	ret = i915_switch_context(req);	453	ret = i915_switch_context(req);
463		454
464	if (ret) {	455	if (ret) {
465	DRM_ERROR("ring init context: %d\n", ret);	456	DRM_ERROR("ring init context: %d\n", ret);
466	return ret;	457	return ret;
467	}	458	}
468		459
469	return 0;	460	return 0;
470	}	461	}
471		462
472	static int context_idr_cleanup(int id, void p, void data)	463	static int context_idr_cleanup(int id, void p, void data)
473	{	464	{
474	struct intel_context *ctx = p;	465	struct intel_context *ctx = p;
475		466
476	i915_gem_context_unreference(ctx);	467	i915_gem_context_unreference(ctx);
477	return 0;	468	return 0;
478	}	469	}
479		470
480	int i915_gem_context_open(struct drm_device dev, struct drm_file file)	471	int i915_gem_context_open(struct drm_device dev, struct drm_file file)
481	{	472	{
482	struct drm_i915_file_private *file_priv = file->driver_priv;	473	struct drm_i915_file_private *file_priv = file->driver_priv;
483	struct intel_context *ctx;	474	struct intel_context *ctx;
484		475

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_gem_context.c – Rev 6937 → 7144