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1 | /* |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation |
2 | * Copyright © 2011-2012 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
21 | * IN THE SOFTWARE. |
21 | * IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Ben Widawsky |
24 | * Ben Widawsky |
25 | * |
25 | * |
26 | */ |
26 | */ |
27 | 27 | ||
28 | /* |
28 | /* |
29 | * This file implements HW context support. On gen5+ a HW context consists of an |
29 | * This file implements HW context support. On gen5+ a HW context consists of an |
30 | * opaque GPU object which is referenced at times of context saves and restores. |
30 | * opaque GPU object which is referenced at times of context saves and restores. |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though |
33 | * something like a context does exist for the media ring, the code only |
33 | * something like a context does exist for the media ring, the code only |
34 | * supports contexts for the render ring. |
34 | * supports contexts for the render ring. |
35 | * |
35 | * |
36 | * In software, there is a distinction between contexts created by the user, |
36 | * In software, there is a distinction between contexts created by the user, |
37 | * and the default HW context. The default HW context is used by GPU clients |
37 | * and the default HW context. The default HW context is used by GPU clients |
38 | * that do not request setup of their own hardware context. The default |
38 | * that do not request setup of their own hardware context. The default |
39 | * context's state is never restored to help prevent programming errors. This |
39 | * context's state is never restored to help prevent programming errors. This |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. |
41 | * The default context only exists to give the GPU some offset to load as the |
41 | * The default context only exists to give the GPU some offset to load as the |
42 | * current to invoke a save of the context we actually care about. In fact, the |
42 | * current to invoke a save of the context we actually care about. In fact, the |
43 | * code could likely be constructed, albeit in a more complicated fashion, to |
43 | * code could likely be constructed, albeit in a more complicated fashion, to |
44 | * never use the default context, though that limits the driver's ability to |
44 | * never use the default context, though that limits the driver's ability to |
45 | * swap out, and/or destroy other contexts. |
45 | * swap out, and/or destroy other contexts. |
46 | * |
46 | * |
47 | * All other contexts are created as a request by the GPU client. These contexts |
47 | * All other contexts are created as a request by the GPU client. These contexts |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and |
49 | * potentially query certain state) at any time. The kernel driver makes |
49 | * potentially query certain state) at any time. The kernel driver makes |
50 | * certain that the appropriate commands are inserted. |
50 | * certain that the appropriate commands are inserted. |
51 | * |
51 | * |
52 | * The context life cycle is semi-complicated in that context BOs may live |
52 | * The context life cycle is semi-complicated in that context BOs may live |
53 | * longer than the context itself because of the way the hardware, and object |
53 | * longer than the context itself because of the way the hardware, and object |
54 | * tracking works. Below is a very crude representation of the state machine |
54 | * tracking works. Below is a very crude representation of the state machine |
55 | * describing the context life. |
55 | * describing the context life. |
56 | * refcount pincount active |
56 | * refcount pincount active |
57 | * S0: initial state 0 0 0 |
57 | * S0: initial state 0 0 0 |
58 | * S1: context created 1 0 0 |
58 | * S1: context created 1 0 0 |
59 | * S2: context is currently running 2 1 X |
59 | * S2: context is currently running 2 1 X |
60 | * S3: GPU referenced, but not current 2 0 1 |
60 | * S3: GPU referenced, but not current 2 0 1 |
61 | * S4: context is current, but destroyed 1 1 0 |
61 | * S4: context is current, but destroyed 1 1 0 |
62 | * S5: like S3, but destroyed 1 0 1 |
62 | * S5: like S3, but destroyed 1 0 1 |
63 | * |
63 | * |
64 | * The most common (but not all) transitions: |
64 | * The most common (but not all) transitions: |
65 | * S0->S1: client creates a context |
65 | * S0->S1: client creates a context |
66 | * S1->S2: client submits execbuf with context |
66 | * S1->S2: client submits execbuf with context |
67 | * S2->S3: other clients submits execbuf with context |
67 | * S2->S3: other clients submits execbuf with context |
68 | * S3->S1: context object was retired |
68 | * S3->S1: context object was retired |
69 | * S3->S2: clients submits another execbuf |
69 | * S3->S2: clients submits another execbuf |
70 | * S2->S4: context destroy called with current context |
70 | * S2->S4: context destroy called with current context |
71 | * S3->S5->S0: destroy path |
71 | * S3->S5->S0: destroy path |
72 | * S4->S5->S0: destroy path on current context |
72 | * S4->S5->S0: destroy path on current context |
73 | * |
73 | * |
74 | * There are two confusing terms used above: |
74 | * There are two confusing terms used above: |
75 | * The "current context" means the context which is currently running on the |
75 | * The "current context" means the context which is currently running on the |
76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this |
78 | * offset, but it will on the next context switch. The only way to avoid this |
79 | * is to do a GPU reset. |
79 | * is to do a GPU reset. |
80 | * |
80 | * |
81 | * An "active context' is one which was previously the "current context" and is |
81 | * An "active context' is one which was previously the "current context" and is |
82 | * on the active list waiting for the next context switch to occur. Until this |
82 | * on the active list waiting for the next context switch to occur. Until this |
83 | * happens, the object must remain at the same gtt offset. It is therefore |
83 | * happens, the object must remain at the same gtt offset. It is therefore |
84 | * possible to destroy a context, but it is still active. |
84 | * possible to destroy a context, but it is still active. |
85 | * |
85 | * |
86 | */ |
86 | */ |
87 | 87 | ||
88 | #include |
88 | #include |
89 | #include |
89 | #include |
90 | #include "i915_drv.h" |
90 | #include "i915_drv.h" |
91 | #include "i915_trace.h" |
91 | #include "i915_trace.h" |
92 | 92 | ||
93 | /* This is a HW constraint. The value below is the largest known requirement |
93 | /* This is a HW constraint. The value below is the largest known requirement |
94 | * I've seen in a spec to date, and that was a workaround for a non-shipping |
94 | * I've seen in a spec to date, and that was a workaround for a non-shipping |
95 | * part. It should be safe to decrease this, but it's more future proof as is. |
95 | * part. It should be safe to decrease this, but it's more future proof as is. |
96 | */ |
96 | */ |
97 | #define GEN6_CONTEXT_ALIGN (64<<10) |
97 | #define GEN6_CONTEXT_ALIGN (64<<10) |
98 | #define GEN7_CONTEXT_ALIGN 4096 |
98 | #define GEN7_CONTEXT_ALIGN 4096 |
99 | 99 | ||
100 | static size_t get_context_alignment(struct drm_device *dev) |
100 | static size_t get_context_alignment(struct drm_device *dev) |
101 | { |
101 | { |
102 | if (IS_GEN6(dev)) |
102 | if (IS_GEN6(dev)) |
103 | return GEN6_CONTEXT_ALIGN; |
103 | return GEN6_CONTEXT_ALIGN; |
104 | 104 | ||
105 | return GEN7_CONTEXT_ALIGN; |
105 | return GEN7_CONTEXT_ALIGN; |
106 | } |
106 | } |
107 | 107 | ||
108 | static int get_context_size(struct drm_device *dev) |
108 | static int get_context_size(struct drm_device *dev) |
109 | { |
109 | { |
110 | struct drm_i915_private *dev_priv = dev->dev_private; |
110 | struct drm_i915_private *dev_priv = dev->dev_private; |
111 | int ret; |
111 | int ret; |
112 | u32 reg; |
112 | u32 reg; |
113 | 113 | ||
114 | switch (INTEL_INFO(dev)->gen) { |
114 | switch (INTEL_INFO(dev)->gen) { |
115 | case 6: |
115 | case 6: |
116 | reg = I915_READ(CXT_SIZE); |
116 | reg = I915_READ(CXT_SIZE); |
117 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; |
117 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; |
118 | break; |
118 | break; |
119 | case 7: |
119 | case 7: |
120 | reg = I915_READ(GEN7_CXT_SIZE); |
120 | reg = I915_READ(GEN7_CXT_SIZE); |
121 | if (IS_HASWELL(dev)) |
121 | if (IS_HASWELL(dev)) |
122 | ret = HSW_CXT_TOTAL_SIZE; |
122 | ret = HSW_CXT_TOTAL_SIZE; |
123 | else |
123 | else |
124 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; |
124 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; |
125 | break; |
125 | break; |
126 | case 8: |
126 | case 8: |
127 | ret = GEN8_CXT_TOTAL_SIZE; |
127 | ret = GEN8_CXT_TOTAL_SIZE; |
128 | break; |
128 | break; |
129 | default: |
129 | default: |
130 | BUG(); |
130 | BUG(); |
131 | } |
131 | } |
132 | 132 | ||
133 | return ret; |
133 | return ret; |
134 | } |
134 | } |
135 | 135 | ||
136 | static void i915_gem_context_clean(struct intel_context *ctx) |
136 | static void i915_gem_context_clean(struct intel_context *ctx) |
137 | { |
137 | { |
138 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
138 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
139 | struct i915_vma *vma, *next; |
139 | struct i915_vma *vma, *next; |
140 | 140 | ||
141 | if (!ppgtt) |
141 | if (!ppgtt) |
142 | return; |
142 | return; |
143 | 143 | ||
144 | list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list, |
144 | list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list, |
145 | mm_list) { |
145 | mm_list) { |
146 | if (WARN_ON(__i915_vma_unbind_no_wait(vma))) |
146 | if (WARN_ON(__i915_vma_unbind_no_wait(vma))) |
147 | break; |
147 | break; |
148 | } |
148 | } |
149 | } |
149 | } |
150 | 150 | ||
151 | void i915_gem_context_free(struct kref *ctx_ref) |
151 | void i915_gem_context_free(struct kref *ctx_ref) |
152 | { |
152 | { |
153 | struct intel_context *ctx = container_of(ctx_ref, typeof(*ctx), ref); |
153 | struct intel_context *ctx = container_of(ctx_ref, typeof(*ctx), ref); |
154 | 154 | ||
155 | trace_i915_context_free(ctx); |
155 | trace_i915_context_free(ctx); |
156 | 156 | ||
157 | if (i915.enable_execlists) |
157 | if (i915.enable_execlists) |
158 | intel_lr_context_free(ctx); |
158 | intel_lr_context_free(ctx); |
159 | 159 | ||
160 | /* |
160 | /* |
161 | * This context is going away and we need to remove all VMAs still |
161 | * This context is going away and we need to remove all VMAs still |
162 | * around. This is to handle imported shared objects for which |
162 | * around. This is to handle imported shared objects for which |
163 | * destructor did not run when their handles were closed. |
163 | * destructor did not run when their handles were closed. |
164 | */ |
164 | */ |
165 | i915_gem_context_clean(ctx); |
165 | i915_gem_context_clean(ctx); |
166 | 166 | ||
167 | i915_ppgtt_put(ctx->ppgtt); |
167 | i915_ppgtt_put(ctx->ppgtt); |
168 | 168 | ||
169 | if (ctx->legacy_hw_ctx.rcs_state) |
169 | if (ctx->legacy_hw_ctx.rcs_state) |
170 | drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base); |
170 | drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base); |
171 | list_del(&ctx->link); |
171 | list_del(&ctx->link); |
172 | kfree(ctx); |
172 | kfree(ctx); |
173 | } |
173 | } |
174 | 174 | ||
175 | struct drm_i915_gem_object * |
175 | struct drm_i915_gem_object * |
176 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) |
176 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) |
177 | { |
177 | { |
178 | struct drm_i915_gem_object *obj; |
178 | struct drm_i915_gem_object *obj; |
179 | int ret; |
179 | int ret; |
180 | 180 | ||
181 | obj = i915_gem_alloc_object(dev, size); |
181 | obj = i915_gem_alloc_object(dev, size); |
182 | if (obj == NULL) |
182 | if (obj == NULL) |
183 | return ERR_PTR(-ENOMEM); |
183 | return ERR_PTR(-ENOMEM); |
184 | 184 | ||
185 | /* |
185 | /* |
186 | * Try to make the context utilize L3 as well as LLC. |
186 | * Try to make the context utilize L3 as well as LLC. |
187 | * |
187 | * |
188 | * On VLV we don't have L3 controls in the PTEs so we |
188 | * On VLV we don't have L3 controls in the PTEs so we |
189 | * shouldn't touch the cache level, especially as that |
189 | * shouldn't touch the cache level, especially as that |
190 | * would make the object snooped which might have a |
190 | * would make the object snooped which might have a |
191 | * negative performance impact. |
191 | * negative performance impact. |
192 | */ |
192 | */ |
193 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) { |
193 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) { |
194 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); |
194 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); |
195 | /* Failure shouldn't ever happen this early */ |
195 | /* Failure shouldn't ever happen this early */ |
196 | if (WARN_ON(ret)) { |
196 | if (WARN_ON(ret)) { |
197 | drm_gem_object_unreference(&obj->base); |
197 | drm_gem_object_unreference(&obj->base); |
198 | return ERR_PTR(ret); |
198 | return ERR_PTR(ret); |
199 | } |
199 | } |
200 | } |
200 | } |
201 | 201 | ||
202 | return obj; |
202 | return obj; |
203 | } |
203 | } |
204 | 204 | ||
205 | static struct intel_context * |
205 | static struct intel_context * |
206 | __create_hw_context(struct drm_device *dev, |
206 | __create_hw_context(struct drm_device *dev, |
207 | struct drm_i915_file_private *file_priv) |
207 | struct drm_i915_file_private *file_priv) |
208 | { |
208 | { |
209 | struct drm_i915_private *dev_priv = dev->dev_private; |
209 | struct drm_i915_private *dev_priv = dev->dev_private; |
210 | struct intel_context *ctx; |
210 | struct intel_context *ctx; |
211 | int ret; |
211 | int ret; |
212 | 212 | ||
213 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
213 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
214 | if (ctx == NULL) |
214 | if (ctx == NULL) |
215 | return ERR_PTR(-ENOMEM); |
215 | return ERR_PTR(-ENOMEM); |
216 | 216 | ||
217 | kref_init(&ctx->ref); |
217 | kref_init(&ctx->ref); |
218 | list_add_tail(&ctx->link, &dev_priv->context_list); |
218 | list_add_tail(&ctx->link, &dev_priv->context_list); |
219 | ctx->i915 = dev_priv; |
219 | ctx->i915 = dev_priv; |
220 | 220 | ||
221 | if (dev_priv->hw_context_size) { |
221 | if (dev_priv->hw_context_size) { |
222 | struct drm_i915_gem_object *obj = |
222 | struct drm_i915_gem_object *obj = |
223 | i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size); |
223 | i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size); |
224 | if (IS_ERR(obj)) { |
224 | if (IS_ERR(obj)) { |
225 | ret = PTR_ERR(obj); |
225 | ret = PTR_ERR(obj); |
226 | goto err_out; |
226 | goto err_out; |
227 | } |
227 | } |
228 | ctx->legacy_hw_ctx.rcs_state = obj; |
228 | ctx->legacy_hw_ctx.rcs_state = obj; |
229 | } |
229 | } |
230 | 230 | ||
231 | /* Default context will never have a file_priv */ |
231 | /* Default context will never have a file_priv */ |
232 | if (file_priv != NULL) { |
232 | if (file_priv != NULL) { |
233 | ret = idr_alloc(&file_priv->context_idr, ctx, |
233 | ret = idr_alloc(&file_priv->context_idr, ctx, |
234 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
234 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
235 | if (ret < 0) |
235 | if (ret < 0) |
236 | goto err_out; |
236 | goto err_out; |
237 | } else |
237 | } else |
238 | ret = DEFAULT_CONTEXT_HANDLE; |
238 | ret = DEFAULT_CONTEXT_HANDLE; |
239 | 239 | ||
240 | ctx->file_priv = file_priv; |
240 | ctx->file_priv = file_priv; |
241 | ctx->user_handle = ret; |
241 | ctx->user_handle = ret; |
242 | /* NB: Mark all slices as needing a remap so that when the context first |
242 | /* NB: Mark all slices as needing a remap so that when the context first |
243 | * loads it will restore whatever remap state already exists. If there |
243 | * loads it will restore whatever remap state already exists. If there |
244 | * is no remap info, it will be a NOP. */ |
244 | * is no remap info, it will be a NOP. */ |
245 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; |
245 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; |
246 | 246 | ||
247 | ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD; |
247 | ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD; |
248 | 248 | ||
249 | return ctx; |
249 | return ctx; |
250 | 250 | ||
251 | err_out: |
251 | err_out: |
252 | i915_gem_context_unreference(ctx); |
252 | i915_gem_context_unreference(ctx); |
253 | return ERR_PTR(ret); |
253 | return ERR_PTR(ret); |
254 | } |
254 | } |
255 | 255 | ||
256 | /** |
256 | /** |
257 | * The default context needs to exist per ring that uses contexts. It stores the |
257 | * The default context needs to exist per ring that uses contexts. It stores the |
258 | * context state of the GPU for applications that don't utilize HW contexts, as |
258 | * context state of the GPU for applications that don't utilize HW contexts, as |
259 | * well as an idle case. |
259 | * well as an idle case. |
260 | */ |
260 | */ |
261 | static struct intel_context * |
261 | static struct intel_context * |
262 | i915_gem_create_context(struct drm_device *dev, |
262 | i915_gem_create_context(struct drm_device *dev, |
263 | struct drm_i915_file_private *file_priv) |
263 | struct drm_i915_file_private *file_priv) |
264 | { |
264 | { |
265 | const bool is_global_default_ctx = file_priv == NULL; |
265 | const bool is_global_default_ctx = file_priv == NULL; |
266 | struct intel_context *ctx; |
266 | struct intel_context *ctx; |
267 | int ret = 0; |
267 | int ret = 0; |
268 | 268 | ||
269 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
269 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
270 | 270 | ||
271 | ctx = __create_hw_context(dev, file_priv); |
271 | ctx = __create_hw_context(dev, file_priv); |
272 | if (IS_ERR(ctx)) |
272 | if (IS_ERR(ctx)) |
273 | return ctx; |
273 | return ctx; |
274 | 274 | ||
275 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) { |
275 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) { |
276 | /* We may need to do things with the shrinker which |
276 | /* We may need to do things with the shrinker which |
277 | * require us to immediately switch back to the default |
277 | * require us to immediately switch back to the default |
278 | * context. This can cause a problem as pinning the |
278 | * context. This can cause a problem as pinning the |
279 | * default context also requires GTT space which may not |
279 | * default context also requires GTT space which may not |
280 | * be available. To avoid this we always pin the default |
280 | * be available. To avoid this we always pin the default |
281 | * context. |
281 | * context. |
282 | */ |
282 | */ |
283 | ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, |
283 | ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, |
284 | get_context_alignment(dev), 0); |
284 | get_context_alignment(dev), 0); |
285 | if (ret) { |
285 | if (ret) { |
286 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); |
286 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); |
287 | goto err_destroy; |
287 | goto err_destroy; |
288 | } |
288 | } |
289 | } |
289 | } |
290 | 290 | ||
291 | if (USES_FULL_PPGTT(dev)) { |
291 | if (USES_FULL_PPGTT(dev)) { |
292 | struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv); |
292 | struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv); |
293 | 293 | ||
294 | if (IS_ERR_OR_NULL(ppgtt)) { |
294 | if (IS_ERR_OR_NULL(ppgtt)) { |
295 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
295 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
296 | PTR_ERR(ppgtt)); |
296 | PTR_ERR(ppgtt)); |
297 | ret = PTR_ERR(ppgtt); |
297 | ret = PTR_ERR(ppgtt); |
298 | goto err_unpin; |
298 | goto err_unpin; |
299 | } |
299 | } |
300 | 300 | ||
301 | ctx->ppgtt = ppgtt; |
301 | ctx->ppgtt = ppgtt; |
302 | } |
302 | } |
303 | 303 | ||
304 | trace_i915_context_create(ctx); |
304 | trace_i915_context_create(ctx); |
305 | 305 | ||
306 | return ctx; |
306 | return ctx; |
307 | 307 | ||
308 | err_unpin: |
308 | err_unpin: |
309 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) |
309 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) |
310 | i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); |
310 | i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); |
311 | err_destroy: |
311 | err_destroy: |
312 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
312 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
313 | i915_gem_context_unreference(ctx); |
313 | i915_gem_context_unreference(ctx); |
314 | return ERR_PTR(ret); |
314 | return ERR_PTR(ret); |
315 | } |
315 | } |
316 | 316 | ||
317 | void i915_gem_context_reset(struct drm_device *dev) |
317 | void i915_gem_context_reset(struct drm_device *dev) |
318 | { |
318 | { |
319 | struct drm_i915_private *dev_priv = dev->dev_private; |
319 | struct drm_i915_private *dev_priv = dev->dev_private; |
320 | int i; |
320 | int i; |
321 | 321 | ||
322 | if (i915.enable_execlists) { |
322 | if (i915.enable_execlists) { |
323 | struct intel_context *ctx; |
323 | struct intel_context *ctx; |
324 | 324 | ||
325 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
325 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
326 | intel_lr_context_reset(dev, ctx); |
326 | intel_lr_context_reset(dev, ctx); |
327 | } |
327 | } |
328 | 328 | ||
329 | return; |
329 | return; |
330 | } |
330 | } |
331 | 331 | ||
332 | for (i = 0; i < I915_NUM_RINGS; i++) { |
332 | for (i = 0; i < I915_NUM_RINGS; i++) { |
333 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
333 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
334 | struct intel_context *lctx = ring->last_context; |
334 | struct intel_context *lctx = ring->last_context; |
335 | 335 | ||
336 | if (lctx) { |
336 | if (lctx) { |
337 | if (lctx->legacy_hw_ctx.rcs_state && i == RCS) |
337 | if (lctx->legacy_hw_ctx.rcs_state && i == RCS) |
338 | i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state); |
338 | i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state); |
339 | 339 | ||
340 | i915_gem_context_unreference(lctx); |
340 | i915_gem_context_unreference(lctx); |
341 | ring->last_context = NULL; |
341 | ring->last_context = NULL; |
342 | } |
342 | } |
- | 343 | ||
- | 344 | /* Force the GPU state to be reinitialised on enabling */ |
|
- | 345 | if (ring->default_context) |
|
- | 346 | ring->default_context->legacy_hw_ctx.initialized = false; |
|
343 | } |
347 | } |
344 | } |
348 | } |
345 | 349 | ||
346 | int i915_gem_context_init(struct drm_device *dev) |
350 | int i915_gem_context_init(struct drm_device *dev) |
347 | { |
351 | { |
348 | struct drm_i915_private *dev_priv = dev->dev_private; |
352 | struct drm_i915_private *dev_priv = dev->dev_private; |
349 | struct intel_context *ctx; |
353 | struct intel_context *ctx; |
350 | int i; |
354 | int i; |
351 | 355 | ||
352 | /* Init should only be called once per module load. Eventually the |
356 | /* Init should only be called once per module load. Eventually the |
353 | * restriction on the context_disabled check can be loosened. */ |
357 | * restriction on the context_disabled check can be loosened. */ |
354 | if (WARN_ON(dev_priv->ring[RCS].default_context)) |
358 | if (WARN_ON(dev_priv->ring[RCS].default_context)) |
355 | return 0; |
359 | return 0; |
356 | 360 | ||
357 | if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) { |
361 | if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) { |
358 | if (!i915.enable_execlists) { |
362 | if (!i915.enable_execlists) { |
359 | DRM_INFO("Only EXECLIST mode is supported in vgpu.\n"); |
363 | DRM_INFO("Only EXECLIST mode is supported in vgpu.\n"); |
360 | return -EINVAL; |
364 | return -EINVAL; |
361 | } |
365 | } |
362 | } |
366 | } |
363 | 367 | ||
364 | if (i915.enable_execlists) { |
368 | if (i915.enable_execlists) { |
365 | /* NB: intentionally left blank. We will allocate our own |
369 | /* NB: intentionally left blank. We will allocate our own |
366 | * backing objects as we need them, thank you very much */ |
370 | * backing objects as we need them, thank you very much */ |
367 | dev_priv->hw_context_size = 0; |
371 | dev_priv->hw_context_size = 0; |
368 | } else if (HAS_HW_CONTEXTS(dev)) { |
372 | } else if (HAS_HW_CONTEXTS(dev)) { |
369 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
373 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
370 | if (dev_priv->hw_context_size > (1<<20)) { |
374 | if (dev_priv->hw_context_size > (1<<20)) { |
371 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", |
375 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", |
372 | dev_priv->hw_context_size); |
376 | dev_priv->hw_context_size); |
373 | dev_priv->hw_context_size = 0; |
377 | dev_priv->hw_context_size = 0; |
374 | } |
378 | } |
375 | } |
379 | } |
376 | 380 | ||
377 | ctx = i915_gem_create_context(dev, NULL); |
381 | ctx = i915_gem_create_context(dev, NULL); |
378 | if (IS_ERR(ctx)) { |
382 | if (IS_ERR(ctx)) { |
379 | DRM_ERROR("Failed to create default global context (error %ld)\n", |
383 | DRM_ERROR("Failed to create default global context (error %ld)\n", |
380 | PTR_ERR(ctx)); |
384 | PTR_ERR(ctx)); |
381 | return PTR_ERR(ctx); |
385 | return PTR_ERR(ctx); |
382 | } |
386 | } |
383 | 387 | ||
384 | for (i = 0; i < I915_NUM_RINGS; i++) { |
388 | for (i = 0; i < I915_NUM_RINGS; i++) { |
385 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
389 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
386 | 390 | ||
387 | /* NB: RCS will hold a ref for all rings */ |
391 | /* NB: RCS will hold a ref for all rings */ |
388 | ring->default_context = ctx; |
392 | ring->default_context = ctx; |
389 | } |
393 | } |
390 | 394 | ||
391 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
395 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
392 | i915.enable_execlists ? "LR" : |
396 | i915.enable_execlists ? "LR" : |
393 | dev_priv->hw_context_size ? "HW" : "fake"); |
397 | dev_priv->hw_context_size ? "HW" : "fake"); |
394 | return 0; |
398 | return 0; |
395 | } |
399 | } |
396 | 400 | ||
397 | void i915_gem_context_fini(struct drm_device *dev) |
401 | void i915_gem_context_fini(struct drm_device *dev) |
398 | { |
402 | { |
399 | struct drm_i915_private *dev_priv = dev->dev_private; |
403 | struct drm_i915_private *dev_priv = dev->dev_private; |
400 | struct intel_context *dctx = dev_priv->ring[RCS].default_context; |
404 | struct intel_context *dctx = dev_priv->ring[RCS].default_context; |
401 | int i; |
405 | int i; |
402 | 406 | ||
403 | if (dctx->legacy_hw_ctx.rcs_state) { |
407 | if (dctx->legacy_hw_ctx.rcs_state) { |
404 | /* The only known way to stop the gpu from accessing the hw context is |
408 | /* The only known way to stop the gpu from accessing the hw context is |
405 | * to reset it. Do this as the very last operation to avoid confusing |
409 | * to reset it. Do this as the very last operation to avoid confusing |
406 | * other code, leading to spurious errors. */ |
410 | * other code, leading to spurious errors. */ |
407 | intel_gpu_reset(dev); |
411 | intel_gpu_reset(dev); |
408 | 412 | ||
409 | /* When default context is created and switched to, base object refcount |
413 | /* When default context is created and switched to, base object refcount |
410 | * will be 2 (+1 from object creation and +1 from do_switch()). |
414 | * will be 2 (+1 from object creation and +1 from do_switch()). |
411 | * i915_gem_context_fini() will be called after gpu_idle() has switched |
415 | * i915_gem_context_fini() will be called after gpu_idle() has switched |
412 | * to default context. So we need to unreference the base object once |
416 | * to default context. So we need to unreference the base object once |
413 | * to offset the do_switch part, so that i915_gem_context_unreference() |
417 | * to offset the do_switch part, so that i915_gem_context_unreference() |
414 | * can then free the base object correctly. */ |
418 | * can then free the base object correctly. */ |
415 | WARN_ON(!dev_priv->ring[RCS].last_context); |
419 | WARN_ON(!dev_priv->ring[RCS].last_context); |
416 | if (dev_priv->ring[RCS].last_context == dctx) { |
420 | if (dev_priv->ring[RCS].last_context == dctx) { |
417 | /* Fake switch to NULL context */ |
421 | /* Fake switch to NULL context */ |
418 | WARN_ON(dctx->legacy_hw_ctx.rcs_state->active); |
422 | WARN_ON(dctx->legacy_hw_ctx.rcs_state->active); |
419 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
423 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
420 | i915_gem_context_unreference(dctx); |
424 | i915_gem_context_unreference(dctx); |
421 | dev_priv->ring[RCS].last_context = NULL; |
425 | dev_priv->ring[RCS].last_context = NULL; |
422 | } |
426 | } |
423 | 427 | ||
424 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
428 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
425 | } |
429 | } |
426 | 430 | ||
427 | for (i = 0; i < I915_NUM_RINGS; i++) { |
431 | for (i = 0; i < I915_NUM_RINGS; i++) { |
428 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
432 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
429 | 433 | ||
430 | if (ring->last_context) |
434 | if (ring->last_context) |
431 | i915_gem_context_unreference(ring->last_context); |
435 | i915_gem_context_unreference(ring->last_context); |
432 | 436 | ||
433 | ring->default_context = NULL; |
437 | ring->default_context = NULL; |
434 | ring->last_context = NULL; |
438 | ring->last_context = NULL; |
435 | } |
439 | } |
436 | 440 | ||
437 | i915_gem_context_unreference(dctx); |
441 | i915_gem_context_unreference(dctx); |
438 | } |
442 | } |
439 | 443 | ||
440 | int i915_gem_context_enable(struct drm_i915_gem_request *req) |
444 | int i915_gem_context_enable(struct drm_i915_gem_request *req) |
441 | { |
445 | { |
442 | struct intel_engine_cs *ring = req->ring; |
446 | struct intel_engine_cs *ring = req->ring; |
443 | int ret; |
447 | int ret; |
444 | 448 | ||
445 | if (i915.enable_execlists) { |
449 | if (i915.enable_execlists) { |
446 | if (ring->init_context == NULL) |
450 | if (ring->init_context == NULL) |
447 | return 0; |
451 | return 0; |
448 | 452 | ||
449 | ret = ring->init_context(req); |
453 | ret = ring->init_context(req); |
450 | } else |
454 | } else |
451 | ret = i915_switch_context(req); |
455 | ret = i915_switch_context(req); |
452 | 456 | ||
453 | if (ret) { |
457 | if (ret) { |
454 | DRM_ERROR("ring init context: %d\n", ret); |
458 | DRM_ERROR("ring init context: %d\n", ret); |
455 | return ret; |
459 | return ret; |
456 | } |
460 | } |
457 | 461 | ||
458 | return 0; |
462 | return 0; |
459 | } |
463 | } |
460 | 464 | ||
461 | static int context_idr_cleanup(int id, void *p, void *data) |
465 | static int context_idr_cleanup(int id, void *p, void *data) |
462 | { |
466 | { |
463 | struct intel_context *ctx = p; |
467 | struct intel_context *ctx = p; |
464 | 468 | ||
465 | i915_gem_context_unreference(ctx); |
469 | i915_gem_context_unreference(ctx); |
466 | return 0; |
470 | return 0; |
467 | } |
471 | } |
468 | 472 | ||
469 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
473 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
470 | { |
474 | { |
471 | struct drm_i915_file_private *file_priv = file->driver_priv; |
475 | struct drm_i915_file_private *file_priv = file->driver_priv; |
472 | struct intel_context *ctx; |
476 | struct intel_context *ctx; |
473 | 477 | ||
474 | idr_init(&file_priv->context_idr); |
478 | idr_init(&file_priv->context_idr); |
475 | 479 | ||
476 | mutex_lock(&dev->struct_mutex); |
480 | mutex_lock(&dev->struct_mutex); |
477 | ctx = i915_gem_create_context(dev, file_priv); |
481 | ctx = i915_gem_create_context(dev, file_priv); |
478 | mutex_unlock(&dev->struct_mutex); |
482 | mutex_unlock(&dev->struct_mutex); |
479 | 483 | ||
480 | if (IS_ERR(ctx)) { |
484 | if (IS_ERR(ctx)) { |
481 | idr_destroy(&file_priv->context_idr); |
485 | idr_destroy(&file_priv->context_idr); |
482 | return PTR_ERR(ctx); |
486 | return PTR_ERR(ctx); |
483 | } |
487 | } |
484 | 488 | ||
485 | return 0; |
489 | return 0; |
486 | } |
490 | } |
487 | 491 | ||
488 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
492 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
489 | { |
493 | { |
490 | struct drm_i915_file_private *file_priv = file->driver_priv; |
494 | struct drm_i915_file_private *file_priv = file->driver_priv; |
491 | 495 | ||
492 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
496 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
493 | idr_destroy(&file_priv->context_idr); |
497 | idr_destroy(&file_priv->context_idr); |
494 | } |
498 | } |
495 | 499 | ||
496 | struct intel_context * |
500 | struct intel_context * |
497 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
501 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
498 | { |
502 | { |
499 | struct intel_context *ctx; |
503 | struct intel_context *ctx; |
500 | 504 | ||
501 | ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id); |
505 | ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id); |
502 | if (!ctx) |
506 | if (!ctx) |
503 | return ERR_PTR(-ENOENT); |
507 | return ERR_PTR(-ENOENT); |
504 | 508 | ||
505 | return ctx; |
509 | return ctx; |
506 | } |
510 | } |
507 | 511 | ||
508 | static inline int |
512 | static inline int |
509 | mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) |
513 | mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) |
510 | { |
514 | { |
511 | struct intel_engine_cs *ring = req->ring; |
515 | struct intel_engine_cs *ring = req->ring; |
512 | u32 flags = hw_flags | MI_MM_SPACE_GTT; |
516 | u32 flags = hw_flags | MI_MM_SPACE_GTT; |
513 | const int num_rings = |
517 | const int num_rings = |
514 | /* Use an extended w/a on ivb+ if signalling from other rings */ |
518 | /* Use an extended w/a on ivb+ if signalling from other rings */ |
515 | i915_semaphore_is_enabled(ring->dev) ? |
519 | i915_semaphore_is_enabled(ring->dev) ? |
516 | hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 : |
520 | hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 : |
517 | 0; |
521 | 0; |
518 | int len, i, ret; |
522 | int len, i, ret; |
519 | 523 | ||
520 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
524 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
521 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value |
525 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value |
522 | * explicitly, so we rely on the value at ring init, stored in |
526 | * explicitly, so we rely on the value at ring init, stored in |
523 | * itlb_before_ctx_switch. |
527 | * itlb_before_ctx_switch. |
524 | */ |
528 | */ |
525 | if (IS_GEN6(ring->dev)) { |
529 | if (IS_GEN6(ring->dev)) { |
526 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0); |
530 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0); |
527 | if (ret) |
531 | if (ret) |
528 | return ret; |
532 | return ret; |
529 | } |
533 | } |
530 | 534 | ||
531 | /* These flags are for resource streamer on HSW+ */ |
535 | /* These flags are for resource streamer on HSW+ */ |
532 | if (IS_HASWELL(ring->dev) || INTEL_INFO(ring->dev)->gen >= 8) |
536 | if (IS_HASWELL(ring->dev) || INTEL_INFO(ring->dev)->gen >= 8) |
533 | flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN); |
537 | flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN); |
534 | else if (INTEL_INFO(ring->dev)->gen < 8) |
538 | else if (INTEL_INFO(ring->dev)->gen < 8) |
535 | flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); |
539 | flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); |
536 | 540 | ||
537 | 541 | ||
538 | len = 4; |
542 | len = 4; |
539 | if (INTEL_INFO(ring->dev)->gen >= 7) |
543 | if (INTEL_INFO(ring->dev)->gen >= 7) |
540 | len += 2 + (num_rings ? 4*num_rings + 2 : 0); |
544 | len += 2 + (num_rings ? 4*num_rings + 2 : 0); |
541 | 545 | ||
542 | ret = intel_ring_begin(req, len); |
546 | ret = intel_ring_begin(req, len); |
543 | if (ret) |
547 | if (ret) |
544 | return ret; |
548 | return ret; |
545 | 549 | ||
546 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
550 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
547 | if (INTEL_INFO(ring->dev)->gen >= 7) { |
551 | if (INTEL_INFO(ring->dev)->gen >= 7) { |
548 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
552 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
549 | if (num_rings) { |
553 | if (num_rings) { |
550 | struct intel_engine_cs *signaller; |
554 | struct intel_engine_cs *signaller; |
551 | 555 | ||
552 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); |
556 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); |
553 | for_each_ring(signaller, to_i915(ring->dev), i) { |
557 | for_each_ring(signaller, to_i915(ring->dev), i) { |
554 | if (signaller == ring) |
558 | if (signaller == ring) |
555 | continue; |
559 | continue; |
556 | 560 | ||
557 | intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); |
561 | intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); |
558 | intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
562 | intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
559 | } |
563 | } |
560 | } |
564 | } |
561 | } |
565 | } |
562 | 566 | ||
563 | intel_ring_emit(ring, MI_NOOP); |
567 | intel_ring_emit(ring, MI_NOOP); |
564 | intel_ring_emit(ring, MI_SET_CONTEXT); |
568 | intel_ring_emit(ring, MI_SET_CONTEXT); |
565 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(req->ctx->legacy_hw_ctx.rcs_state) | |
569 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(req->ctx->legacy_hw_ctx.rcs_state) | |
566 | flags); |
570 | flags); |
567 | /* |
571 | /* |
568 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP |
572 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP |
569 | * WaMiSetContext_Hang:snb,ivb,vlv |
573 | * WaMiSetContext_Hang:snb,ivb,vlv |
570 | */ |
574 | */ |
571 | intel_ring_emit(ring, MI_NOOP); |
575 | intel_ring_emit(ring, MI_NOOP); |
572 | 576 | ||
573 | if (INTEL_INFO(ring->dev)->gen >= 7) { |
577 | if (INTEL_INFO(ring->dev)->gen >= 7) { |
574 | if (num_rings) { |
578 | if (num_rings) { |
575 | struct intel_engine_cs *signaller; |
579 | struct intel_engine_cs *signaller; |
576 | 580 | ||
577 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); |
581 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); |
578 | for_each_ring(signaller, to_i915(ring->dev), i) { |
582 | for_each_ring(signaller, to_i915(ring->dev), i) { |
579 | if (signaller == ring) |
583 | if (signaller == ring) |
580 | continue; |
584 | continue; |
581 | 585 | ||
582 | intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); |
586 | intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); |
583 | intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
587 | intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
584 | } |
588 | } |
585 | } |
589 | } |
586 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
590 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
587 | } |
591 | } |
588 | 592 | ||
589 | intel_ring_advance(ring); |
593 | intel_ring_advance(ring); |
590 | 594 | ||
591 | return ret; |
595 | return ret; |
592 | } |
596 | } |
593 | 597 | ||
594 | static inline bool should_skip_switch(struct intel_engine_cs *ring, |
598 | static inline bool should_skip_switch(struct intel_engine_cs *ring, |
595 | struct intel_context *from, |
599 | struct intel_context *from, |
596 | struct intel_context *to) |
600 | struct intel_context *to) |
597 | { |
601 | { |
598 | if (to->remap_slice) |
602 | if (to->remap_slice) |
599 | return false; |
603 | return false; |
600 | 604 | ||
601 | if (to->ppgtt && from == to && |
605 | if (to->ppgtt && from == to && |
602 | !(intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) |
606 | !(intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) |
603 | return true; |
607 | return true; |
604 | 608 | ||
605 | return false; |
609 | return false; |
606 | } |
610 | } |
607 | 611 | ||
608 | static bool |
612 | static bool |
609 | needs_pd_load_pre(struct intel_engine_cs *ring, struct intel_context *to) |
613 | needs_pd_load_pre(struct intel_engine_cs *ring, struct intel_context *to) |
610 | { |
614 | { |
611 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
615 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
612 | 616 | ||
613 | if (!to->ppgtt) |
617 | if (!to->ppgtt) |
614 | return false; |
618 | return false; |
615 | 619 | ||
616 | if (INTEL_INFO(ring->dev)->gen < 8) |
620 | if (INTEL_INFO(ring->dev)->gen < 8) |
617 | return true; |
621 | return true; |
618 | 622 | ||
619 | if (ring != &dev_priv->ring[RCS]) |
623 | if (ring != &dev_priv->ring[RCS]) |
620 | return true; |
624 | return true; |
621 | 625 | ||
622 | return false; |
626 | return false; |
623 | } |
627 | } |
624 | 628 | ||
625 | static bool |
629 | static bool |
626 | needs_pd_load_post(struct intel_engine_cs *ring, struct intel_context *to, |
630 | needs_pd_load_post(struct intel_engine_cs *ring, struct intel_context *to, |
627 | u32 hw_flags) |
631 | u32 hw_flags) |
628 | { |
632 | { |
629 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
633 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
630 | 634 | ||
631 | if (!to->ppgtt) |
635 | if (!to->ppgtt) |
632 | return false; |
636 | return false; |
633 | 637 | ||
634 | if (!IS_GEN8(ring->dev)) |
638 | if (!IS_GEN8(ring->dev)) |
635 | return false; |
639 | return false; |
636 | 640 | ||
637 | if (ring != &dev_priv->ring[RCS]) |
641 | if (ring != &dev_priv->ring[RCS]) |
638 | return false; |
642 | return false; |
639 | 643 | ||
640 | if (hw_flags & MI_RESTORE_INHIBIT) |
644 | if (hw_flags & MI_RESTORE_INHIBIT) |
641 | return true; |
645 | return true; |
642 | 646 | ||
643 | return false; |
647 | return false; |
644 | } |
648 | } |
645 | 649 | ||
646 | static int do_switch(struct drm_i915_gem_request *req) |
650 | static int do_switch(struct drm_i915_gem_request *req) |
647 | { |
651 | { |
648 | struct intel_context *to = req->ctx; |
652 | struct intel_context *to = req->ctx; |
649 | struct intel_engine_cs *ring = req->ring; |
653 | struct intel_engine_cs *ring = req->ring; |
650 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
654 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
651 | struct intel_context *from = ring->last_context; |
655 | struct intel_context *from = ring->last_context; |
652 | u32 hw_flags = 0; |
656 | u32 hw_flags = 0; |
653 | bool uninitialized = false; |
657 | bool uninitialized = false; |
654 | int ret, i; |
658 | int ret, i; |
655 | 659 | ||
656 | if (from != NULL && ring == &dev_priv->ring[RCS]) { |
660 | if (from != NULL && ring == &dev_priv->ring[RCS]) { |
657 | BUG_ON(from->legacy_hw_ctx.rcs_state == NULL); |
661 | BUG_ON(from->legacy_hw_ctx.rcs_state == NULL); |
658 | BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state)); |
662 | BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state)); |
659 | } |
663 | } |
660 | 664 | ||
661 | if (should_skip_switch(ring, from, to)) |
665 | if (should_skip_switch(ring, from, to)) |
662 | return 0; |
666 | return 0; |
663 | 667 | ||
664 | /* Trying to pin first makes error handling easier. */ |
668 | /* Trying to pin first makes error handling easier. */ |
665 | if (ring == &dev_priv->ring[RCS]) { |
669 | if (ring == &dev_priv->ring[RCS]) { |
666 | ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state, |
670 | ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state, |
667 | get_context_alignment(ring->dev), 0); |
671 | get_context_alignment(ring->dev), 0); |
668 | if (ret) |
672 | if (ret) |
669 | return ret; |
673 | return ret; |
670 | } |
674 | } |
671 | 675 | ||
672 | /* |
676 | /* |
673 | * Pin can switch back to the default context if we end up calling into |
677 | * Pin can switch back to the default context if we end up calling into |
674 | * evict_everything - as a last ditch gtt defrag effort that also |
678 | * evict_everything - as a last ditch gtt defrag effort that also |
675 | * switches to the default context. Hence we need to reload from here. |
679 | * switches to the default context. Hence we need to reload from here. |
676 | */ |
680 | */ |
677 | from = ring->last_context; |
681 | from = ring->last_context; |
678 | 682 | ||
679 | if (needs_pd_load_pre(ring, to)) { |
683 | if (needs_pd_load_pre(ring, to)) { |
680 | /* Older GENs and non render rings still want the load first, |
684 | /* Older GENs and non render rings still want the load first, |
681 | * "PP_DCLV followed by PP_DIR_BASE register through Load |
685 | * "PP_DCLV followed by PP_DIR_BASE register through Load |
682 | * Register Immediate commands in Ring Buffer before submitting |
686 | * Register Immediate commands in Ring Buffer before submitting |
683 | * a context."*/ |
687 | * a context."*/ |
684 | trace_switch_mm(ring, to); |
688 | trace_switch_mm(ring, to); |
685 | ret = to->ppgtt->switch_mm(to->ppgtt, req); |
689 | ret = to->ppgtt->switch_mm(to->ppgtt, req); |
686 | if (ret) |
690 | if (ret) |
687 | goto unpin_out; |
691 | goto unpin_out; |
688 | 692 | ||
689 | /* Doing a PD load always reloads the page dirs */ |
693 | /* Doing a PD load always reloads the page dirs */ |
690 | to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); |
694 | to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); |
691 | } |
695 | } |
692 | 696 | ||
693 | if (ring != &dev_priv->ring[RCS]) { |
697 | if (ring != &dev_priv->ring[RCS]) { |
694 | if (from) |
698 | if (from) |
695 | i915_gem_context_unreference(from); |
699 | i915_gem_context_unreference(from); |
696 | goto done; |
700 | goto done; |
697 | } |
701 | } |
698 | 702 | ||
699 | /* |
703 | /* |
700 | * Clear this page out of any CPU caches for coherent swap-in/out. Note |
704 | * Clear this page out of any CPU caches for coherent swap-in/out. Note |
701 | * that thanks to write = false in this call and us not setting any gpu |
705 | * that thanks to write = false in this call and us not setting any gpu |
702 | * write domains when putting a context object onto the active list |
706 | * write domains when putting a context object onto the active list |
703 | * (when switching away from it), this won't block. |
707 | * (when switching away from it), this won't block. |
704 | * |
708 | * |
705 | * XXX: We need a real interface to do this instead of trickery. |
709 | * XXX: We need a real interface to do this instead of trickery. |
706 | */ |
710 | */ |
707 | ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false); |
711 | ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false); |
708 | if (ret) |
712 | if (ret) |
709 | goto unpin_out; |
713 | goto unpin_out; |
710 | 714 | ||
711 | if (!to->legacy_hw_ctx.initialized) { |
715 | if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to)) { |
712 | hw_flags |= MI_RESTORE_INHIBIT; |
716 | hw_flags |= MI_RESTORE_INHIBIT; |
713 | /* NB: If we inhibit the restore, the context is not allowed to |
717 | /* NB: If we inhibit the restore, the context is not allowed to |
714 | * die because future work may end up depending on valid address |
718 | * die because future work may end up depending on valid address |
715 | * space. This means we must enforce that a page table load |
719 | * space. This means we must enforce that a page table load |
716 | * occur when this occurs. */ |
720 | * occur when this occurs. */ |
717 | } else if (to->ppgtt && |
721 | } else if (to->ppgtt && |
718 | (intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) { |
722 | (intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) { |
719 | hw_flags |= MI_FORCE_RESTORE; |
723 | hw_flags |= MI_FORCE_RESTORE; |
720 | to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); |
724 | to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); |
721 | } |
725 | } |
722 | 726 | ||
723 | /* We should never emit switch_mm more than once */ |
727 | /* We should never emit switch_mm more than once */ |
724 | WARN_ON(needs_pd_load_pre(ring, to) && |
728 | WARN_ON(needs_pd_load_pre(ring, to) && |
725 | needs_pd_load_post(ring, to, hw_flags)); |
729 | needs_pd_load_post(ring, to, hw_flags)); |
726 | 730 | ||
727 | ret = mi_set_context(req, hw_flags); |
731 | ret = mi_set_context(req, hw_flags); |
728 | if (ret) |
732 | if (ret) |
729 | goto unpin_out; |
733 | goto unpin_out; |
730 | 734 | ||
731 | /* GEN8 does *not* require an explicit reload if the PDPs have been |
735 | /* GEN8 does *not* require an explicit reload if the PDPs have been |
732 | * setup, and we do not wish to move them. |
736 | * setup, and we do not wish to move them. |
733 | */ |
737 | */ |
734 | if (needs_pd_load_post(ring, to, hw_flags)) { |
738 | if (needs_pd_load_post(ring, to, hw_flags)) { |
735 | trace_switch_mm(ring, to); |
739 | trace_switch_mm(ring, to); |
736 | ret = to->ppgtt->switch_mm(to->ppgtt, req); |
740 | ret = to->ppgtt->switch_mm(to->ppgtt, req); |
737 | /* The hardware context switch is emitted, but we haven't |
741 | /* The hardware context switch is emitted, but we haven't |
738 | * actually changed the state - so it's probably safe to bail |
742 | * actually changed the state - so it's probably safe to bail |
739 | * here. Still, let the user know something dangerous has |
743 | * here. Still, let the user know something dangerous has |
740 | * happened. |
744 | * happened. |
741 | */ |
745 | */ |
742 | if (ret) { |
746 | if (ret) { |
743 | DRM_ERROR("Failed to change address space on context switch\n"); |
747 | DRM_ERROR("Failed to change address space on context switch\n"); |
744 | goto unpin_out; |
748 | goto unpin_out; |
745 | } |
749 | } |
746 | } |
750 | } |
747 | 751 | ||
748 | for (i = 0; i < MAX_L3_SLICES; i++) { |
752 | for (i = 0; i < MAX_L3_SLICES; i++) { |
749 | if (!(to->remap_slice & (1< |
753 | if (!(to->remap_slice & (1< |
750 | continue; |
754 | continue; |
751 | 755 | ||
752 | ret = i915_gem_l3_remap(req, i); |
756 | ret = i915_gem_l3_remap(req, i); |
753 | /* If it failed, try again next round */ |
757 | /* If it failed, try again next round */ |
754 | if (ret) |
758 | if (ret) |
755 | DRM_DEBUG_DRIVER("L3 remapping failed\n"); |
759 | DRM_DEBUG_DRIVER("L3 remapping failed\n"); |
756 | else |
760 | else |
757 | to->remap_slice &= ~(1< |
761 | to->remap_slice &= ~(1< |
758 | } |
762 | } |
759 | 763 | ||
760 | /* The backing object for the context is done after switching to the |
764 | /* The backing object for the context is done after switching to the |
761 | * *next* context. Therefore we cannot retire the previous context until |
765 | * *next* context. Therefore we cannot retire the previous context until |
762 | * the next context has already started running. In fact, the below code |
766 | * the next context has already started running. In fact, the below code |
763 | * is a bit suboptimal because the retiring can occur simply after the |
767 | * is a bit suboptimal because the retiring can occur simply after the |
764 | * MI_SET_CONTEXT instead of when the next seqno has completed. |
768 | * MI_SET_CONTEXT instead of when the next seqno has completed. |
765 | */ |
769 | */ |
766 | if (from != NULL) { |
770 | if (from != NULL) { |
767 | from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
771 | from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
768 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), req); |
772 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), req); |
769 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
773 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
770 | * whole damn pipeline, we don't need to explicitly mark the |
774 | * whole damn pipeline, we don't need to explicitly mark the |
771 | * object dirty. The only exception is that the context must be |
775 | * object dirty. The only exception is that the context must be |
772 | * correct in case the object gets swapped out. Ideally we'd be |
776 | * correct in case the object gets swapped out. Ideally we'd be |
773 | * able to defer doing this until we know the object would be |
777 | * able to defer doing this until we know the object would be |
774 | * swapped, but there is no way to do that yet. |
778 | * swapped, but there is no way to do that yet. |
775 | */ |
779 | */ |
776 | from->legacy_hw_ctx.rcs_state->dirty = 1; |
780 | from->legacy_hw_ctx.rcs_state->dirty = 1; |
777 | 781 | ||
778 | /* obj is kept alive until the next request by its active ref */ |
782 | /* obj is kept alive until the next request by its active ref */ |
779 | i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state); |
783 | i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state); |
780 | i915_gem_context_unreference(from); |
784 | i915_gem_context_unreference(from); |
781 | } |
785 | } |
782 | 786 | ||
783 | uninitialized = !to->legacy_hw_ctx.initialized; |
787 | uninitialized = !to->legacy_hw_ctx.initialized; |
784 | to->legacy_hw_ctx.initialized = true; |
788 | to->legacy_hw_ctx.initialized = true; |
785 | 789 | ||
786 | done: |
790 | done: |
787 | i915_gem_context_reference(to); |
791 | i915_gem_context_reference(to); |
788 | ring->last_context = to; |
792 | ring->last_context = to; |
789 | 793 | ||
790 | if (uninitialized) { |
794 | if (uninitialized) { |
791 | if (ring->init_context) { |
795 | if (ring->init_context) { |
792 | ret = ring->init_context(req); |
796 | ret = ring->init_context(req); |
793 | if (ret) |
797 | if (ret) |
794 | DRM_ERROR("ring init context: %d\n", ret); |
798 | DRM_ERROR("ring init context: %d\n", ret); |
795 | } |
799 | } |
796 | } |
800 | } |
797 | 801 | ||
798 | return 0; |
802 | return 0; |
799 | 803 | ||
800 | unpin_out: |
804 | unpin_out: |
801 | if (ring->id == RCS) |
805 | if (ring->id == RCS) |
802 | i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state); |
806 | i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state); |
803 | return ret; |
807 | return ret; |
804 | } |
808 | } |
805 | 809 | ||
806 | /** |
810 | /** |
807 | * i915_switch_context() - perform a GPU context switch. |
811 | * i915_switch_context() - perform a GPU context switch. |
808 | * @req: request for which we'll execute the context switch |
812 | * @req: request for which we'll execute the context switch |
809 | * |
813 | * |
810 | * The context life cycle is simple. The context refcount is incremented and |
814 | * The context life cycle is simple. The context refcount is incremented and |
811 | * decremented by 1 and create and destroy. If the context is in use by the GPU, |
815 | * decremented by 1 and create and destroy. If the context is in use by the GPU, |
812 | * it will have a refcount > 1. This allows us to destroy the context abstract |
816 | * it will have a refcount > 1. This allows us to destroy the context abstract |
813 | * object while letting the normal object tracking destroy the backing BO. |
817 | * object while letting the normal object tracking destroy the backing BO. |
814 | * |
818 | * |
815 | * This function should not be used in execlists mode. Instead the context is |
819 | * This function should not be used in execlists mode. Instead the context is |
816 | * switched by writing to the ELSP and requests keep a reference to their |
820 | * switched by writing to the ELSP and requests keep a reference to their |
817 | * context. |
821 | * context. |
818 | */ |
822 | */ |
819 | int i915_switch_context(struct drm_i915_gem_request *req) |
823 | int i915_switch_context(struct drm_i915_gem_request *req) |
820 | { |
824 | { |
821 | struct intel_engine_cs *ring = req->ring; |
825 | struct intel_engine_cs *ring = req->ring; |
822 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
826 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
823 | 827 | ||
824 | WARN_ON(i915.enable_execlists); |
828 | WARN_ON(i915.enable_execlists); |
825 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
829 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
826 | 830 | ||
827 | if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */ |
831 | if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */ |
828 | if (req->ctx != ring->last_context) { |
832 | if (req->ctx != ring->last_context) { |
829 | i915_gem_context_reference(req->ctx); |
833 | i915_gem_context_reference(req->ctx); |
830 | if (ring->last_context) |
834 | if (ring->last_context) |
831 | i915_gem_context_unreference(ring->last_context); |
835 | i915_gem_context_unreference(ring->last_context); |
832 | ring->last_context = req->ctx; |
836 | ring->last_context = req->ctx; |
833 | } |
837 | } |
834 | return 0; |
838 | return 0; |
835 | } |
839 | } |
836 | 840 | ||
837 | return do_switch(req); |
841 | return do_switch(req); |
838 | } |
842 | } |
839 | 843 | ||
840 | static bool contexts_enabled(struct drm_device *dev) |
844 | static bool contexts_enabled(struct drm_device *dev) |
841 | { |
845 | { |
842 | return i915.enable_execlists || to_i915(dev)->hw_context_size; |
846 | return i915.enable_execlists || to_i915(dev)->hw_context_size; |
843 | } |
847 | } |
844 | 848 | ||
845 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
849 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
846 | struct drm_file *file) |
850 | struct drm_file *file) |
847 | { |
851 | { |
848 | struct drm_i915_gem_context_create *args = data; |
852 | struct drm_i915_gem_context_create *args = data; |
849 | struct drm_i915_file_private *file_priv = file->driver_priv; |
853 | struct drm_i915_file_private *file_priv = file->driver_priv; |
850 | struct intel_context *ctx; |
854 | struct intel_context *ctx; |
851 | int ret; |
855 | int ret; |
852 | 856 | ||
853 | if (!contexts_enabled(dev)) |
857 | if (!contexts_enabled(dev)) |
854 | return -ENODEV; |
858 | return -ENODEV; |
855 | 859 | ||
856 | ret = i915_mutex_lock_interruptible(dev); |
860 | ret = i915_mutex_lock_interruptible(dev); |
857 | if (ret) |
861 | if (ret) |
858 | return ret; |
862 | return ret; |
859 | 863 | ||
860 | ctx = i915_gem_create_context(dev, file_priv); |
864 | ctx = i915_gem_create_context(dev, file_priv); |
861 | mutex_unlock(&dev->struct_mutex); |
865 | mutex_unlock(&dev->struct_mutex); |
862 | if (IS_ERR(ctx)) |
866 | if (IS_ERR(ctx)) |
863 | return PTR_ERR(ctx); |
867 | return PTR_ERR(ctx); |
864 | 868 | ||
865 | args->ctx_id = ctx->user_handle; |
869 | args->ctx_id = ctx->user_handle; |
866 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); |
870 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); |
867 | 871 | ||
868 | return 0; |
872 | return 0; |
869 | } |
873 | } |
870 | 874 | ||
871 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
875 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
872 | struct drm_file *file) |
876 | struct drm_file *file) |
873 | { |
877 | { |
874 | struct drm_i915_gem_context_destroy *args = data; |
878 | struct drm_i915_gem_context_destroy *args = data; |
875 | struct drm_i915_file_private *file_priv = file->driver_priv; |
879 | struct drm_i915_file_private *file_priv = file->driver_priv; |
876 | struct intel_context *ctx; |
880 | struct intel_context *ctx; |
877 | int ret; |
881 | int ret; |
878 | 882 | ||
879 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
883 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
880 | return -ENOENT; |
884 | return -ENOENT; |
881 | 885 | ||
882 | ret = i915_mutex_lock_interruptible(dev); |
886 | ret = i915_mutex_lock_interruptible(dev); |
883 | if (ret) |
887 | if (ret) |
884 | return ret; |
888 | return ret; |
885 | 889 | ||
886 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
890 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
887 | if (IS_ERR(ctx)) { |
891 | if (IS_ERR(ctx)) { |
888 | mutex_unlock(&dev->struct_mutex); |
892 | mutex_unlock(&dev->struct_mutex); |
889 | return PTR_ERR(ctx); |
893 | return PTR_ERR(ctx); |
890 | } |
894 | } |
891 | 895 | ||
892 | idr_remove(&ctx->file_priv->context_idr, ctx->user_handle); |
896 | idr_remove(&ctx->file_priv->context_idr, ctx->user_handle); |
893 | i915_gem_context_unreference(ctx); |
897 | i915_gem_context_unreference(ctx); |
894 | mutex_unlock(&dev->struct_mutex); |
898 | mutex_unlock(&dev->struct_mutex); |
895 | 899 | ||
896 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); |
900 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); |
897 | return 0; |
901 | return 0; |
898 | } |
902 | } |
899 | 903 | ||
900 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
904 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
901 | struct drm_file *file) |
905 | struct drm_file *file) |
902 | { |
906 | { |
903 | struct drm_i915_file_private *file_priv = file->driver_priv; |
907 | struct drm_i915_file_private *file_priv = file->driver_priv; |
904 | struct drm_i915_gem_context_param *args = data; |
908 | struct drm_i915_gem_context_param *args = data; |
905 | struct intel_context *ctx; |
909 | struct intel_context *ctx; |
906 | int ret; |
910 | int ret; |
907 | 911 | ||
908 | ret = i915_mutex_lock_interruptible(dev); |
912 | ret = i915_mutex_lock_interruptible(dev); |
909 | if (ret) |
913 | if (ret) |
910 | return ret; |
914 | return ret; |
911 | 915 | ||
912 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
916 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
913 | if (IS_ERR(ctx)) { |
917 | if (IS_ERR(ctx)) { |
914 | mutex_unlock(&dev->struct_mutex); |
918 | mutex_unlock(&dev->struct_mutex); |
915 | return PTR_ERR(ctx); |
919 | return PTR_ERR(ctx); |
916 | } |
920 | } |
917 | 921 | ||
918 | args->size = 0; |
922 | args->size = 0; |
919 | switch (args->param) { |
923 | switch (args->param) { |
920 | case I915_CONTEXT_PARAM_BAN_PERIOD: |
924 | case I915_CONTEXT_PARAM_BAN_PERIOD: |
921 | args->value = ctx->hang_stats.ban_period_seconds; |
925 | args->value = ctx->hang_stats.ban_period_seconds; |
922 | break; |
926 | break; |
923 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
927 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
924 | args->value = ctx->flags & CONTEXT_NO_ZEROMAP; |
928 | args->value = ctx->flags & CONTEXT_NO_ZEROMAP; |
925 | break; |
929 | break; |
926 | default: |
930 | default: |
927 | ret = -EINVAL; |
931 | ret = -EINVAL; |
928 | break; |
932 | break; |
929 | } |
933 | } |
930 | mutex_unlock(&dev->struct_mutex); |
934 | mutex_unlock(&dev->struct_mutex); |
931 | 935 | ||
932 | return ret; |
936 | return ret; |
933 | } |
937 | } |
934 | 938 | ||
935 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, |
939 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, |
936 | struct drm_file *file) |
940 | struct drm_file *file) |
937 | { |
941 | { |
938 | struct drm_i915_file_private *file_priv = file->driver_priv; |
942 | struct drm_i915_file_private *file_priv = file->driver_priv; |
939 | struct drm_i915_gem_context_param *args = data; |
943 | struct drm_i915_gem_context_param *args = data; |
940 | struct intel_context *ctx; |
944 | struct intel_context *ctx; |
941 | int ret; |
945 | int ret; |
942 | 946 | ||
943 | ret = i915_mutex_lock_interruptible(dev); |
947 | ret = i915_mutex_lock_interruptible(dev); |
944 | if (ret) |
948 | if (ret) |
945 | return ret; |
949 | return ret; |
946 | 950 | ||
947 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
951 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
948 | if (IS_ERR(ctx)) { |
952 | if (IS_ERR(ctx)) { |
949 | mutex_unlock(&dev->struct_mutex); |
953 | mutex_unlock(&dev->struct_mutex); |
950 | return PTR_ERR(ctx); |
954 | return PTR_ERR(ctx); |
951 | } |
955 | } |
952 | 956 | ||
953 | switch (args->param) { |
957 | switch (args->param) { |
954 | case I915_CONTEXT_PARAM_BAN_PERIOD: |
958 | case I915_CONTEXT_PARAM_BAN_PERIOD: |
955 | if (args->size) |
959 | if (args->size) |
956 | ret = -EINVAL; |
960 | ret = -EINVAL; |
957 | else if (args->value < ctx->hang_stats.ban_period_seconds) |
961 | else if (args->value < ctx->hang_stats.ban_period_seconds) |
958 | ret = -EPERM; |
962 | ret = -EPERM; |
959 | else |
963 | else |
960 | ctx->hang_stats.ban_period_seconds = args->value; |
964 | ctx->hang_stats.ban_period_seconds = args->value; |
961 | break; |
965 | break; |
962 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
966 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
963 | if (args->size) { |
967 | if (args->size) { |
964 | ret = -EINVAL; |
968 | ret = -EINVAL; |
965 | } else { |
969 | } else { |
966 | ctx->flags &= ~CONTEXT_NO_ZEROMAP; |
970 | ctx->flags &= ~CONTEXT_NO_ZEROMAP; |
967 | ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0; |
971 | ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0; |
968 | } |
972 | } |
969 | break; |
973 | break; |
970 | default: |
974 | default: |
971 | ret = -EINVAL; |
975 | ret = -EINVAL; |
972 | break; |
976 | break; |
973 | } |
977 | } |
974 | mutex_unlock(&dev->struct_mutex); |
978 | mutex_unlock(&dev->struct_mutex); |
975 | 979 | ||
976 | return ret; |
980 | return ret; |
977 | }> |
981 | }> |
978 | > |
982 | > |
979 | > |
983 | > |
980 | > |
984 | > |
981 | >>>>>>20))><20))>>><>>10) |
985 | >>>>>>20))><20))>>><>>10) |
982 | #define><10) |
986 | #define><10) |
983 | #define> |
987 | #define> |