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	struct drm_i915_gem_object *obj;

	struct drm_i915_gem_object *obj;

	int ret;

	int ret;

	u32 handle;

	u32 handle;

	size = roundup(size, PAGE_SIZE);

		return -EINVAL;

	/* Allocate the new object */

	/* Allocate the new object */

	obj = i915_gem_alloc_object(dev, size);

	obj = i915_gem_alloc_object(dev, size);

	i915_gem_info_add_obj(dev_priv, size);

	i915_gem_info_add_obj(dev_priv, size);

	obj->base.write_domain = I915_GEM_DOMAIN_CPU;

	obj->base.write_domain = I915_GEM_DOMAIN_CPU;

	if (IS_GEN6(dev)) {

	if (IS_GEN6(dev) || IS_GEN7(dev)) {

		/* On Gen6, we can have the GPU use the LLC (the CPU

		/* On Gen6, we can have the GPU use the LLC (the CPU

		 * cache) for about a 10% performance improvement

		 * cache) for about a 10% performance improvement

		 * compared to uncached.  Graphics requests other than

		 * compared to uncached.  Graphics requests other than

    INIT_LIST_HEAD(&dev_priv->mm.fence_list);

    INIT_LIST_HEAD(&dev_priv->mm.fence_list);

    INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);

    INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);

    INIT_LIST_HEAD(&dev_priv->mm.gtt_list);

    INIT_LIST_HEAD(&dev_priv->mm.gtt_list);

    for (i = 0; i < I915_NUM_RINGS; i++)

    for (i = 0; i < I915_NUM_RINGS; i++)

        init_ring_lists(&dev_priv->ring[i]);

        init_ring_lists(&dev_priv->ring[i]);

        INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);

        INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);

//    INIT_DELAYED_WORK(&dev_priv->mm.retire_work,

//    INIT_DELAYED_WORK(&dev_priv->mm.retire_work,

//              i915_gem_retire_work_handler);

//              i915_gem_retire_work_handler);

//    init_completion(&dev_priv->error_completion);

//    init_completion(&dev_priv->error_completion);