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Rev 6935 | Rev 6937 | ||
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Line 31... | Line 31... | ||
31 | #define _I915_DRV_H_ |
31 | #define _I915_DRV_H_ |
Line 32... | Line 32... | ||
32 | 32 | ||
33 | #include |
33 | #include |
Line -... | Line 34... | ||
- | 34 | #include |
|
34 | #include |
35 | |
35 | 36 | #include |
|
36 | #include "i915_reg.h" |
37 | #include "i915_reg.h" |
37 | #include "intel_bios.h" |
38 | #include "intel_bios.h" |
38 | #include "intel_ringbuffer.h" |
39 | #include "intel_ringbuffer.h" |
Line 43... | Line 44... | ||
43 | #include |
44 | #include |
44 | #include |
45 | #include |
45 | #include |
46 | #include |
46 | #include |
47 | #include |
47 | #include |
48 | #include |
48 | //#include |
49 | #include |
49 | #include |
50 | #include |
50 | #include |
51 | #include |
51 | #include "intel_guc.h" |
52 | #include "intel_guc.h" |
Line 52... | Line 53... | ||
52 | 53 | ||
Line 53... | Line -... | ||
53 | #include |
- | |
54 | - | ||
55 | #define ioread32(addr) readl(addr) |
- | |
56 | static inline u8 inb(u16 port) |
- | |
57 | { |
- | |
58 | u8 v; |
- | |
59 | asm volatile("inb %1,%0" : "=a" (v) : "dN" (port)); |
- | |
60 | return v; |
- | |
61 | } |
- | |
62 | - | ||
63 | static inline void outb(u8 v, u16 port) |
- | |
64 | { |
- | |
65 | asm volatile("outb %0,%1" : : "a" (v), "dN" (port)); |
- | |
66 | } |
- | |
67 | 54 | #include |
|
68 | 55 | ||
Line 69... | Line 56... | ||
69 | /* General customization: |
56 | /* General customization: |
70 | */ |
57 | */ |
71 | 58 | ||
Line 72... | Line 59... | ||
72 | #define DRIVER_NAME "i915" |
59 | #define DRIVER_NAME "i915" |
73 | #define DRIVER_DESC "Intel Graphics" |
60 | #define DRIVER_DESC "Intel Graphics" |
74 | #define DRIVER_DATE "20151010" |
61 | #define DRIVER_DATE "20151218" |
75 | 62 | ||
Line 192... | Line 179... | ||
192 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, |
179 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, |
193 | POWER_DOMAIN_TRANSCODER_A, |
180 | POWER_DOMAIN_TRANSCODER_A, |
194 | POWER_DOMAIN_TRANSCODER_B, |
181 | POWER_DOMAIN_TRANSCODER_B, |
195 | POWER_DOMAIN_TRANSCODER_C, |
182 | POWER_DOMAIN_TRANSCODER_C, |
196 | POWER_DOMAIN_TRANSCODER_EDP, |
183 | POWER_DOMAIN_TRANSCODER_EDP, |
197 | POWER_DOMAIN_PORT_DDI_A_2_LANES, |
- | |
198 | POWER_DOMAIN_PORT_DDI_A_4_LANES, |
184 | POWER_DOMAIN_PORT_DDI_A_LANES, |
199 | POWER_DOMAIN_PORT_DDI_B_2_LANES, |
- | |
200 | POWER_DOMAIN_PORT_DDI_B_4_LANES, |
185 | POWER_DOMAIN_PORT_DDI_B_LANES, |
201 | POWER_DOMAIN_PORT_DDI_C_2_LANES, |
- | |
202 | POWER_DOMAIN_PORT_DDI_C_4_LANES, |
186 | POWER_DOMAIN_PORT_DDI_C_LANES, |
203 | POWER_DOMAIN_PORT_DDI_D_2_LANES, |
- | |
204 | POWER_DOMAIN_PORT_DDI_D_4_LANES, |
187 | POWER_DOMAIN_PORT_DDI_D_LANES, |
205 | POWER_DOMAIN_PORT_DDI_E_2_LANES, |
188 | POWER_DOMAIN_PORT_DDI_E_LANES, |
206 | POWER_DOMAIN_PORT_DSI, |
189 | POWER_DOMAIN_PORT_DSI, |
207 | POWER_DOMAIN_PORT_CRT, |
190 | POWER_DOMAIN_PORT_CRT, |
208 | POWER_DOMAIN_PORT_OTHER, |
191 | POWER_DOMAIN_PORT_OTHER, |
209 | POWER_DOMAIN_VGA, |
192 | POWER_DOMAIN_VGA, |
210 | POWER_DOMAIN_AUDIO, |
193 | POWER_DOMAIN_AUDIO, |
Line 212... | Line 195... | ||
212 | POWER_DOMAIN_AUX_A, |
195 | POWER_DOMAIN_AUX_A, |
213 | POWER_DOMAIN_AUX_B, |
196 | POWER_DOMAIN_AUX_B, |
214 | POWER_DOMAIN_AUX_C, |
197 | POWER_DOMAIN_AUX_C, |
215 | POWER_DOMAIN_AUX_D, |
198 | POWER_DOMAIN_AUX_D, |
216 | POWER_DOMAIN_GMBUS, |
199 | POWER_DOMAIN_GMBUS, |
- | 200 | POWER_DOMAIN_MODESET, |
|
217 | POWER_DOMAIN_INIT, |
201 | POWER_DOMAIN_INIT, |
Line 218... | Line 202... | ||
218 | 202 | ||
219 | POWER_DOMAIN_NUM, |
203 | POWER_DOMAIN_NUM, |
Line 301... | Line 285... | ||
301 | 285 | ||
302 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ |
286 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ |
303 | list_for_each_entry(intel_plane, \ |
287 | list_for_each_entry(intel_plane, \ |
304 | &(dev)->mode_config.plane_list, \ |
288 | &(dev)->mode_config.plane_list, \ |
305 | base.head) \ |
289 | base.head) \ |
Line 306... | Line 290... | ||
306 | if ((intel_plane)->pipe == (intel_crtc)->pipe) |
290 | for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe) |
307 | 291 | ||
Line 308... | Line 292... | ||
308 | #define for_each_intel_crtc(dev, intel_crtc) \ |
292 | #define for_each_intel_crtc(dev, intel_crtc) \ |
Line 318... | Line 302... | ||
318 | &dev->mode_config.connector_list, \ |
302 | &dev->mode_config.connector_list, \ |
319 | base.head) |
303 | base.head) |
Line 320... | Line 304... | ||
320 | 304 | ||
321 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
305 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
322 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ |
306 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ |
Line 323... | Line 307... | ||
323 | if ((intel_encoder)->base.crtc == (__crtc)) |
307 | for_each_if ((intel_encoder)->base.crtc == (__crtc)) |
324 | 308 | ||
325 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
309 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
Line 326... | Line 310... | ||
326 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ |
310 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ |
327 | if ((intel_connector)->base.encoder == (__encoder)) |
311 | for_each_if ((intel_connector)->base.encoder == (__encoder)) |
328 | 312 | ||
Line 329... | Line 313... | ||
329 | #define for_each_power_domain(domain, mask) \ |
313 | #define for_each_power_domain(domain, mask) \ |
330 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ |
314 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ |
331 | if ((1 << (domain)) & (mask)) |
315 | for_each_if ((1 << (domain)) & (mask)) |
Line 472... | Line 456... | ||
472 | struct opregion_acpi *acpi; |
456 | struct opregion_acpi *acpi; |
473 | struct opregion_swsci *swsci; |
457 | struct opregion_swsci *swsci; |
474 | u32 swsci_gbda_sub_functions; |
458 | u32 swsci_gbda_sub_functions; |
475 | u32 swsci_sbcb_sub_functions; |
459 | u32 swsci_sbcb_sub_functions; |
476 | struct opregion_asle *asle; |
460 | struct opregion_asle *asle; |
477 | void *vbt; |
461 | void *rvda; |
- | 462 | const void *vbt; |
|
- | 463 | u32 vbt_size; |
|
478 | u32 *lid_state; |
464 | u32 *lid_state; |
479 | struct work_struct asle_work; |
465 | struct work_struct asle_work; |
480 | }; |
466 | }; |
481 | #define OPREGION_SIZE (8*1024) |
467 | #define OPREGION_SIZE (8*1024) |
Line 643... | Line 629... | ||
643 | bool (*find_dpll)(const struct intel_limit *limit, |
629 | bool (*find_dpll)(const struct intel_limit *limit, |
644 | struct intel_crtc_state *crtc_state, |
630 | struct intel_crtc_state *crtc_state, |
645 | int target, int refclk, |
631 | int target, int refclk, |
646 | struct dpll *match_clock, |
632 | struct dpll *match_clock, |
647 | struct dpll *best_clock); |
633 | struct dpll *best_clock); |
- | 634 | int (*compute_pipe_wm)(struct intel_crtc *crtc, |
|
- | 635 | struct drm_atomic_state *state); |
|
648 | void (*update_wm)(struct drm_crtc *crtc); |
636 | void (*update_wm)(struct drm_crtc *crtc); |
649 | void (*update_sprite_wm)(struct drm_plane *plane, |
- | |
650 | struct drm_crtc *crtc, |
- | |
651 | uint32_t sprite_width, uint32_t sprite_height, |
- | |
652 | int pixel_size, bool enable, bool scaled); |
- | |
653 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
637 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
654 | void (*modeset_commit_cdclk)(struct drm_atomic_state *state); |
638 | void (*modeset_commit_cdclk)(struct drm_atomic_state *state); |
655 | /* Returns the active state of the crtc, and if the crtc is active, |
639 | /* Returns the active state of the crtc, and if the crtc is active, |
656 | * fills out the pipe-config with the hw state. */ |
640 | * fills out the pipe-config with the hw state. */ |
657 | bool (*get_pipe_config)(struct intel_crtc *, |
641 | bool (*get_pipe_config)(struct intel_crtc *, |
Line 705... | Line 689... | ||
705 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
689 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
706 | enum forcewake_domains domains); |
690 | enum forcewake_domains domains); |
707 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
691 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
708 | enum forcewake_domains domains); |
692 | enum forcewake_domains domains); |
Line 709... | Line 693... | ||
709 | 693 | ||
710 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
694 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); |
711 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
695 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); |
712 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
696 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); |
Line 713... | Line 697... | ||
713 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
697 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); |
714 | 698 | ||
715 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, |
699 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r, |
716 | uint8_t val, bool trace); |
700 | uint8_t val, bool trace); |
717 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, |
701 | void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r, |
718 | uint16_t val, bool trace); |
702 | uint16_t val, bool trace); |
719 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, |
703 | void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r, |
720 | uint32_t val, bool trace); |
704 | uint32_t val, bool trace); |
721 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, |
705 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r, |
Line 722... | Line 706... | ||
722 | uint64_t val, bool trace); |
706 | uint64_t val, bool trace); |
723 | }; |
707 | }; |
Line 733... | Line 717... | ||
733 | struct intel_uncore_forcewake_domain { |
717 | struct intel_uncore_forcewake_domain { |
734 | struct drm_i915_private *i915; |
718 | struct drm_i915_private *i915; |
735 | enum forcewake_domain_id id; |
719 | enum forcewake_domain_id id; |
736 | unsigned wake_count; |
720 | unsigned wake_count; |
737 | struct timer_list timer; |
721 | struct timer_list timer; |
738 | u32 reg_set; |
722 | i915_reg_t reg_set; |
739 | u32 val_set; |
723 | u32 val_set; |
740 | u32 val_clear; |
724 | u32 val_clear; |
741 | u32 reg_ack; |
725 | i915_reg_t reg_ack; |
742 | u32 reg_post; |
726 | i915_reg_t reg_post; |
743 | u32 val_reset; |
727 | u32 val_reset; |
744 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
728 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
745 | }; |
729 | }; |
Line 746... | Line 730... | ||
746 | 730 | ||
747 | /* Iterate over initialised fw domains */ |
731 | /* Iterate over initialised fw domains */ |
748 | #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \ |
732 | #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \ |
749 | for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ |
733 | for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ |
750 | (i__) < FW_DOMAIN_ID_COUNT; \ |
734 | (i__) < FW_DOMAIN_ID_COUNT; \ |
751 | (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \ |
735 | (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \ |
Line 752... | Line 736... | ||
752 | if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__))) |
736 | for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__))) |
753 | 737 | ||
Line 754... | Line 738... | ||
754 | #define for_each_fw_domain(domain__, dev_priv__, i__) \ |
738 | #define for_each_fw_domain(domain__, dev_priv__, i__) \ |
755 | for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) |
739 | for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) |
756 | 740 | ||
757 | enum csr_state { |
- | |
758 | FW_UNINITIALIZED = 0, |
- | |
Line 759... | Line 741... | ||
759 | FW_LOADED, |
741 | #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) |
- | 742 | #define CSR_VERSION_MAJOR(version) ((version) >> 16) |
|
760 | FW_FAILED |
743 | #define CSR_VERSION_MINOR(version) ((version) & 0xffff) |
761 | }; |
744 | |
762 | 745 | struct intel_csr { |
|
- | 746 | struct work_struct work; |
|
763 | struct intel_csr { |
747 | const char *fw_path; |
764 | const char *fw_path; |
748 | uint32_t *dmc_payload; |
765 | uint32_t *dmc_payload; |
749 | uint32_t dmc_fw_size; |
766 | uint32_t dmc_fw_size; |
750 | uint32_t version; |
767 | uint32_t mmio_count; |
751 | uint32_t mmio_count; |
Line 768... | Line 752... | ||
768 | uint32_t mmioaddr[8]; |
752 | i915_reg_t mmioaddr[8]; |
769 | uint32_t mmiodata[8]; |
753 | uint32_t mmiodata[8]; |
770 | enum csr_state state; |
754 | uint32_t dc_state; |
Line 781... | Line 765... | ||
781 | func(is_pineview) sep \ |
765 | func(is_pineview) sep \ |
782 | func(is_broadwater) sep \ |
766 | func(is_broadwater) sep \ |
783 | func(is_crestline) sep \ |
767 | func(is_crestline) sep \ |
784 | func(is_ivybridge) sep \ |
768 | func(is_ivybridge) sep \ |
785 | func(is_valleyview) sep \ |
769 | func(is_valleyview) sep \ |
- | 770 | func(is_cherryview) sep \ |
|
786 | func(is_haswell) sep \ |
771 | func(is_haswell) sep \ |
787 | func(is_skylake) sep \ |
772 | func(is_skylake) sep \ |
- | 773 | func(is_broxton) sep \ |
|
- | 774 | func(is_kabylake) sep \ |
|
788 | func(is_preliminary) sep \ |
775 | func(is_preliminary) sep \ |
789 | func(has_fbc) sep \ |
776 | func(has_fbc) sep \ |
790 | func(has_pipe_cxsr) sep \ |
777 | func(has_pipe_cxsr) sep \ |
791 | func(has_hotplug) sep \ |
778 | func(has_hotplug) sep \ |
792 | func(cursor_needs_physical) sep \ |
779 | func(cursor_needs_physical) sep \ |
Line 918... | Line 905... | ||
918 | 905 | ||
919 | struct i915_fbc { |
906 | struct i915_fbc { |
920 | /* This is always the inner lock when overlapping with struct_mutex and |
907 | /* This is always the inner lock when overlapping with struct_mutex and |
921 | * it's the outer lock when overlapping with stolen_lock. */ |
908 | * it's the outer lock when overlapping with stolen_lock. */ |
922 | struct mutex lock; |
- | |
923 | unsigned long uncompressed_size; |
909 | struct mutex lock; |
924 | unsigned threshold; |
910 | unsigned threshold; |
925 | unsigned int fb_id; |
911 | unsigned int fb_id; |
926 | unsigned int possible_framebuffer_bits; |
912 | unsigned int possible_framebuffer_bits; |
927 | unsigned int busy_bits; |
913 | unsigned int busy_bits; |
Line 931... | Line 917... | ||
931 | struct drm_mm_node compressed_fb; |
917 | struct drm_mm_node compressed_fb; |
932 | struct drm_mm_node *compressed_llb; |
918 | struct drm_mm_node *compressed_llb; |
Line 933... | Line 919... | ||
933 | 919 | ||
Line 934... | Line -... | ||
934 | bool false_color; |
- | |
935 | - | ||
936 | /* Tracks whether the HW is actually enabled, not whether the feature is |
920 | bool false_color; |
- | 921 | ||
Line 937... | Line 922... | ||
937 | * possible. */ |
922 | bool enabled; |
938 | bool enabled; |
923 | bool active; |
939 | 924 | ||
940 | struct intel_fbc_work { |
925 | struct intel_fbc_work { |
- | 926 | bool scheduled; |
|
941 | struct delayed_work work; |
927 | struct work_struct work; |
- | 928 | struct drm_framebuffer *fb; |
|
- | 929 | unsigned long enable_jiffies; |
|
Line 942... | Line -... | ||
942 | struct intel_crtc *crtc; |
- | |
943 | struct drm_framebuffer *fb; |
- | |
944 | } *fbc_work; |
- | |
945 | - | ||
946 | enum no_fbc_reason { |
- | |
947 | FBC_OK, /* FBC is enabled */ |
- | |
948 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ |
- | |
949 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
- | |
950 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ |
- | |
951 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ |
- | |
952 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ |
- | |
953 | FBC_BAD_PLANE, /* fbc not supported on plane */ |
- | |
954 | FBC_NOT_TILED, /* buffer not tiled */ |
- | |
955 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
- | |
956 | FBC_MODULE_PARAM, |
- | |
957 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ |
- | |
958 | FBC_ROTATION, /* rotation is not supported */ |
- | |
959 | FBC_IN_DBG_MASTER, /* kernel debugger is active */ |
- | |
960 | FBC_BAD_STRIDE, /* stride is not supported */ |
- | |
961 | FBC_PIXEL_RATE, /* pixel rate is too big */ |
930 | } work; |
962 | FBC_PIXEL_FORMAT /* pixel format is invalid */ |
931 | |
963 | } no_fbc_reason; |
932 | const char *no_fbc_reason; |
964 | 933 | ||
Line 965... | Line 934... | ||
965 | bool (*fbc_enabled)(struct drm_i915_private *dev_priv); |
934 | bool (*is_active)(struct drm_i915_private *dev_priv); |
966 | void (*enable_fbc)(struct intel_crtc *crtc); |
935 | void (*activate)(struct intel_crtc *crtc); |
967 | void (*disable_fbc)(struct drm_i915_private *dev_priv); |
936 | void (*deactivate)(struct drm_i915_private *dev_priv); |
Line 1032... | Line 1001... | ||
1032 | 1001 | ||
1033 | struct intel_gmbus { |
1002 | struct intel_gmbus { |
1034 | struct i2c_adapter adapter; |
1003 | struct i2c_adapter adapter; |
1035 | u32 force_bit; |
1004 | u32 force_bit; |
1036 | u32 reg0; |
1005 | u32 reg0; |
1037 | u32 gpio_reg; |
1006 | i915_reg_t gpio_reg; |
1038 | struct i2c_algo_bit_data bit_algo; |
1007 | struct i2c_algo_bit_data bit_algo; |
1039 | struct drm_i915_private *dev_priv; |
1008 | struct drm_i915_private *dev_priv; |
Line 1040... | Line 1009... | ||
1040 | }; |
1009 | }; |
Line 1171... | Line 1140... | ||
1171 | unsigned boosts; |
1140 | unsigned boosts; |
Line 1172... | Line 1141... | ||
1172 | 1141 | ||
Line 1173... | Line 1142... | ||
1173 | struct intel_rps_client semaphores, mmioflips; |
1142 | struct intel_rps_client semaphores, mmioflips; |
1174 | 1143 | ||
Line 1175... | Line 1144... | ||
1175 | /* manual wa residency calculations */ |
1144 | /* manual wa residency calculations */ |
1176 | struct intel_rps_ei ei; |
1145 | struct intel_rps_ei up_ei, down_ei; |
1177 | 1146 | ||
1178 | /* |
1147 | /* |
Line 1291... | Line 1260... | ||
1291 | unsigned long stolen_base; /* limited to low memory (32-bit) */ |
1260 | unsigned long stolen_base; /* limited to low memory (32-bit) */ |
Line 1292... | Line 1261... | ||
1292 | 1261 | ||
1293 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1262 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
Line -... | Line 1263... | ||
- | 1263 | struct i915_hw_ppgtt *aliasing_ppgtt; |
|
1294 | struct i915_hw_ppgtt *aliasing_ppgtt; |
1264 | |
1295 | 1265 | struct notifier_block oom_notifier; |
|
Line 1296... | Line 1266... | ||
1296 | /** LRU list of objects with fence regs on them. */ |
1266 | /** LRU list of objects with fence regs on them. */ |
1297 | struct list_head fence_list; |
1267 | struct list_head fence_list; |
Line 1631... | Line 1601... | ||
1631 | * case it happens. |
1601 | * case it happens. |
1632 | * |
1602 | * |
1633 | * For more, read the Documentation/power/runtime_pm.txt. |
1603 | * For more, read the Documentation/power/runtime_pm.txt. |
1634 | */ |
1604 | */ |
1635 | struct i915_runtime_pm { |
1605 | struct i915_runtime_pm { |
- | 1606 | atomic_t wakeref_count; |
|
- | 1607 | atomic_t atomic_seq; |
|
1636 | bool suspended; |
1608 | bool suspended; |
1637 | bool irqs_enabled; |
1609 | bool irqs_enabled; |
1638 | }; |
1610 | }; |
Line 1639... | Line 1611... | ||
1639 | 1611 | ||
Line 1677... | Line 1649... | ||
1677 | unsigned busy_bits; |
1649 | unsigned busy_bits; |
1678 | unsigned flip_bits; |
1650 | unsigned flip_bits; |
1679 | }; |
1651 | }; |
Line 1680... | Line 1652... | ||
1680 | 1652 | ||
1681 | struct i915_wa_reg { |
1653 | struct i915_wa_reg { |
1682 | u32 addr; |
1654 | i915_reg_t addr; |
1683 | u32 value; |
1655 | u32 value; |
1684 | /* bitmask representing WA bits */ |
1656 | /* bitmask representing WA bits */ |
1685 | u32 mask; |
1657 | u32 mask; |
Line 1706... | Line 1678... | ||
1706 | struct drm_i915_gem_object *batch_obj; |
1678 | struct drm_i915_gem_object *batch_obj; |
1707 | struct intel_context *ctx; |
1679 | struct intel_context *ctx; |
1708 | struct drm_i915_gem_request *request; |
1680 | struct drm_i915_gem_request *request; |
1709 | }; |
1681 | }; |
Line -... | Line 1682... | ||
- | 1682 | ||
- | 1683 | /* used in computing the new watermarks state */ |
|
- | 1684 | struct intel_wm_config { |
|
- | 1685 | unsigned int num_pipes_active; |
|
- | 1686 | bool sprites_enabled; |
|
- | 1687 | bool sprites_scaled; |
|
- | 1688 | }; |
|
1710 | 1689 | ||
1711 | struct drm_i915_private { |
1690 | struct drm_i915_private { |
1712 | struct drm_device *dev; |
1691 | struct drm_device *dev; |
1713 | struct kmem_cache *objects; |
1692 | struct kmem_cache *objects; |
1714 | struct kmem_cache *vmas; |
1693 | struct kmem_cache *vmas; |
Line 1726... | Line 1705... | ||
1726 | 1705 | ||
Line 1727... | Line 1706... | ||
1727 | struct intel_guc guc; |
1706 | struct intel_guc guc; |
Line 1728... | Line -... | ||
1728 | - | ||
1729 | struct intel_csr csr; |
- | |
1730 | - | ||
1731 | /* Display CSR-related protection */ |
1707 | |
Line 1732... | Line 1708... | ||
1732 | struct mutex csr_lock; |
1708 | struct intel_csr csr; |
1733 | 1709 | ||
1734 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
1710 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
Line 1743... | Line 1719... | ||
1743 | uint32_t gpio_mmio_base; |
1719 | uint32_t gpio_mmio_base; |
Line 1744... | Line 1720... | ||
1744 | 1720 | ||
1745 | /* MMIO base address for MIPI regs */ |
1721 | /* MMIO base address for MIPI regs */ |
Line -... | Line 1722... | ||
- | 1722 | uint32_t mipi_mmio_base; |
|
- | 1723 | ||
1746 | uint32_t mipi_mmio_base; |
1724 | uint32_t psr_mmio_base; |
Line 1747... | Line 1725... | ||
1747 | 1725 | ||
1748 | wait_queue_head_t gmbus_wait_queue; |
1726 | wait_queue_head_t gmbus_wait_queue; |
1749 | 1727 | ||
Line 1906... | Line 1884... | ||
1906 | u32 fdi_rx_config; |
1884 | u32 fdi_rx_config; |
Line 1907... | Line 1885... | ||
1907 | 1885 | ||
Line 1908... | Line 1886... | ||
1908 | u32 chv_phy_control; |
1886 | u32 chv_phy_control; |
- | 1887 | ||
1909 | 1888 | u32 suspend_count; |
|
1910 | u32 suspend_count; |
1889 | bool suspended_to_idle; |
Line 1911... | Line 1890... | ||
1911 | struct i915_suspend_saved_registers regfile; |
1890 | struct i915_suspend_saved_registers regfile; |
1912 | struct vlv_s0ix_state vlv_s0ix_state; |
1891 | struct vlv_s0ix_state vlv_s0ix_state; |
Line 1928... | Line 1907... | ||
1928 | * for SKL for all 8 levels |
1907 | * for SKL for all 8 levels |
1929 | * in 1us units. |
1908 | * in 1us units. |
1930 | */ |
1909 | */ |
1931 | uint16_t skl_latency[8]; |
1910 | uint16_t skl_latency[8]; |
Line -... | Line 1911... | ||
- | 1911 | ||
- | 1912 | /* Committed wm config */ |
|
- | 1913 | struct intel_wm_config config; |
|
1932 | 1914 | ||
1933 | /* |
1915 | /* |
1934 | * The skl_wm_values structure is a bit too big for stack |
1916 | * The skl_wm_values structure is a bit too big for stack |
1935 | * allocation, so we keep the staging struct where we store |
1917 | * allocation, so we keep the staging struct where we store |
1936 | * intermediate results here instead. |
1918 | * intermediate results here instead. |
Line 1962... | Line 1944... | ||
1962 | bool edp_low_vswing; |
1944 | bool edp_low_vswing; |
Line 1963... | Line 1945... | ||
1963 | 1945 | ||
1964 | /* perform PHY state sanity checks? */ |
1946 | /* perform PHY state sanity checks? */ |
Line -... | Line 1947... | ||
- | 1947 | bool chv_phy_assert[2]; |
|
- | 1948 | ||
1965 | bool chv_phy_assert[2]; |
1949 | struct intel_encoder *dig_port_map[I915_MAX_PORTS]; |
1966 | 1950 | ||
1967 | /* |
1951 | /* |
1968 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch |
1952 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch |
1969 | * will be rejected. Instead look for a better place. |
1953 | * will be rejected. Instead look for a better place. |
Line 1986... | Line 1970... | ||
1986 | } |
1970 | } |
Line 1987... | Line 1971... | ||
1987 | 1971 | ||
1988 | /* Iterate over initialised rings */ |
1972 | /* Iterate over initialised rings */ |
1989 | #define for_each_ring(ring__, dev_priv__, i__) \ |
1973 | #define for_each_ring(ring__, dev_priv__, i__) \ |
1990 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ |
1974 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ |
Line 1991... | Line 1975... | ||
1991 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) |
1975 | for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))) |
1992 | 1976 | ||
1993 | enum hdmi_force_audio { |
1977 | enum hdmi_force_audio { |
1994 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ |
1978 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ |
Line 1998... | Line 1982... | ||
1998 | }; |
1982 | }; |
Line 1999... | Line 1983... | ||
1999 | 1983 | ||
Line 2000... | Line 1984... | ||
2000 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
1984 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
- | 1985 | ||
- | 1986 | struct drm_i915_gem_object_ops { |
|
- | 1987 | unsigned int flags; |
|
2001 | 1988 | #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1 |
|
2002 | struct drm_i915_gem_object_ops { |
1989 | |
2003 | /* Interface between the GEM object and its backing storage. |
1990 | /* Interface between the GEM object and its backing storage. |
2004 | * get_pages() is called once prior to the use of the associated set |
1991 | * get_pages() is called once prior to the use of the associated set |
2005 | * of pages before to binding them into the GTT, and put_pages() is |
1992 | * of pages before to binding them into the GTT, and put_pages() is |
Line 2013... | Line 2000... | ||
2013 | * being released or under memory pressure (where we attempt to |
2000 | * being released or under memory pressure (where we attempt to |
2014 | * reap pages for the shrinker). |
2001 | * reap pages for the shrinker). |
2015 | */ |
2002 | */ |
2016 | int (*get_pages)(struct drm_i915_gem_object *); |
2003 | int (*get_pages)(struct drm_i915_gem_object *); |
2017 | void (*put_pages)(struct drm_i915_gem_object *); |
2004 | void (*put_pages)(struct drm_i915_gem_object *); |
- | 2005 | ||
2018 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
2006 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
2019 | void (*release)(struct drm_i915_gem_object *); |
2007 | void (*release)(struct drm_i915_gem_object *); |
2020 | }; |
2008 | }; |
Line 2021... | Line 2009... | ||
2021 | 2009 | ||
Line 2156... | Line 2144... | ||
2156 | unsigned long framebuffer_references; |
2144 | unsigned long framebuffer_references; |
Line 2157... | Line 2145... | ||
2157 | 2145 | ||
2158 | /** Record of address bit 17 of each page at last unbind. */ |
2146 | /** Record of address bit 17 of each page at last unbind. */ |
Line -... | Line 2147... | ||
- | 2147 | unsigned long *bit_17; |
|
- | 2148 | ||
- | 2149 | union { |
|
- | 2150 | /** for phy allocated objects */ |
|
2159 | unsigned long *bit_17; |
2151 | struct drm_dma_handle *phys_handle; |
2160 | 2152 | ||
2161 | struct i915_gem_userptr { |
2153 | struct i915_gem_userptr { |
2162 | uintptr_t ptr; |
2154 | uintptr_t ptr; |
2163 | unsigned read_only :1; |
2155 | unsigned read_only :1; |
Line 2164... | Line 2156... | ||
2164 | unsigned workers :4; |
2156 | unsigned workers :4; |
2165 | #define I915_GEM_USERPTR_MAX_WORKERS 15 |
2157 | #define I915_GEM_USERPTR_MAX_WORKERS 15 |
2166 | 2158 | ||
2167 | struct i915_mm_struct *mm; |
2159 | struct i915_mm_struct *mm; |
2168 | struct i915_mmu_object *mmu_object; |
2160 | struct i915_mmu_object *mmu_object; |
2169 | struct work_struct *work; |
- | |
2170 | } userptr; |
- | |
2171 | 2161 | struct work_struct *work; |
|
2172 | /** for phys allocated objects */ |
2162 | } userptr; |
Line 2173... | Line 2163... | ||
2173 | struct drm_dma_handle *phys_handle; |
2163 | }; |
2174 | }; |
2164 | }; |
Line 2449... | Line 2439... | ||
2449 | }) |
2439 | }) |
2450 | #define INTEL_INFO(p) (&__I915__(p)->info) |
2440 | #define INTEL_INFO(p) (&__I915__(p)->info) |
2451 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
2441 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
2452 | #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision) |
2442 | #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision) |
Line -... | Line 2443... | ||
- | 2443 | ||
- | 2444 | #define REVID_FOREVER 0xff |
|
- | 2445 | /* |
|
- | 2446 | * Return true if revision is in range [since,until] inclusive. |
|
- | 2447 | * |
|
- | 2448 | * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. |
|
- | 2449 | */ |
|
- | 2450 | #define IS_REVID(p, since, until) \ |
|
- | 2451 | (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) |
|
2453 | 2452 | ||
2454 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2453 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2455 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) |
2454 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) |
2456 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
2455 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
2457 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
2456 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
Line 2471... | Line 2470... | ||
2471 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
2470 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
2472 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2471 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2473 | INTEL_DEVID(dev) == 0x0152 || \ |
2472 | INTEL_DEVID(dev) == 0x0152 || \ |
2474 | INTEL_DEVID(dev) == 0x015a) |
2473 | INTEL_DEVID(dev) == 0x015a) |
2475 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
2474 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
2476 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
2475 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview) |
2477 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
2476 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
2478 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
2477 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev)) |
2479 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
2478 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
2480 | #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev)) |
2479 | #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) |
- | 2480 | #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) |
|
2481 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
2481 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
2482 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
2482 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
2483 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
2483 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
2484 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
2484 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
2485 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ |
2485 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ |
Line 2503... | Line 2503... | ||
2503 | INTEL_DEVID(dev) == 0x1921 || \ |
2503 | INTEL_DEVID(dev) == 0x1921 || \ |
2504 | INTEL_DEVID(dev) == 0x1926) |
2504 | INTEL_DEVID(dev) == 0x1926) |
2505 | #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ |
2505 | #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ |
2506 | INTEL_DEVID(dev) == 0x1915 || \ |
2506 | INTEL_DEVID(dev) == 0x1915 || \ |
2507 | INTEL_DEVID(dev) == 0x191E) |
2507 | INTEL_DEVID(dev) == 0x191E) |
- | 2508 | #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \ |
|
- | 2509 | INTEL_DEVID(dev) == 0x5913 || \ |
|
- | 2510 | INTEL_DEVID(dev) == 0x5916 || \ |
|
- | 2511 | INTEL_DEVID(dev) == 0x5921 || \ |
|
- | 2512 | INTEL_DEVID(dev) == 0x5926) |
|
- | 2513 | #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \ |
|
- | 2514 | INTEL_DEVID(dev) == 0x5915 || \ |
|
- | 2515 | INTEL_DEVID(dev) == 0x591E) |
|
2508 | #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ |
2516 | #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ |
2509 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
2517 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
2510 | #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ |
2518 | #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ |
2511 | (INTEL_DEVID(dev) & 0x00F0) == 0x0030) |
2519 | (INTEL_DEVID(dev) & 0x00F0) == 0x0030) |
Line 2512... | Line 2520... | ||
2512 | 2520 | ||
Line 2513... | Line 2521... | ||
2513 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
2521 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
2514 | 2522 | ||
2515 | #define SKL_REVID_A0 (0x0) |
2523 | #define SKL_REVID_A0 0x0 |
2516 | #define SKL_REVID_B0 (0x1) |
2524 | #define SKL_REVID_B0 0x1 |
2517 | #define SKL_REVID_C0 (0x2) |
2525 | #define SKL_REVID_C0 0x2 |
2518 | #define SKL_REVID_D0 (0x3) |
2526 | #define SKL_REVID_D0 0x3 |
- | 2527 | #define SKL_REVID_E0 0x4 |
|
- | 2528 | #define SKL_REVID_F0 0x5 |
|
2519 | #define SKL_REVID_E0 (0x4) |
2529 | |
2520 | #define SKL_REVID_F0 (0x5) |
2530 | #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) |
- | 2531 | ||
2521 | 2532 | #define BXT_REVID_A0 0x0 |
|
2522 | #define BXT_REVID_A0 (0x0) |
2533 | #define BXT_REVID_A1 0x1 |
- | 2534 | #define BXT_REVID_B0 0x3 |
|
- | 2535 | #define BXT_REVID_C0 0x9 |
|
Line 2523... | Line 2536... | ||
2523 | #define BXT_REVID_B0 (0x3) |
2536 | |
2524 | #define BXT_REVID_C0 (0x9) |
2537 | #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until)) |
2525 | 2538 | ||
2526 | /* |
2539 | /* |
Line 2591... | Line 2604... | ||
2591 | 2604 | ||
2592 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
2605 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
2593 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
2606 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
2594 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2607 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2595 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ |
2608 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ |
2596 | IS_SKYLAKE(dev)) |
2609 | IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
2597 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
2610 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
- | 2611 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ |
|
2598 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ |
2612 | IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \ |
2599 | IS_SKYLAKE(dev)) |
2613 | IS_KABYLAKE(dev)) |
2600 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
2614 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
Line 2601... | Line 2615... | ||
2601 | #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) |
2615 | #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) |
Line 2602... | Line 2616... | ||
2602 | 2616 | ||
2603 | #define HAS_CSR(dev) (IS_GEN9(dev)) |
2617 | #define HAS_CSR(dev) (IS_GEN9(dev)) |
Line 2604... | Line 2618... | ||
2604 | 2618 | ||
2605 | #define HAS_GUC_UCODE(dev) (IS_GEN9(dev)) |
2619 | #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) |
Line 2606... | Line 2620... | ||
2606 | #define HAS_GUC_SCHED(dev) (IS_GEN9(dev)) |
2620 | #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) |
2607 | 2621 | ||
- | 2622 | #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ |
|
Line 2608... | Line 2623... | ||
2608 | #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ |
2623 | INTEL_INFO(dev)->gen >= 8) |
2609 | INTEL_INFO(dev)->gen >= 8) |
2624 | |
2610 | 2625 | #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \ |
|
2611 | #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \ |
2626 | !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \ |
Line 2624... | Line 2639... | ||
2624 | 2639 | ||
2625 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
2640 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
2626 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
2641 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
2627 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
2642 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
- | 2643 | #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
|
2628 | #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
2644 | #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) |
2629 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2645 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2630 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
2646 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
2631 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
2647 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
Line 2632... | Line 2648... | ||
2632 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
2648 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
- | 2649 | ||
Line 2633... | Line 2650... | ||
2633 | 2650 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \ |
|
2634 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) |
2651 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
2635 | 2652 | ||
Line 2655... | Line 2672... | ||
2655 | int semaphores; |
2672 | int semaphores; |
2656 | int lvds_channel_mode; |
2673 | int lvds_channel_mode; |
2657 | int panel_use_ssc; |
2674 | int panel_use_ssc; |
2658 | int vbt_sdvo_panel_type; |
2675 | int vbt_sdvo_panel_type; |
2659 | int enable_rc6; |
2676 | int enable_rc6; |
- | 2677 | int enable_dc; |
|
2660 | int enable_fbc; |
2678 | int enable_fbc; |
2661 | int enable_ppgtt; |
2679 | int enable_ppgtt; |
2662 | int enable_execlists; |
2680 | int enable_execlists; |
2663 | int enable_psr; |
2681 | int enable_psr; |
2664 | unsigned int preliminary_hw_support; |
2682 | unsigned int preliminary_hw_support; |
Line 2706... | Line 2724... | ||
2706 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2724 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2707 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
2725 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
2708 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
2726 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
2709 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
2727 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
2710 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
2728 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
2711 | void i915_firmware_load_error_print(const char *fw_path, int err); |
- | |
Line 2712... | Line 2729... | ||
2712 | 2729 | ||
2713 | /* intel_hotplug.c */ |
2730 | /* intel_hotplug.c */ |
2714 | void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask); |
2731 | void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask); |
2715 | void intel_hpd_init(struct drm_i915_private *dev_priv); |
2732 | void intel_hpd_init(struct drm_i915_private *dev_priv); |
Line 2763... | Line 2780... | ||
2763 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2780 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2764 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); |
2781 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); |
2765 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
2782 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
2766 | uint32_t mask, |
2783 | uint32_t mask, |
2767 | uint32_t bits); |
2784 | uint32_t bits); |
- | 2785 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
|
- | 2786 | uint32_t interrupt_mask, |
|
- | 2787 | uint32_t enabled_irq_mask); |
|
2768 | void |
2788 | static inline void |
2769 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask); |
2789 | ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) |
- | 2790 | { |
|
- | 2791 | ilk_update_display_irq(dev_priv, bits, bits); |
|
2770 | void |
2792 | } |
- | 2793 | static inline void |
|
2771 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask); |
2794 | ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) |
- | 2795 | { |
|
- | 2796 | ilk_update_display_irq(dev_priv, bits, 0); |
|
- | 2797 | } |
|
- | 2798 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, |
|
- | 2799 | enum pipe pipe, |
|
- | 2800 | uint32_t interrupt_mask, |
|
- | 2801 | uint32_t enabled_irq_mask); |
|
- | 2802 | static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, |
|
- | 2803 | enum pipe pipe, uint32_t bits) |
|
- | 2804 | { |
|
- | 2805 | bdw_update_pipe_irq(dev_priv, pipe, bits, bits); |
|
- | 2806 | } |
|
- | 2807 | static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, |
|
- | 2808 | enum pipe pipe, uint32_t bits) |
|
- | 2809 | { |
|
- | 2810 | bdw_update_pipe_irq(dev_priv, pipe, bits, 0); |
|
- | 2811 | } |
|
2772 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
2812 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
2773 | uint32_t interrupt_mask, |
2813 | uint32_t interrupt_mask, |
2774 | uint32_t enabled_irq_mask); |
2814 | uint32_t enabled_irq_mask); |
- | 2815 | static inline void |
|
2775 | #define ibx_enable_display_interrupt(dev_priv, bits) \ |
2816 | ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) |
- | 2817 | { |
|
2776 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) |
2818 | ibx_display_interrupt_update(dev_priv, bits, bits); |
- | 2819 | } |
|
- | 2820 | static inline void |
|
2777 | #define ibx_disable_display_interrupt(dev_priv, bits) \ |
2821 | ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) |
- | 2822 | { |
|
2778 | ibx_display_interrupt_update((dev_priv), (bits), 0) |
2823 | ibx_display_interrupt_update(dev_priv, bits, 0); |
- | 2824 | } |
|
- | 2825 | ||
Line 2779... | Line 2826... | ||
2779 | 2826 | ||
2780 | /* i915_gem.c */ |
2827 | /* i915_gem.c */ |
2781 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
2828 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
2782 | struct drm_file *file_priv); |
2829 | struct drm_file *file_priv); |
Line 2842... | Line 2889... | ||
2842 | #define PIN_OFFSET_BIAS (1<<3) |
2889 | #define PIN_OFFSET_BIAS (1<<3) |
2843 | #define PIN_USER (1<<4) |
2890 | #define PIN_USER (1<<4) |
2844 | #define PIN_UPDATE (1<<5) |
2891 | #define PIN_UPDATE (1<<5) |
2845 | #define PIN_ZONE_4G (1<<6) |
2892 | #define PIN_ZONE_4G (1<<6) |
2846 | #define PIN_HIGH (1<<7) |
2893 | #define PIN_HIGH (1<<7) |
- | 2894 | #define PIN_OFFSET_FIXED (1<<8) |
|
2847 | #define PIN_OFFSET_MASK (~4095) |
2895 | #define PIN_OFFSET_MASK (~4095) |
2848 | int __must_check |
2896 | int __must_check |
2849 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
2897 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
2850 | struct i915_address_space *vm, |
2898 | struct i915_address_space *vm, |
2851 | uint32_t alignment, |
2899 | uint32_t alignment, |
Line 2877... | Line 2925... | ||
2877 | static inline int __sg_page_count(struct scatterlist *sg) |
2925 | static inline int __sg_page_count(struct scatterlist *sg) |
2878 | { |
2926 | { |
2879 | return sg->length >> PAGE_SHIFT; |
2927 | return sg->length >> PAGE_SHIFT; |
2880 | } |
2928 | } |
Line -... | Line 2929... | ||
- | 2929 | ||
- | 2930 | struct page * |
|
- | 2931 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n); |
|
2881 | 2932 | ||
2882 | static inline struct page * |
2933 | static inline struct page * |
2883 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
2934 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
2884 | { |
2935 | { |
2885 | if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) |
2936 | if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) |
Line 3016... | Line 3067... | ||
3016 | int __must_check |
3067 | int __must_check |
3017 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
3068 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
3018 | int __must_check |
3069 | int __must_check |
3019 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3070 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3020 | u32 alignment, |
3071 | u32 alignment, |
3021 | struct intel_engine_cs *pipelined, |
- | |
3022 | struct drm_i915_gem_request **pipelined_request, |
- | |
3023 | const struct i915_ggtt_view *view); |
3072 | const struct i915_ggtt_view *view); |
3024 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
3073 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
3025 | const struct i915_ggtt_view *view); |
3074 | const struct i915_ggtt_view *view); |
3026 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
3075 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
3027 | int align); |
3076 | int align); |
Line 3192... | Line 3241... | ||
3192 | unsigned alignment, |
3241 | unsigned alignment, |
3193 | unsigned cache_level, |
3242 | unsigned cache_level, |
3194 | unsigned long start, |
3243 | unsigned long start, |
3195 | unsigned long end, |
3244 | unsigned long end, |
3196 | unsigned flags); |
3245 | unsigned flags); |
- | 3246 | int __must_check i915_gem_evict_for_vma(struct i915_vma *target); |
|
3197 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
3247 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
Line 3198... | Line 3248... | ||
3198 | 3248 | ||
3199 | /* belongs in i915_gem_gtt.h */ |
3249 | /* belongs in i915_gem_gtt.h */ |
3200 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
3250 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
Line 3321... | Line 3371... | ||
3321 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
3371 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
3322 | } |
3372 | } |
3323 | extern void intel_i2c_reset(struct drm_device *dev); |
3373 | extern void intel_i2c_reset(struct drm_device *dev); |
Line 3324... | Line 3374... | ||
3324 | 3374 | ||
3325 | /* intel_bios.c */ |
3375 | /* intel_bios.c */ |
- | 3376 | int intel_bios_init(struct drm_i915_private *dev_priv); |
|
Line 3326... | Line 3377... | ||
3326 | bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); |
3377 | bool intel_bios_is_valid_vbt(const void *buf, size_t size); |
3327 | 3378 | ||
3328 | /* intel_opregion.c */ |
3379 | /* intel_opregion.c */ |
3329 | #ifdef CONFIG_ACPI |
3380 | #ifdef CONFIG_ACPI |
Line 3375... | Line 3426... | ||
3375 | extern void intel_init_pch_refclk(struct drm_device *dev); |
3426 | extern void intel_init_pch_refclk(struct drm_device *dev); |
3376 | extern void intel_set_rps(struct drm_device *dev, u8 val); |
3427 | extern void intel_set_rps(struct drm_device *dev, u8 val); |
3377 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3428 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3378 | bool enable); |
3429 | bool enable); |
3379 | extern void intel_detect_pch(struct drm_device *dev); |
3430 | extern void intel_detect_pch(struct drm_device *dev); |
3380 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); |
- | |
3381 | extern int intel_enable_rc6(const struct drm_device *dev); |
3431 | extern int intel_enable_rc6(const struct drm_device *dev); |
Line 3382... | Line 3432... | ||
3382 | 3432 | ||
3383 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
3433 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
3384 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3434 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
Line 3458... | Line 3508... | ||
3458 | (u64)upper << 32 | lower; }) |
3508 | (u64)upper << 32 | lower; }) |
Line 3459... | Line 3509... | ||
3459 | 3509 | ||
3460 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3510 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
Line -... | Line 3511... | ||
- | 3511 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
|
- | 3512 | ||
- | 3513 | #define __raw_read(x, s) \ |
|
- | 3514 | static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \ |
|
- | 3515 | i915_reg_t reg) \ |
|
- | 3516 | { \ |
|
- | 3517 | return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
|
- | 3518 | } |
|
- | 3519 | ||
- | 3520 | #define __raw_write(x, s) \ |
|
- | 3521 | static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \ |
|
- | 3522 | i915_reg_t reg, uint##x##_t val) \ |
|
- | 3523 | { \ |
|
- | 3524 | write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
|
- | 3525 | } |
|
- | 3526 | __raw_read(8, b) |
|
- | 3527 | __raw_read(16, w) |
|
- | 3528 | __raw_read(32, l) |
|
- | 3529 | __raw_read(64, q) |
|
- | 3530 | ||
- | 3531 | __raw_write(8, b) |
|
- | 3532 | __raw_write(16, w) |
|
- | 3533 | __raw_write(32, l) |
|
- | 3534 | __raw_write(64, q) |
|
- | 3535 | ||
- | 3536 | #undef __raw_read |
|
3461 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
3537 | #undef __raw_write |
3462 | 3538 | ||
3463 | /* These are untraced mmio-accessors that are only valid to be used inside |
3539 | /* These are untraced mmio-accessors that are only valid to be used inside |
3464 | * criticial sections inside IRQ handlers where forcewake is explicitly |
3540 | * criticial sections inside IRQ handlers where forcewake is explicitly |
3465 | * controlled. |
3541 | * controlled. |
3466 | * Think twice, and think again, before using these. |
3542 | * Think twice, and think again, before using these. |
3467 | * Note: Should only be used between intel_uncore_forcewake_irqlock() and |
3543 | * Note: Should only be used between intel_uncore_forcewake_irqlock() and |
3468 | * intel_uncore_forcewake_irqunlock(). |
3544 | * intel_uncore_forcewake_irqunlock(). |
3469 | */ |
3545 | */ |
3470 | #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__)) |
3546 | #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) |
Line 3471... | Line 3547... | ||
3471 | #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__)) |
3547 | #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) |
3472 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) |
3548 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) |
3473 | 3549 | ||
3474 | /* "Broadcast RGB" property */ |
3550 | /* "Broadcast RGB" property */ |
Line 3475... | Line 3551... | ||
3475 | #define INTEL_BROADCAST_RGB_AUTO 0 |
3551 | #define INTEL_BROADCAST_RGB_AUTO 0 |
3476 | #define INTEL_BROADCAST_RGB_FULL 1 |
3552 | #define INTEL_BROADCAST_RGB_FULL 1 |
3477 | #define INTEL_BROADCAST_RGB_LIMITED 2 |
3553 | #define INTEL_BROADCAST_RGB_LIMITED 2 |
3478 | 3554 | ||
3479 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
3555 | static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev) |
3480 | { |
3556 | { |
3481 | if (IS_VALLEYVIEW(dev)) |
3557 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
3482 | return VLV_VGACNTRL; |
3558 | return VLV_VGACNTRL; |
Line 3541... | Line 3617... | ||
3541 | { |
3617 | { |
3542 | if (ring->trace_irq_req == NULL && ring->irq_get(ring)) |
3618 | if (ring->trace_irq_req == NULL && ring->irq_get(ring)) |
3543 | i915_gem_request_assign(&ring->trace_irq_req, req); |
3619 | i915_gem_request_assign(&ring->trace_irq_req, req); |
3544 | } |
3620 | } |
Line -... | Line 3621... | ||
- | 3621 | ||
- | 3622 | #include "intel_drv.h" |
|
3545 | 3623 |