WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_drv.h

 	PLANE_B,
 	PLANE_C,
 };
 #define plane_name(p) ((p) + 'A')
+#define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
 enum port {
 	PORT_A = 0,
 	PORT_B,
 	PORT_C,
 	PORT_D,
 	PORT_E,
 	I915_MAX_PORTS
 };
+#define port_name(p) ((p) + 'A')
+enum intel_display_power_domain {
+	POWER_DOMAIN_PIPE_A,
+	POWER_DOMAIN_PIPE_B,
+	POWER_DOMAIN_PIPE_C,
+	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
+	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
+	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
+	POWER_DOMAIN_TRANSCODER_A,
+	POWER_DOMAIN_TRANSCODER_B,
+	POWER_DOMAIN_TRANSCODER_C,
+	POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF,
+};
+#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
+#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
+		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
-#define port_name(p) ((p) + 'A')
+#define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
 enum hpd_pin {
 	HPD_NONE = 0,
 	HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
+		if ((intel_encoder)->base.crtc == (__crtc))
+struct drm_i915_private;
+enum intel_dpll_id {
+	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
+	/* real shared dpll ids must be >= 0 */
+	DPLL_ID_PCH_PLL_A,
+	DPLL_ID_PCH_PLL_B,
+};
+#define I915_NUM_PLLS 2
+struct intel_dpll_hw_state {
+	uint32_t dpll;
+	uint32_t dpll_md;
+	uint32_t fp0;
+	uint32_t fp1;
-		if ((intel_encoder)->base.crtc == (__crtc))
+};
-struct intel_pch_pll {
+struct intel_shared_dpll {
 	int refcount; /* count of number of CRTCs sharing this PLL */
 	int active; /* count of number of active CRTCs (i.e. DPMS on) */
+	bool on; /* is the PLL actually active? Disabled during modeset */
-	bool on; /* is the PLL actually active? Disabled during modeset */
+	const char *name;
+	/* should match the index in the dev_priv->shared_dplls array */
+	enum intel_dpll_id id;
+	struct intel_dpll_hw_state hw_state;
+	void (*mode_set)(struct drm_i915_private *dev_priv,
+			 struct intel_shared_dpll *pll);
+	void (*enable)(struct drm_i915_private *dev_priv,
-	int pll_reg;
+		       struct intel_shared_dpll *pll);
+	void (*disable)(struct drm_i915_private *dev_priv,
+			struct intel_shared_dpll *pll);
+	bool (*get_hw_state)(struct drm_i915_private *dev_priv,
-	int fp0_reg;
+			     struct intel_shared_dpll *pll,
-	int fp1_reg;
-};
+			     struct intel_dpll_hw_state *hw_state);
-#define I915_NUM_PLLS 2
+};
 /* Used by dp and fdi links */
  */
 #define DRIVER_MAJOR		1
 #define DRIVER_MINOR		6
 #define DRIVER_PATCHLEVEL	0
 #define WATCH_COHERENCY	0
 #define WATCH_LISTS	0
 #define WATCH_GTT	0
 struct opregion_header;
 struct opregion_acpi;
 struct opregion_swsci;
-struct opregion_asle;
-struct drm_i915_private;
+struct opregion_asle;
 struct intel_opregion {
 	struct opregion_header __iomem *header;
 		u32 tiling:2;
 		u32 dirty:1;
 		u32 purgeable:1;
 		s32 ring:4;
 		u32 cache_level:2;
-	} *active_bo, *pinned_bo;
+	} **active_bo, **pinned_bo;
-	u32 active_bo_count, pinned_bo_count;
+	u32 *active_bo_count, *pinned_bo_count;
 	struct intel_overlay_error_state *overlay;
 	struct intel_display_error_state *display;
 };
 struct intel_crtc_config;
+struct intel_crtc;
+struct intel_limit;
-struct intel_crtc;
+struct dpll;
 struct drm_i915_display_funcs {
 	bool (*fbc_enabled)(struct drm_device *dev);
 	void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
 	void (*disable_fbc)(struct drm_device *dev);
+	int (*get_display_clock_speed)(struct drm_device *dev);
+	int (*get_fifo_size)(struct drm_device *dev, int plane);
+	/**
+	 * find_dpll() - Find the best values for the PLL
+	 * @limit: limits for the PLL
+	 * @crtc: current CRTC
+	 * @target: target frequency in kHz
+	 * @refclk: reference clock frequency in kHz
+	 * @match_clock: if provided, @best_clock P divider must
+	 *               match the P divider from @match_clock
+	 *               used for LVDS downclocking
+	 * @best_clock: best PLL values found
+	 *
+	 * Returns true on success, false on failure.
+	 */
+	bool (*find_dpll)(const struct intel_limit *limit,
+			  struct drm_crtc *crtc,
+			  int target, int refclk,
-	int (*get_display_clock_speed)(struct drm_device *dev);
+			  struct dpll *match_clock,
-	int (*get_fifo_size)(struct drm_device *dev, int plane);
+			  struct dpll *best_clock);
+	void (*update_wm)(struct drm_device *dev);
-	void (*update_wm)(struct drm_device *dev);
+	void (*update_sprite_wm)(struct drm_plane *plane,
-	void (*update_sprite_wm)(struct drm_device *dev, int pipe,
-				 uint32_t sprite_width, int pixel_size);
+				 struct drm_crtc *crtc,
-	void (*update_linetime_wm)(struct drm_device *dev, int pipe,
+				 uint32_t sprite_width, int pixel_size,
-				 struct drm_display_mode *mode);
+				 bool enable, bool scaled);
 	void (*modeset_global_resources)(struct drm_device *dev);
 	/* Returns the active state of the crtc, and if the crtc is active,
 	 * fills out the pipe-config with the hw state. */
+	bool (*get_pipe_config)(struct intel_crtc *,
-	bool (*get_pipe_config)(struct intel_crtc *,
+				struct intel_crtc_config *);
-				struct intel_crtc_config *);
+	void (*get_clock)(struct intel_crtc *, struct intel_crtc_config *);
 	int (*crtc_mode_set)(struct drm_crtc *crtc,
 			     int x, int y,
 			     struct drm_framebuffer *old_fb);
 			  struct drm_crtc *crtc);
 	void (*fdi_link_train)(struct drm_crtc *crtc);
 	void (*init_clock_gating)(struct drm_device *dev);
 	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 			  struct drm_framebuffer *fb,
-			  struct drm_i915_gem_object *obj);
+			  struct drm_i915_gem_object *obj,
+			  uint32_t flags);
 	int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 			    int x, int y);
 	void (*hpd_irq_setup)(struct drm_device *dev);
 	/* clock updates for mode set */
 	/* cursor updates */
 	/* render clock increase/decrease */
 	/* display clock increase/decrease */
 	/* pll clock increase/decrease */
 };
-struct drm_i915_gt_funcs {
+struct intel_uncore_funcs {
 	void (*force_wake_get)(struct drm_i915_private *dev_priv);
 	void (*force_wake_put)(struct drm_i915_private *dev_priv);
+};
+struct intel_uncore {
+	spinlock_t lock; /** lock is also taken in irq contexts. */
+	struct intel_uncore_funcs funcs;
+	unsigned fifo_count;
+	unsigned forcewake_count;
 };
-#define DEV_INFO_FLAGS \
+#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
-	DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
+	func(is_mobile) sep \
-	DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
+	func(is_i85x) sep \
-	DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
+	func(is_i915g) sep \
-	DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
+	func(is_i945gm) sep \
-	DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
+	func(is_g33) sep \
-	DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
+	func(need_gfx_hws) sep \
-	DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
+	func(is_g4x) sep \
-	DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
+	func(is_pineview) sep \
-	DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
+	func(is_broadwater) sep \
-	DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
+	func(is_crestline) sep \
-	DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
+	func(is_ivybridge) sep \
-	DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
+	func(is_valleyview) sep \
-	DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
+	func(is_haswell) sep \
-	DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
+	func(has_force_wake) sep \
-	DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
+	func(has_fbc) sep \
-	DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
+	func(has_pipe_cxsr) sep \
-	DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
+	func(has_hotplug) sep \
-	DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
+	func(cursor_needs_physical) sep \
-	DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
+	func(has_overlay) sep \
-	DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
+	func(overlay_needs_physical) sep \
-	DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
+	func(supports_tv) sep \
+	func(has_bsd_ring) sep \
+	func(has_blt_ring) sep \
+	func(has_vebox_ring) sep \
-	DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
+	func(has_llc) sep \
+	func(has_ddi) sep \
+	func(has_fpga_dbg)
-	DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
+#define DEFINE_FLAG(name) u8 name:1
-	DEV_INFO_FLAG(has_llc)
+#define SEP_SEMICOLON ;
 struct intel_device_info {
-	u32 display_mmio_offset;
-	u8 num_pipes:3;
-	u8 gen;
-	u8 is_mobile:1;
-	u8 is_i85x:1;
-	u8 is_i915g:1;
-	u8 is_i945gm:1;
-	u8 is_g33:1;
-	u8 need_gfx_hws:1;
-	u8 is_g4x:1;
-	u8 is_pineview:1;
-	u8 is_broadwater:1;
-	u8 is_crestline:1;
-	u8 is_ivybridge:1;
-	u8 is_valleyview:1;
-	u8 has_force_wake:1;
-	u8 is_haswell:1;
-	u8 has_fbc:1;
-	u8 has_pipe_cxsr:1;
-	u8 has_hotplug:1;
+	u32 display_mmio_offset;
-	u8 cursor_needs_physical:1;
-	u8 has_overlay:1;
-	u8 overlay_needs_physical:1;
-	u8 supports_tv:1;
-	u8 has_bsd_ring:1;
+	u8 num_pipes:3;
+	u8 gen;
+	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
+};
 	u8 has_blt_ring:1;
-	u8 has_llc:1;
+#undef DEFINE_FLAG
+#undef SEP_SEMICOLON
+enum i915_cache_level {
+	I915_CACHE_NONE = 0,
+	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
+	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
+			      caches, eg sampler/render caches, and the
+			      large Last-Level-Cache. LLC is coherent with
+			      the CPU, but L3 is only visible to the GPU. */
+	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
+};
-};
+typedef uint32_t gen6_gtt_pte_t;
+struct i915_address_space {
+	struct drm_mm mm;
+	struct drm_device *dev;
+	struct list_head global_link;
+	unsigned long start;		/* Start offset always 0 for dri2 */
+	size_t total;		/* size addr space maps (ex. 2GB for ggtt) */
+	struct {
+		dma_addr_t addr;
+		struct page *page;
+	} scratch;
+	/**
+	 * List of objects currently involved in rendering.
+	 *
+	 * Includes buffers having the contents of their GPU caches
+	 * flushed, not necessarily primitives.  last_rendering_seqno
+	 * represents when the rendering involved will be completed.
+	 *
+	 * A reference is held on the buffer while on this list.
+	 */
+	struct list_head active_list;
+	/**
+	 * LRU list of objects which are not in the ringbuffer and
+	 * are ready to unbind, but are still in the GTT.
+	 *
+	 * last_rendering_seqno is 0 while an object is in this list.
+	 *
+	 * A reference is not held on the buffer while on this list,
+	 * as merely being GTT-bound shouldn't prevent its being
+	 * freed, and we'll pull it off the list in the free path.
+	 */
+	struct list_head inactive_list;
+	/* FIXME: Need a more generic return type */
+	gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
+				     enum i915_cache_level level);
+	void (*clear_range)(struct i915_address_space *vm,
+			    unsigned int first_entry,
+			    unsigned int num_entries);
+	void (*insert_entries)(struct i915_address_space *vm,
-enum i915_cache_level {
+			       struct sg_table *st,
-	I915_CACHE_NONE = 0,
+			       unsigned int first_entry,
-	I915_CACHE_LLC,
+			       enum i915_cache_level cache_level);
-	I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
+	void (*cleanup)(struct i915_address_space *vm);
 };
 /* The Graphics Translation Table is the way in which GEN hardware translates a
  * Graphics Virtual Address into a Physical Address. In addition to the normal
  * collateral associated with any va->pa translations GEN hardware also has a
- * portion of the GTT which can be mapped by the CPU and remain both coherent
- * and correct (in cases like swizzling). That region is referred to as GMADR in
+ * portion of the GTT which can be mapped by the CPU and remain both coherent
- * the spec.
+ * and correct (in cases like swizzling). That region is referred to as GMADR in
- */
+ * the spec.
-struct i915_gtt {
+ */
-	unsigned long start;		/* Start offset of used GTT */
+struct i915_gtt {
-	size_t total;			/* Total size GTT can map */
+	struct i915_address_space base;
 	size_t stolen_size;		/* Total size of stolen memory */
-	unsigned long mappable_end;	/* End offset that we can CPU map */
+	unsigned long mappable_end;	/* End offset that we can CPU map */
 	struct io_mapping *mappable;	/* Mapping to our CPU mappable region */
 	phys_addr_t mappable_base;	/* PA of our GMADR */
 	/** "Graphics Stolen Memory" holds the global PTEs */
 	void __iomem *gsm;
-	bool do_idle_maps;
-	dma_addr_t scratch_page_dma;
-	struct page *scratch_page;
-	/* global gtt ops */
-	int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
-			  size_t *stolen, phys_addr_t *mappable_base,
 			  unsigned long *mappable_end);
-	void (*gtt_remove)(struct drm_device *dev);
+	bool do_idle_maps;
-	void (*gtt_clear_range)(struct drm_device *dev,
-				unsigned int first_entry,
 				unsigned int num_entries);
-	void (*gtt_insert_entries)(struct drm_device *dev,
+	int mtrr;
 				   struct sg_table *st,
-				   unsigned int pg_start,
+	/* global gtt ops */
-				   enum i915_cache_level cache_level);
+	int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
-};
+			  size_t *stolen, phys_addr_t *mappable_base,
-#define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
-#define I915_PPGTT_PD_ENTRIES 512
-#define I915_PPGTT_PT_ENTRIES 1024
-struct i915_hw_ppgtt {
-	struct drm_device *dev;
-	unsigned num_pd_entries;
-	struct page **pt_pages;
-	uint32_t pd_offset;
-	dma_addr_t *pt_dma_addr;
+			  unsigned long *mappable_end);
-	dma_addr_t scratch_page_dma_addr;
 };
+#define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
+struct i915_hw_ppgtt {
+	struct i915_address_space base;
+	unsigned num_pd_entries;
+	struct page **pt_pages;
+	uint32_t pd_offset;
+	dma_addr_t *pt_dma_addr;
+	int (*enable)(struct drm_device *dev);
+};
+/**
+ * A VMA represents a GEM BO that is bound into an address space. Therefore, a
+ * VMA's presence cannot be guaranteed before binding, or after unbinding the
+ * object into/from the address space.
+ *
+ * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
+ * will always be <= an objects lifetime. So object refcounting should cover us.
+ */
+struct i915_vma {
+	struct drm_mm_node node;
+	struct drm_i915_gem_object *obj;
+	struct i915_address_space *vm;
+	/** This object's place on the active/inactive lists */
+	struct list_head mm_list;
+	struct list_head vma_link; /* Link in the object's VMA list */
-	/* pte functions, mirroring the interface of the global gtt. */
+	/** This vma's place in the batchbuffer or on the eviction list */
-	void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
+	struct list_head exec_list;
 			    unsigned int first_entry,
+};
 			    unsigned int num_entries);
-	void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
+struct i915_ctx_hang_stats {
-			       struct sg_table *st,
+	/* This context had batch pending when hang was declared */
-			       unsigned int pg_start,
+	unsigned batch_pending;
 			       enum i915_cache_level cache_level);
+	/* This context had batch active when hang was declared */
-	int (*enable)(struct drm_device *dev);
+	unsigned batch_active;
+};
+/* This must match up with the value previously used for execbuf2.rsvd1. */
+#define DEFAULT_CONTEXT_ID 0
+struct i915_hw_context {
+	struct kref ref;
+	int id;
+	bool is_initialized;
+	struct drm_i915_file_private *file_priv;
+	struct intel_ring_buffer *ring;
+	struct drm_i915_gem_object *obj;
+	struct i915_ctx_hang_stats hang_stats;
+};
+struct i915_fbc {
+	unsigned long size;
-	void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
+	unsigned int fb_id;
+	enum plane plane;
+	int y;
 };
+	struct drm_mm_node *compressed_fb;
 	struct drm_mm_node *compressed_llb;
 /* This must match up with the value previously used for execbuf2.rsvd1. */
-#define DEFAULT_CONTEXT_ID 0
+	struct intel_fbc_work {
-struct i915_hw_context {
+		struct delayed_work work;
-	int id;
+		struct drm_crtc *crtc;
-	bool is_initialized;
+		struct drm_framebuffer *fb;
+		int interval;
+	} *fbc_work;
+enum no_fbc_reason {
+		FBC_OK, /* FBC is enabled */
+		FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
+	FBC_NO_OUTPUT, /* no outputs enabled to compress */
+		FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
+	FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
+	FBC_MODE_TOO_LARGE, /* mode too large for compression */
+	FBC_BAD_PLANE, /* fbc not supported on plane */
+	FBC_NOT_TILED, /* buffer not tiled */
+	FBC_MULTIPLE_PIPES, /* more than one pipe active */
+	FBC_MODULE_PARAM,
+		FBC_CHIP_DEFAULT, /* disabled by default on this chip */
-	struct drm_i915_file_private *file_priv;
+	} no_fbc_reason;
-	struct intel_ring_buffer *ring;
+};
 	struct drm_i915_gem_object *obj;
-};
+enum no_psr_reason {
 };
 #define QUIRK_PIPEA_FORCE (1<<0)
 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
+#define QUIRK_INVERT_BRIGHTNESS (1<<2)
-#define QUIRK_INVERT_BRIGHTNESS (1<<2)
+#define QUIRK_NO_PCH_PWM_ENABLE (1<<3)
 struct intel_fbdev;
 	u32 saveMCHBAR_RENDER_STANDBY;
 	u32 savePCH_PORT_HOTPLUG;
 };
+struct intel_gen6_power_mgmt {
-struct intel_gen6_power_mgmt {
+	/* work and pm_iir are protected by dev_priv->irq_lock */
 	struct work_struct work;
+	u32 pm_iir;
-	u32 pm_iir;
-	/* lock - irqsave spinlock that protectects the work_struct and
-	 * pm_iir. */
+	/* On vlv we need to manually drop to Vmin with a delayed work. */
-	spinlock_t lock;
+	struct delayed_work vlv_work;
 	/* The below variables an all the rps hw state are protected by
 	 * dev->struct mutext. */
 	u8 cur_delay;
+	u8 min_delay;
-	u8 min_delay;
+	u8 max_delay;
-	u8 max_delay;
+	u8 rpe_delay;
 	u8 hw_max;
 	struct drm_i915_gem_object *pwrctx;
 	struct drm_i915_gem_object *renderctx;
+};
+/* Power well structure for haswell */
+struct i915_power_well {
+	struct drm_device *device;
+	spinlock_t lock;
+	/* power well enable/disable usage count */
+	int count;
+	int i915_request;
 };
 struct i915_dri1_state {
 	unsigned allow_batchbuffer : 1;
 	int page_flipping;
 	uint32_t counter;
+};
+struct i915_ums_state {
+	/**
+	 * Flag if the X Server, and thus DRM, is not currently in
+	 * control of the device.
+	 *
+	 * This is set between LeaveVT and EnterVT.  It needs to be
+	 * replaced with a semaphore.  It also needs to be
+	 * transitioned away from for kernel modesetting.
+	 */
+	int mm_suspended;
 };
 struct intel_l3_parity {
 	u32 *remap_info;
 	struct work_struct error_work;
 };
-struct i915_gem_mm {
-	/** Memory allocator for GTT stolen memory */
-	struct drm_mm stolen;
+struct i915_gem_mm {
-	/** Memory allocator for GTT */
+	/** Memory allocator for GTT stolen memory */
-	struct drm_mm gtt_space;
+	struct drm_mm stolen;
 	/** List of all objects in gtt_space. Used to restore gtt
 	 * mappings on resume */
 	struct list_head unbound_list;
 	/** Usable portion of the GTT for GEM */
-	unsigned long stolen_base; /* limited to low memory (32-bit) */
-	int gtt_mtrr;
+	unsigned long stolen_base; /* limited to low memory (32-bit) */
 	/** PPGTT used for aliasing the PPGTT with the GTT */
-	struct i915_hw_ppgtt *aliasing_ppgtt;
-	bool shrinker_no_lock_stealing;
-	/**
-	 * List of objects currently involved in rendering.
-	 *
-	 * Includes buffers having the contents of their GPU caches
-	 * flushed, not necessarily primitives.  last_rendering_seqno
-	 * represents when the rendering involved will be completed.
-	 *
-	 * A reference is held on the buffer while on this list.
-	 */
-	struct list_head active_list;
-	/**
-	 * LRU list of objects which are not in the ringbuffer and
-	 * are ready to unbind, but are still in the GTT.
-	 *
-	 * last_rendering_seqno is 0 while an object is in this list.
-	 *
-	 * A reference is not held on the buffer while on this list,
-	 * as merely being GTT-bound shouldn't prevent its being
-	 * freed, and we'll pull it off the list in the free path.
+	struct i915_hw_ppgtt *aliasing_ppgtt;
 	 */
-	struct list_head inactive_list;
+	bool shrinker_no_lock_stealing;
 	 * Are we in a non-interruptible section of code like
 	 * modesetting?
 	 */
 	bool interruptible;
-	/**
-	 * Flag if the X Server, and thus DRM, is not currently in
-	 * control of the device.
-	 *
-	 * This is set between LeaveVT and EnterVT.  It needs to be
-	 * replaced with a semaphore.  It also needs to be
-	 * transitioned away from for kernel modesetting.
-	 */
-	int suspended;
 	/** Bit 6 swizzling required for X tiling */
 	uint32_t bit_6_swizzle_x;
 	/** Bit 6 swizzling required for Y tiling */
 	uint32_t bit_6_swizzle_y;
 	/* storage for physical objects */
+	struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 	struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 	/* accounting, useful for userland debugging */
-	/* accounting, useful for userland debugging */
+	spinlock_t object_stat_lock;
+	size_t object_memory;
+	u32 object_count;
+};
+struct drm_i915_error_state_buf {
+	unsigned bytes;
+	unsigned size;
+	int err;
+	u8 *buf;
+	loff_t start;
+	loff_t pos;
+};
+struct i915_error_state_file_priv {
-	size_t object_memory;
+	struct drm_device *dev;
-	u32 object_count;
+	struct drm_i915_error_state *error;
 };
 struct i915_gpu_error {
-	/* For hangcheck timer */
-#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
-#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
-	struct timer_list hangcheck_timer;
+	/* For hangcheck timer */
-	int hangcheck_count;
+#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
-	uint32_t last_acthd[I915_NUM_RINGS];
+#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
-	uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
+	struct timer_list hangcheck_timer;
 	MODESET_ON_LID_OPEN,
 	MODESET_DONE,
 	MODESET_SUSPENDED,
 };
+struct intel_vbt_data {
+	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
+	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
+	/* Feature bits */
+	unsigned int int_tv_support:1;
+	unsigned int lvds_dither:1;
+	unsigned int lvds_vbt:1;
+	unsigned int int_crt_support:1;
+	unsigned int lvds_use_ssc:1;
+	unsigned int display_clock_mode:1;
+	unsigned int fdi_rx_polarity_inverted:1;
+	int lvds_ssc_freq;
+	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
+	/* eDP */
+	int edp_rate;
+	int edp_lanes;
+	int edp_preemphasis;
+	int edp_vswing;
+	bool edp_initialized;
+	bool edp_support;
+	int edp_bpp;
+	struct edp_power_seq edp_pps;
+	int crt_ddc_pin;
+	int child_dev_num;
+	struct child_device_config *child_dev;
+};
+enum intel_ddb_partitioning {
+	INTEL_DDB_PART_1_2,
+	INTEL_DDB_PART_5_6, /* IVB+ */
+};
+struct intel_wm_level {
+	bool enable;
+	uint32_t pri_val;
+	uint32_t spr_val;
+	uint32_t cur_val;
+	uint32_t fbc_val;
+};
+/*
+ * This struct tracks the state needed for the Package C8+ feature.
+ *
+ * Package states C8 and deeper are really deep PC states that can only be
+ * reached when all the devices on the system allow it, so even if the graphics
+ * device allows PC8+, it doesn't mean the system will actually get to these
+ * states.
+ *
+ * Our driver only allows PC8+ when all the outputs are disabled, the power well
+ * is disabled and the GPU is idle. When these conditions are met, we manually
+ * do the other conditions: disable the interrupts, clocks and switch LCPLL
+ * refclk to Fclk.
+ *
+ * When we really reach PC8 or deeper states (not just when we allow it) we lose
+ * the state of some registers, so when we come back from PC8+ we need to
+ * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
+ * need to take care of the registers kept by RC6.
+ *
+ * The interrupt disabling is part of the requirements. We can only leave the
+ * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
+ * can lock the machine.
+ *
+ * Ideally every piece of our code that needs PC8+ disabled would call
+ * hsw_disable_package_c8, which would increment disable_count and prevent the
+ * system from reaching PC8+. But we don't have a symmetric way to do this for
+ * everything, so we have the requirements_met and gpu_idle variables. When we
+ * switch requirements_met or gpu_idle to true we decrease disable_count, and
+ * increase it in the opposite case. The requirements_met variable is true when
+ * all the CRTCs, encoders and the power well are disabled. The gpu_idle
+ * variable is true when the GPU is idle.
+ *
+ * In addition to everything, we only actually enable PC8+ if disable_count
+ * stays at zero for at least some seconds. This is implemented with the
+ * enable_work variable. We do this so we don't enable/disable PC8 dozens of
+ * consecutive times when all screens are disabled and some background app
+ * queries the state of our connectors, or we have some application constantly
+ * waking up to use the GPU. Only after the enable_work function actually
+ * enables PC8+ the "enable" variable will become true, which means that it can
+ * be false even if disable_count is 0.
+ *
+ * The irqs_disabled variable becomes true exactly after we disable the IRQs and
+ * goes back to false exactly before we reenable the IRQs. We use this variable
+ * to check if someone is trying to enable/disable IRQs while they're supposed
+ * to be disabled. This shouldn't happen and we'll print some error messages in
+ * case it happens, but if it actually happens we'll also update the variables
+ * inside struct regsave so when we restore the IRQs they will contain the
+ * latest expected values.
+ *
+ * For more, read "Display Sequences for Package C8" on our documentation.
+ */
+struct i915_package_c8 {
+	bool requirements_met;
+	bool gpu_idle;
+	bool irqs_disabled;
+	/* Only true after the delayed work task actually enables it. */
+	bool enabled;
+	int disable_count;
+	struct mutex lock;
+	struct delayed_work enable_work;
+	struct {
+		uint32_t deimr;
+		uint32_t sdeimr;
+		uint32_t gtimr;
+		uint32_t gtier;
+		uint32_t gen6_pmimr;
+	} regsave;
+};
 typedef struct drm_i915_private {
 	struct drm_device *dev;
 	const struct intel_device_info *info;
-	int relative_constants_mode;
-	void __iomem *regs;
-	struct drm_i915_gt_funcs gt;
-	/** gt_fifo_count and the subsequent register write are synchronized
-	 * with dev->struct_mutex. */
-	unsigned gt_fifo_count;
+	int relative_constants_mode;
 	/** forcewake_count is protected by gt_lock */
 	struct mutex dpio_lock;
 	/** Cached value of IMR to avoid reads in updating the bitfield */
 	u32 irq_mask;
+	u32 gt_irq_mask;
-	u32 gt_irq_mask;
+	u32 pm_irq_mask;
 	struct work_struct hotplug_work;
 	bool enable_hotplug_processing;
 			HPD_ENABLED = 0,
 			HPD_DISABLED = 1,
 			HPD_MARK_DISABLED = 2
 		} hpd_mark;
 	} hpd_stats[HPD_NUM_PINS];
+	u32 hpd_event_bits;
 	int num_pch_pll;
-	int num_plane;
-	unsigned long cfb_size;
-	unsigned int cfb_fb;
-	enum plane cfb_plane;
+	int num_plane;
-	int cfb_y;
 	struct intel_fbc_work *fbc_work;
+	struct i915_fbc fbc;
 	struct intel_opregion opregion;
-	struct intel_opregion opregion;
+	struct intel_vbt_data vbt;
 	/* overlay */
 	struct intel_overlay *overlay;
 	unsigned int sprite_scaling_enabled;
+	/* backlight */
-	/* backlight */
+	struct {
-	struct {
+		int level;
-		int level;
+		bool enabled;
-		bool enabled;
-		struct backlight_device *device;
-	} backlight;
-	/* LVDS info */
-	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
-	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
-	/* Feature bits from the VBIOS */
-	unsigned int int_tv_support:1;
-	unsigned int lvds_dither:1;
-	unsigned int lvds_vbt:1;
-	unsigned int int_crt_support:1;
-	unsigned int lvds_use_ssc:1;
-	unsigned int display_clock_mode:1;
-	unsigned int fdi_rx_polarity_inverted:1;
-	int lvds_ssc_freq;
-	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
-	struct {
-		int rate;
-		int lanes;
-		int preemphasis;
-		int vswing;
-		bool initialized;
+		spinlock_t lock; /* bl registers and the above bl fields */
-		bool support;
-		int bpp;
+		struct backlight_device *device;
-		struct edp_power_seq pps;
+	} backlight;
 	} edp;
-	bool no_aux_handshake;
+	/* LVDS info */
+	bool no_aux_handshake;
+	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
+	int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
+	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
+	unsigned int fsb_freq, mem_freq, is_ddr3;
-	int crt_ddc_pin;
+	/**
-	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
+	 * wq - Driver workqueue for GEM.
 	unsigned long quirks;
 	enum modeset_restore modeset_restore;
+	struct mutex modeset_restore_lock;
-	struct mutex modeset_restore_lock;
 	struct list_head vm_list; /* Global list of all address spaces */
-	struct i915_gtt gtt;
+	struct i915_gtt gtt; /* VMA representing the global address space */
-	struct i915_gem_mm mm;
-	/* Kernel Modesetting */
-    struct sdvo_device_mapping sdvo_mappings[2];
+	struct i915_gem_mm mm;
 	/* indicate whether the LVDS_BORDER should be enabled or not */
-	unsigned int lvds_border_bits;
+	/* Kernel Modesetting */
-	/* Panel fitter placement and size for Ironlake+ */
+    struct sdvo_device_mapping sdvo_mappings[2];
 	u32 pch_pf_pos, pch_pf_size;
     struct drm_crtc *plane_to_crtc_mapping[3];
-    struct drm_crtc *plane_to_crtc_mapping[3];
+    struct drm_crtc *pipe_to_crtc_mapping[3];
-    struct drm_crtc *pipe_to_crtc_mapping[3];
+	wait_queue_head_t pending_flip_queue;
 	wait_queue_head_t pending_flip_queue;
 	int num_shared_dpll;
-	struct intel_pch_pll pch_plls[I915_NUM_PLLS];
+	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
-	struct intel_ddi_plls ddi_plls;
-	/* Reclocking support */
+	struct intel_ddi_plls ddi_plls;
 	bool render_reclock_avail;
+	/* Reclocking support */
+	bool render_reclock_avail;
+	bool lvds_downclock_avail;
-	bool lvds_downclock_avail;
+	/* indicates the reduced downclock for LVDS*/
-	/* indicates the reduced downclock for LVDS*/
+	int lvds_downclock;
-	int lvds_downclock;
+	u16 orig_clock;
 	u16 orig_clock;
-	int child_dev_num;
+	bool mchbar_need_disable;
-    struct child_device_config *child_dev;
+	struct intel_l3_parity l3_parity;
-	bool mchbar_need_disable;
 	/* Cannot be determined by PCIID. You must always read a register. */
+	size_t ellc_size;
-	struct intel_l3_parity l3_parity;
+	/* gen6+ rps state */
 	struct intel_gen6_power_mgmt rps;
 	/* gen6+ rps state */
-	struct intel_gen6_power_mgmt rps;
+	/* ilk-only ips/rps state. Everything in here is protected by the global
 	u32 fdi_rx_config;
+	struct i915_suspend_saved_registers regfile;
+	struct {
+		/*
+		 * Raw watermark latency values:
+		 * in 0.1us units for WM0,
+		 * in 0.5us units for WM1+.
+		 */
+		/* primary */
+		uint16_t pri_latency[5];
+		/* sprite */
+		uint16_t spr_latency[5];
+		/* cursor */
+		uint16_t cur_latency[5];
+	} wm;
-	struct i915_suspend_saved_registers regfile;
+	struct i915_package_c8 pc8;
+	/* Old dri1 support infrastructure, beware the dragons ya fools entering
+	 * here! */
-	/* Old dri1 support infrastructure, beware the dragons ya fools entering
+	struct i915_dri1_state dri1;
+	/* Old ums support infrastructure, same warning applies. */
+	struct i915_ums_state ums;
+} drm_i915_private_t;
+static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
 	 * here! */
-	struct i915_dri1_state dri1;
+	return dev->dev_private;
 } drm_i915_private_t;
 	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
 	HDMI_AUDIO_AUTO,		/* trust EDID */
 	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
 };
-#define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
+#define I915_GTT_OFFSET_NONE ((u32)-1)
 struct drm_i915_gem_object_ops {
 	/* Interface between the GEM object and its backing storage.
 struct drm_i915_gem_object {
     struct drm_gem_object base;
 	const struct drm_i915_gem_object_ops *ops;
+	/** List of VMAs backed by this object */
-    /** Current space allocated to this object in the GTT, if any. */
+	struct list_head vma_list;
     struct drm_mm_node *gtt_space;
 	/** Stolen memory for this object, instead of being backed by shmem. */
-	struct drm_mm_node *stolen;
-    struct list_head gtt_list;
+	struct drm_mm_node *stolen;
+	struct list_head global_list;
-	/** This object's place on the active/inactive lists */
+    struct list_head ring_list;
-    struct list_head ring_list;
+	/** Used in execbuf to temporarily hold a ref */
-    struct list_head mm_list;
+	struct list_head obj_exec_link;
     /** This object's place in the batchbuffer or on the eviction list */
      * mappable by accident). Track pin and fault separate for a more
      * accurate mappable working set.
      */
 	unsigned int fault_mappable:1;
 	unsigned int pin_mappable:1;
+	unsigned int pin_display:1;
     /*
      * Is the GPU currently using a fence to access this buffer,
      */
     unsigned int pending_fenced_gpu_access:1;
     unsigned int fenced_gpu_access:1;
-    unsigned int cache_level:2;
+	unsigned int cache_level:3;
      */
     struct hlist_node exec_node;
     unsigned long exec_handle;
     struct drm_i915_gem_exec_object2 *exec_entry;
-    /**
-     * Current offset of the object in GTT space.
-     *
-     * This is the same as gtt_space->start
-     */
-    uint32_t gtt_offset;
 	struct intel_ring_buffer *ring;
     /** Breadcrumb of last rendering to the buffer. */
 	struct intel_ring_buffer *ring;
 	/** GEM sequence number associated with this request. */
+	uint32_t seqno;
+	/** Position in the ringbuffer of the start of the request */
-	uint32_t seqno;
+	u32 head;
+	/** Position in the ringbuffer of the end of the request */
+	u32 tail;
+	/** Context related to this request */
+	struct i915_hw_context *ctx;
-	/** Postion in the ringbuffer of the end of the request */
+	/** Batch buffer related to this request if any */
-	u32 tail;
+	struct drm_i915_gem_object *batch_obj;
 	/** Time at which this request was emitted, in jiffies. */
 	struct {
 		spinlock_t lock;
 		struct list_head request_list;
 	} mm;
 	struct idr context_idr;
+	struct i915_ctx_hang_stats hang_stats;
 };
-#define INTEL_INFO(dev)	(((struct drm_i915_private *) (dev)->dev_private)->info)
+#define INTEL_INFO(dev)	(to_i915(dev)->info)
 #define IS_I830(dev)		((dev)->pci_device == 0x3577)
 #define IS_845G(dev)		((dev)->pci_device == 0x2562)
 #define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)
 #define IS_PINEVIEW_G(dev)	((dev)->pci_device == 0xa001)
 #define IS_PINEVIEW_M(dev)	((dev)->pci_device == 0xa011)
 #define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
 #define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
-#define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)
 #define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)
 #define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
 #define IS_IVB_GT1(dev)		((dev)->pci_device == 0x0156 || \
 				 (dev)->pci_device == 0x0152 ||	\
 				 (dev)->pci_device == 0x015a)
 				 (dev)->pci_device == 0x0106 ||	\
 				 (dev)->pci_device == 0x010A)
 #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
 #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
+#define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
+				 ((dev)->pci_device & 0xFF00) == 0x0C00)
 #define IS_ULT(dev)		(IS_HASWELL(dev) && \
 				 ((dev)->pci_device & 0xFF00) == 0x0A00)
 /*
 #define IS_GEN6(dev)	(INTEL_INFO(dev)->gen == 6)
 #define IS_GEN7(dev)	(INTEL_INFO(dev)->gen == 7)
 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
+#define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
-#define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
+#define HAS_VEBOX(dev)          (INTEL_INFO(dev)->has_vebox_ring)
+#define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
-#define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
+#define HAS_WT(dev)            (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
 #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
 #define SUPPORTS_INTEGRATED_HDMI(dev)	(IS_G4X(dev) || IS_GEN5(dev))
 #define SUPPORTS_INTEGRATED_DP(dev)	(IS_G4X(dev) || IS_GEN5(dev))
 #define SUPPORTS_EDP(dev)		(IS_IRONLAKE_M(dev))
 #define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
 #define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)
-/* dsparb controlled by hw only */
-#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
-#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
+#define HAS_IPS(dev)		(IS_ULT(dev))
 #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
-#define HAS_DDI(dev)		(IS_HASWELL(dev))
+#define HAS_POWER_WELL(dev)	(IS_HASWELL(dev))
-#define HAS_POWER_WELL(dev)	(IS_HASWELL(dev))
+#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
 #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
 #define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
 #define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
-#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
+#define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
 extern int i915_vbt_sdvo_panel_type     __read_mostly;
 extern int i915_enable_rc6              __read_mostly;
 extern int i915_enable_fbc              __read_mostly;
 extern bool i915_enable_hangcheck       __read_mostly;
 extern int i915_enable_ppgtt            __read_mostly;
+extern int i915_enable_psr __read_mostly;
 extern unsigned int i915_preliminary_hw_support __read_mostly;
 extern int i915_disable_power_well __read_mostly;
+extern int i915_enable_ips __read_mostly;
+extern bool i915_fastboot __read_mostly;
+extern int i915_enable_pc8 __read_mostly;
+extern int i915_pc8_timeout __read_mostly;
+extern bool i915_prefault_disable __read_mostly;
 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
 extern void intel_console_resume(struct work_struct *work);
 /* i915_irq.c */
-void i915_hangcheck_elapsed(unsigned long data);
+void i915_queue_hangcheck(struct drm_device *dev);
+void i915_handle_error(struct drm_device *dev, bool wedged);
 void i915_handle_error(struct drm_device *dev, bool wedged);
+extern void intel_irq_init(struct drm_device *dev);
-extern void intel_irq_init(struct drm_device *dev);
-extern void intel_hpd_init(struct drm_device *dev);
+extern void intel_pm_init(struct drm_device *dev);
+extern void intel_hpd_init(struct drm_device *dev);
+extern void intel_pm_init(struct drm_device *dev);
+extern void intel_uncore_sanitize(struct drm_device *dev);
-extern void intel_gt_init(struct drm_device *dev);
+extern void intel_uncore_early_sanitize(struct drm_device *dev);
-extern void intel_gt_reset(struct drm_device *dev);
+extern void intel_uncore_init(struct drm_device *dev);
 extern void intel_uncore_clear_errors(struct drm_device *dev);
-void i915_error_state_free(struct kref *error_ref);
+extern void intel_uncore_check_errors(struct drm_device *dev);
-void
-i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
-void
-i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
-void intel_enable_asle(struct drm_device *dev);
 #ifdef CONFIG_DEBUG_FS
-extern void i915_destroy_error_state(struct drm_device *dev);
+void
-#else
+i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 #define i915_destroy_error_state(x)
-#endif
+void
 void i915_gem_object_init(struct drm_i915_gem_object *obj,
 			 const struct drm_i915_gem_object_ops *ops);
 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
 						  size_t size);
 void i915_gem_free_object(struct drm_gem_object *obj);
+struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj,
+				     struct i915_address_space *vm);
+void i915_gem_vma_destroy(struct i915_vma *vma);
+int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
-int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
+				     struct i915_address_space *vm,
 				     uint32_t alignment,
 				     bool map_and_fenceable,
 				     bool nonblocking);
+void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
-void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
+int __must_check i915_vma_unbind(struct i915_vma *vma);
-int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
+int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj);
 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
 void i915_gem_lastclose(struct drm_device *dev);
 int i915_gem_dumb_create(struct drm_file *file_priv,
 			 struct drm_device *dev,
 			 struct drm_mode_create_dumb *args);
 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
 		      uint32_t handle, uint64_t *offset);
-int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
-			  uint32_t handle);
 /**
  * Returns true if seq1 is later than seq2.
  */
 static inline bool
 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
 static inline void
 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
+{
 	if (obj->fence_reg != I915_FENCE_REG_NONE) {
 		struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
+		WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
 		dev_priv->fence_regs[obj->fence_reg].pin_count--;
+	}
+}
+{
 	return atomic_read(&error->reset_counter) == I915_WEDGED;
+}
 void i915_gem_reset(struct drm_device *dev);
-void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
-int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
-					    uint32_t read_domains,
-					    uint32_t write_domain);
+bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
 int __must_check i915_gem_init(struct drm_device *dev);
 int __must_check i915_gem_init_hw(struct drm_device *dev);
 void i915_gem_l3_remap(struct drm_device *dev);
 void i915_gem_init_swizzling(struct drm_device *dev);
 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
 int __must_check i915_gpu_idle(struct drm_device *dev);
 int __must_check i915_gem_idle(struct drm_device *dev);
-int i915_add_request(struct intel_ring_buffer *ring,
+int __i915_add_request(struct intel_ring_buffer *ring,
+				  struct drm_file *file,
-				  struct drm_file *file,
+		       struct drm_i915_gem_object *batch_obj,
+		     u32 *seqno);
+#define i915_add_request(ring, seqno) \
-		     u32 *seqno);
+	__i915_add_request(ring, NULL, NULL, seqno)
 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
 				   uint32_t seqno);
 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 int __must_check
 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
 int __must_check
 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
 				     u32 alignment,
 				     struct intel_ring_buffer *pipelined);
+void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
 int i915_gem_attach_phys_object(struct drm_device *dev,
 				struct drm_i915_gem_object *obj,
 				int id,
 				int align);
 void i915_gem_detach_phys_object(struct drm_device *dev,
 			    int tiling_mode, bool fenced);
 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
+				    enum i915_cache_level cache_level);
-				    enum i915_cache_level cache_level);
+struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
 				struct dma_buf *dma_buf);
+struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
+				struct drm_gem_object *gem_obj, int flags);
+void i915_gem_restore_fences(struct drm_device *dev);
+unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
+				  struct i915_address_space *vm);
+bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
+bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
+			struct i915_address_space *vm);
+unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
+				struct i915_address_space *vm);
+struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
+				     struct i915_address_space *vm);
+struct i915_vma *
+i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
+				  struct i915_address_space *vm);
+/* Some GGTT VM helpers */
+#define obj_to_ggtt(obj) \
+	(&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
+static inline bool i915_is_ggtt(struct i915_address_space *vm)
+{
+	struct i915_address_space *ggtt =
+		&((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
+	return vm == ggtt;
+}
+static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
+{
+	return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
+}
+static inline unsigned long
+i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
+{
+	return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
+}
+static inline unsigned long
+i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
+{
+	return i915_gem_obj_size(obj, obj_to_ggtt(obj));
+}
+static inline int __must_check
+i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
+		      uint32_t alignment,
+		      bool map_and_fenceable,
+		      bool nonblocking)
+{
-struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
+	return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment,
-				struct drm_gem_object *gem_obj, int flags);
+				   map_and_fenceable, nonblocking);
+}
-void i915_gem_restore_fences(struct drm_device *dev);
+#undef obj_to_ggtt
 /* i915_gem_context.c */
+void i915_gem_context_init(struct drm_device *dev);
+void i915_gem_context_fini(struct drm_device *dev);
+void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
+int i915_switch_context(struct intel_ring_buffer *ring,
+			struct drm_file *file, int to_id);
+void i915_gem_context_free(struct kref *ctx_ref);
+static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
+{
+	kref_get(&ctx->ref);
+}
+static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
+{
+	kref_put(&ctx->ref, i915_gem_context_free);
+}
 void i915_gem_context_init(struct drm_device *dev);
-void i915_gem_context_fini(struct drm_device *dev);
+struct i915_ctx_hang_stats * __must_check
-void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
+i915_gem_context_get_hang_stats(struct drm_device *dev,
-int i915_switch_context(struct intel_ring_buffer *ring,
+				struct drm_file *file,
 		intel_gtt_chipset_flush();
+}
+/* i915_gem_evict.c */
+int __must_check i915_gem_evict_something(struct drm_device *dev,
-/* i915_gem_evict.c */
+					  struct i915_address_space *vm,
-int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
+					  int min_size,
 					  unsigned alignment,
 					  unsigned cache_level,
 					  bool mappable,
 					       u32 gtt_offset,
 					       u32 size);
 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
 /* i915_gem_tiling.c */
-inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
+static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
+{
 	drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
-/* i915_gem_debug.c */
-void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
-			  const char *where, uint32_t mark);
+/* i915_gem_debug.c */
 #if WATCH_LISTS
 int i915_verify_lists(struct drm_device *dev);
 #else
 #define i915_verify_lists(dev) 0
-#endif
-void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
-				     int handle);
-void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
-			  const char *where, uint32_t mark);
+#endif
 /* i915_debugfs.c */
+int i915_debugfs_init(struct drm_minor *minor);
+void i915_debugfs_cleanup(struct drm_minor *minor);
+/* i915_gpu_error.c */
+__printf(2, 3)
+void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
+int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
+			    const struct i915_error_state_file_priv *error);
+int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
+			      size_t count, loff_t pos);
+static inline void i915_error_state_buf_release(
+	struct drm_i915_error_state_buf *eb)
+{
+	kfree(eb->buf);
+}
+void i915_capture_error_state(struct drm_device *dev);
+void i915_error_state_get(struct drm_device *dev,
+			  struct i915_error_state_file_priv *error_priv);
+void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
+void i915_destroy_error_state(struct drm_device *dev);
-int i915_debugfs_init(struct drm_minor *minor);
+void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
-void i915_debugfs_cleanup(struct drm_minor *minor);
+const char *i915_cache_level_str(int type);
 /* i915_suspend.c */
 void i915_teardown_sysfs(struct drm_device *dev_priv);
 /* intel_i2c.c */
 extern int intel_setup_gmbus(struct drm_device *dev);
 extern void intel_teardown_gmbus(struct drm_device *dev);
-extern inline bool intel_gmbus_is_port_valid(unsigned port)
+static inline bool intel_gmbus_is_port_valid(unsigned port)
+{
 	return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
+}
 extern struct i2c_adapter *intel_gmbus_get_adapter(
 		struct drm_i915_private *dev_priv, unsigned port);
 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
-extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
+static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
+{
 	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
 extern int intel_opregion_setup(struct drm_device *dev);
 #ifdef CONFIG_ACPI
 extern void intel_opregion_init(struct drm_device *dev);
 extern void intel_opregion_fini(struct drm_device *dev);
 extern void intel_opregion_asle_intr(struct drm_device *dev);
-extern void intel_opregion_gse_intr(struct drm_device *dev);
-extern void intel_opregion_enable_asle(struct drm_device *dev);
 #else
 static inline void intel_opregion_init(struct drm_device *dev) { return; }
 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
-static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
-static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
 #endif
 /* intel_acpi.c */
 #ifdef CONFIG_ACPI
 static inline void intel_unregister_dsm_handler(void) { return; }
 #endif /* CONFIG_ACPI */
 /* modesetting */
+extern void intel_modeset_init_hw(struct drm_device *dev);
-extern void intel_modeset_init_hw(struct drm_device *dev);
+extern void intel_modeset_suspend_hw(struct drm_device *dev);
 extern void intel_modeset_init(struct drm_device *dev);
 extern void intel_modeset_gem_init(struct drm_device *dev);
 extern void intel_modeset_cleanup(struct drm_device *dev);
 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
 extern bool intel_fbc_enabled(struct drm_device *dev);
 extern void intel_disable_fbc(struct drm_device *dev);
 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
 extern void intel_init_pch_refclk(struct drm_device *dev);
 extern void gen6_set_rps(struct drm_device *dev, u8 val);
+extern void valleyview_set_rps(struct drm_device *dev, u8 val);
+extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
+extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
 extern void intel_detect_pch(struct drm_device *dev);
 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
 extern int intel_enable_rc6(const struct drm_device *dev);
 			struct drm_file *file);
 /* overlay */
 #ifdef CONFIG_DEBUG_FS
 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
+extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
-extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
+					    struct intel_overlay_error_state *error);
 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
-extern void intel_display_print_error_state(struct seq_file *m,
+extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
 					    struct drm_device *dev,
 					    struct intel_display_error_state *error);
 #endif
 /* On SNB platform, before reading ring registers forcewake bit
  * must be set to prevent GT core from power down and stale values being
  * returned.
- */
-void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
+ */
-void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
+void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
-int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
-int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
+void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
+int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
+int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
-int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
+/* intel_sideband.c */
+u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
+void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
+u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
+u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
+void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
+u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
+		   enum intel_sbi_destination destination);
-int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
+void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
+		     enum intel_sbi_destination destination);
-int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
+int vlv_gpu_freq(int ddr_freq, int val);
+int vlv_freq_opcode(int ddr_freq, int val);
-#define __i915_read(x, y) \
-	u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
+#define __i915_read(x) \
 	u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace);
-__i915_read(8, b)
+__i915_read(8)
-__i915_read(16, w)
+__i915_read(16)
-__i915_read(32, l)
-__i915_read(64, q)
+__i915_read(32)
-#undef __i915_read
+__i915_read(64)
+#undef __i915_read
-#define __i915_write(x, y) \
-	void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
+#define __i915_write(x) \
+	void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool trace);
-__i915_write(8, b)
+__i915_write(8)
-__i915_write(16, w)
+__i915_write(16)
-__i915_write(32, l)
+__i915_write(32)
-__i915_write(64, q)
+__i915_write(64)
 #undef __i915_write
-#define I915_READ8(reg)		i915_read8(dev_priv, (reg))
+#define I915_READ8(reg)		i915_read8(dev_priv, (reg), true)
-#define I915_WRITE8(reg, val)	i915_write8(dev_priv, (reg), (val))
+#define I915_WRITE8(reg, val)	i915_write8(dev_priv, (reg), (val), true)
-#define I915_READ16(reg)	i915_read16(dev_priv, (reg))
+#define I915_READ16(reg)	i915_read16(dev_priv, (reg), true)
-#define I915_WRITE16(reg, val)	i915_write16(dev_priv, (reg), (val))
+#define I915_WRITE16(reg, val)	i915_write16(dev_priv, (reg), (val), true)
-#define I915_READ16_NOTRACE(reg)	readw(dev_priv->regs + (reg))
+#define I915_READ16_NOTRACE(reg)	i915_read16(dev_priv, (reg), false)
-#define I915_WRITE16_NOTRACE(reg, val)	writew(val, dev_priv->regs + (reg))
+#define I915_WRITE16_NOTRACE(reg, val)	i915_write16(dev_priv, (reg), (val), false)
-#define I915_READ(reg)		i915_read32(dev_priv, (reg))
+#define I915_READ(reg)		i915_read32(dev_priv, (reg), true)

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_drv.h – Rev 3746 → 4104