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Rev 3480 | Rev 3746 | ||
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Line 96... | Line 96... | ||
96 | PORT_E, |
96 | PORT_E, |
97 | I915_MAX_PORTS |
97 | I915_MAX_PORTS |
98 | }; |
98 | }; |
99 | #define port_name(p) ((p) + 'A') |
99 | #define port_name(p) ((p) + 'A') |
Line -... | Line 100... | ||
- | 100 | ||
- | 101 | enum hpd_pin { |
|
- | 102 | HPD_NONE = 0, |
|
- | 103 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ |
|
- | 104 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
|
- | 105 | HPD_CRT, |
|
- | 106 | HPD_SDVO_B, |
|
- | 107 | HPD_SDVO_C, |
|
- | 108 | HPD_PORT_B, |
|
- | 109 | HPD_PORT_C, |
|
- | 110 | HPD_PORT_D, |
|
- | 111 | HPD_NUM_PINS |
|
- | 112 | }; |
|
100 | 113 | ||
101 | #define I915_GEM_GPU_DOMAINS \ |
114 | #define I915_GEM_GPU_DOMAINS \ |
102 | (I915_GEM_DOMAIN_RENDER | \ |
115 | (I915_GEM_DOMAIN_RENDER | \ |
103 | I915_GEM_DOMAIN_SAMPLER | \ |
116 | I915_GEM_DOMAIN_SAMPLER | \ |
104 | I915_GEM_DOMAIN_COMMAND | \ |
117 | I915_GEM_DOMAIN_COMMAND | \ |
105 | I915_GEM_DOMAIN_INSTRUCTION | \ |
118 | I915_GEM_DOMAIN_INSTRUCTION | \ |
Line 106... | Line 119... | ||
106 | I915_GEM_DOMAIN_VERTEX) |
119 | I915_GEM_DOMAIN_VERTEX) |
Line 107... | Line 120... | ||
107 | 120 | ||
108 | #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
121 | #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
109 | 122 | ||
Line 192... | Line 205... | ||
192 | struct drm_i915_master_private { |
205 | struct drm_i915_master_private { |
193 | drm_local_map_t *sarea; |
206 | drm_local_map_t *sarea; |
194 | struct _drm_i915_sarea *sarea_priv; |
207 | struct _drm_i915_sarea *sarea_priv; |
195 | }; |
208 | }; |
196 | #define I915_FENCE_REG_NONE -1 |
209 | #define I915_FENCE_REG_NONE -1 |
197 | #define I915_MAX_NUM_FENCES 16 |
210 | #define I915_MAX_NUM_FENCES 32 |
198 | /* 16 fences + sign bit for FENCE_REG_NONE */ |
211 | /* 32 fences + sign bit for FENCE_REG_NONE */ |
199 | #define I915_MAX_NUM_FENCE_BITS 5 |
212 | #define I915_MAX_NUM_FENCE_BITS 6 |
Line 200... | Line 213... | ||
200 | 213 | ||
201 | struct drm_i915_fence_reg { |
214 | struct drm_i915_fence_reg { |
202 | struct list_head lru_list; |
215 | struct list_head lru_list; |
203 | struct drm_i915_gem_object *obj; |
216 | struct drm_i915_gem_object *obj; |
Line 253... | Line 266... | ||
253 | struct drm_i915_error_ring { |
266 | struct drm_i915_error_ring { |
254 | struct drm_i915_error_object { |
267 | struct drm_i915_error_object { |
255 | int page_count; |
268 | int page_count; |
256 | u32 gtt_offset; |
269 | u32 gtt_offset; |
257 | u32 *pages[0]; |
270 | u32 *pages[0]; |
258 | } *ringbuffer, *batchbuffer; |
271 | } *ringbuffer, *batchbuffer, *ctx; |
259 | struct drm_i915_error_request { |
272 | struct drm_i915_error_request { |
260 | long jiffies; |
273 | long jiffies; |
261 | u32 seqno; |
274 | u32 seqno; |
262 | u32 tail; |
275 | u32 tail; |
263 | } *requests; |
276 | } *requests; |
Line 281... | Line 294... | ||
281 | u32 active_bo_count, pinned_bo_count; |
294 | u32 active_bo_count, pinned_bo_count; |
282 | struct intel_overlay_error_state *overlay; |
295 | struct intel_overlay_error_state *overlay; |
283 | struct intel_display_error_state *display; |
296 | struct intel_display_error_state *display; |
284 | }; |
297 | }; |
Line -... | Line 298... | ||
- | 298 | ||
- | 299 | struct intel_crtc_config; |
|
- | 300 | struct intel_crtc; |
|
285 | 301 | ||
286 | struct drm_i915_display_funcs { |
302 | struct drm_i915_display_funcs { |
287 | bool (*fbc_enabled)(struct drm_device *dev); |
303 | bool (*fbc_enabled)(struct drm_device *dev); |
288 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
304 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
289 | void (*disable_fbc)(struct drm_device *dev); |
305 | void (*disable_fbc)(struct drm_device *dev); |
Line 293... | Line 309... | ||
293 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, |
309 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, |
294 | uint32_t sprite_width, int pixel_size); |
310 | uint32_t sprite_width, int pixel_size); |
295 | void (*update_linetime_wm)(struct drm_device *dev, int pipe, |
311 | void (*update_linetime_wm)(struct drm_device *dev, int pipe, |
296 | struct drm_display_mode *mode); |
312 | struct drm_display_mode *mode); |
297 | void (*modeset_global_resources)(struct drm_device *dev); |
313 | void (*modeset_global_resources)(struct drm_device *dev); |
- | 314 | /* Returns the active state of the crtc, and if the crtc is active, |
|
- | 315 | * fills out the pipe-config with the hw state. */ |
|
- | 316 | bool (*get_pipe_config)(struct intel_crtc *, |
|
- | 317 | struct intel_crtc_config *); |
|
298 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
318 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
299 | struct drm_display_mode *mode, |
- | |
300 | struct drm_display_mode *adjusted_mode, |
- | |
301 | int x, int y, |
319 | int x, int y, |
302 | struct drm_framebuffer *old_fb); |
320 | struct drm_framebuffer *old_fb); |
303 | void (*crtc_enable)(struct drm_crtc *crtc); |
321 | void (*crtc_enable)(struct drm_crtc *crtc); |
304 | void (*crtc_disable)(struct drm_crtc *crtc); |
322 | void (*crtc_disable)(struct drm_crtc *crtc); |
305 | void (*off)(struct drm_crtc *crtc); |
323 | void (*off)(struct drm_crtc *crtc); |
Line 351... | Line 369... | ||
351 | DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \ |
369 | DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \ |
352 | DEV_INFO_FLAG(has_llc) |
370 | DEV_INFO_FLAG(has_llc) |
Line 353... | Line 371... | ||
353 | 371 | ||
354 | struct intel_device_info { |
372 | struct intel_device_info { |
- | 373 | u32 display_mmio_offset; |
|
355 | u32 display_mmio_offset; |
374 | u8 num_pipes:3; |
356 | u8 gen; |
375 | u8 gen; |
357 | u8 is_mobile:1; |
376 | u8 is_mobile:1; |
358 | u8 is_i85x:1; |
377 | u8 is_i85x:1; |
359 | u8 is_i915g:1; |
378 | u8 is_i915g:1; |
Line 440... | Line 459... | ||
440 | unsigned int num_entries); |
459 | unsigned int num_entries); |
441 | void (*insert_entries)(struct i915_hw_ppgtt *ppgtt, |
460 | void (*insert_entries)(struct i915_hw_ppgtt *ppgtt, |
442 | struct sg_table *st, |
461 | struct sg_table *st, |
443 | unsigned int pg_start, |
462 | unsigned int pg_start, |
444 | enum i915_cache_level cache_level); |
463 | enum i915_cache_level cache_level); |
- | 464 | int (*enable)(struct drm_device *dev); |
|
445 | void (*cleanup)(struct i915_hw_ppgtt *ppgtt); |
465 | void (*cleanup)(struct i915_hw_ppgtt *ppgtt); |
446 | }; |
466 | }; |
Line 447... | Line 467... | ||
447 | 467 | ||
Line 470... | Line 490... | ||
470 | enum intel_pch { |
490 | enum intel_pch { |
471 | PCH_NONE = 0, /* No PCH present */ |
491 | PCH_NONE = 0, /* No PCH present */ |
472 | PCH_IBX, /* Ibexpeak PCH */ |
492 | PCH_IBX, /* Ibexpeak PCH */ |
473 | PCH_CPT, /* Cougarpoint PCH */ |
493 | PCH_CPT, /* Cougarpoint PCH */ |
474 | PCH_LPT, /* Lynxpoint PCH */ |
494 | PCH_LPT, /* Lynxpoint PCH */ |
- | 495 | PCH_NOP, |
|
475 | }; |
496 | }; |
Line 476... | Line 497... | ||
476 | 497 | ||
477 | enum intel_sbi_destination { |
498 | enum intel_sbi_destination { |
478 | SBI_ICLK, |
499 | SBI_ICLK, |
Line 657... | Line 678... | ||
657 | /* The below variables an all the rps hw state are protected by |
678 | /* The below variables an all the rps hw state are protected by |
658 | * dev->struct mutext. */ |
679 | * dev->struct mutext. */ |
659 | u8 cur_delay; |
680 | u8 cur_delay; |
660 | u8 min_delay; |
681 | u8 min_delay; |
661 | u8 max_delay; |
682 | u8 max_delay; |
- | 683 | u8 hw_max; |
|
Line 662... | Line 684... | ||
662 | 684 | ||
Line 663... | Line 685... | ||
663 | struct delayed_work delayed_resume_work; |
685 | struct delayed_work delayed_resume_work; |
664 | 686 | ||
Line 913... | Line 935... | ||
913 | 935 | ||
914 | /* DPIO indirect register protection */ |
936 | /* DPIO indirect register protection */ |
Line 915... | Line 937... | ||
915 | struct mutex dpio_lock; |
937 | struct mutex dpio_lock; |
916 | - | ||
917 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
938 | |
918 | u32 pipestat[2]; |
939 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
Line 919... | Line -... | ||
919 | u32 irq_mask; |
- | |
920 | u32 gt_irq_mask; |
940 | u32 irq_mask; |
921 | 941 | u32 gt_irq_mask; |
|
- | 942 | ||
- | 943 | struct work_struct hotplug_work; |
|
- | 944 | bool enable_hotplug_processing; |
|
- | 945 | struct { |
|
- | 946 | unsigned long hpd_last_jiffies; |
|
- | 947 | int hpd_cnt; |
|
- | 948 | enum { |
|
- | 949 | HPD_ENABLED = 0, |
|
- | 950 | HPD_DISABLED = 1, |
|
Line 922... | Line -... | ||
922 | u32 hotplug_supported_mask; |
- | |
923 | struct work_struct hotplug_work; |
951 | HPD_MARK_DISABLED = 2 |
- | 952 | } hpd_mark; |
|
Line 924... | Line 953... | ||
924 | bool enable_hotplug_processing; |
953 | } hpd_stats[HPD_NUM_PINS]; |
925 | 954 | ||
926 | int num_pipe; |
955 | int num_pch_pll; |
927 | int num_pch_pll; |
956 | int num_plane; |
Line 936... | Line 965... | ||
936 | 965 | ||
937 | /* overlay */ |
966 | /* overlay */ |
938 | struct intel_overlay *overlay; |
967 | struct intel_overlay *overlay; |
Line -... | Line 968... | ||
- | 968 | unsigned int sprite_scaling_enabled; |
|
- | 969 | ||
- | 970 | /* backlight */ |
|
- | 971 | struct { |
|
- | 972 | int level; |
|
- | 973 | bool enabled; |
|
- | 974 | struct backlight_device *device; |
|
939 | unsigned int sprite_scaling_enabled; |
975 | } backlight; |
940 | - | ||
941 | /* LVDS info */ |
- | |
942 | int backlight_level; /* restore backlight to this value */ |
976 | |
943 | bool backlight_enabled; |
977 | /* LVDS info */ |
Line 944... | Line 978... | ||
944 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
978 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
945 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
979 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
946 | 980 | ||
947 | /* Feature bits from the VBIOS */ |
981 | /* Feature bits from the VBIOS */ |
948 | unsigned int int_tv_support:1; |
982 | unsigned int int_tv_support:1; |
949 | unsigned int lvds_dither:1; |
983 | unsigned int lvds_dither:1; |
950 | unsigned int lvds_vbt:1; |
984 | unsigned int lvds_vbt:1; |
- | 985 | unsigned int int_crt_support:1; |
|
951 | unsigned int int_crt_support:1; |
986 | unsigned int lvds_use_ssc:1; |
952 | unsigned int lvds_use_ssc:1; |
987 | unsigned int display_clock_mode:1; |
953 | unsigned int display_clock_mode:1; |
988 | unsigned int fdi_rx_polarity_inverted:1; |
954 | int lvds_ssc_freq; |
989 | int lvds_ssc_freq; |
955 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
990 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
Line 1040... | Line 1075... | ||
1040 | * The console may be contended at resume, but we don't |
1075 | * The console may be contended at resume, but we don't |
1041 | * want it to block on it. |
1076 | * want it to block on it. |
1042 | */ |
1077 | */ |
1043 | struct work_struct console_resume_work; |
1078 | struct work_struct console_resume_work; |
Line 1044... | Line -... | ||
1044 | - | ||
1045 | // struct backlight_device *backlight; |
- | |
1046 | 1079 | ||
1047 | struct drm_property *broadcast_rgb_property; |
1080 | struct drm_property *broadcast_rgb_property; |
Line 1048... | Line 1081... | ||
1048 | struct drm_property *force_audio_property; |
1081 | struct drm_property *force_audio_property; |
1049 | 1082 | ||
Line 1348... | Line 1381... | ||
1348 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
1381 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
Line 1349... | Line 1382... | ||
1349 | 1382 | ||
Line 1350... | Line 1383... | ||
1350 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
1383 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
- | 1384 | ||
Line 1351... | Line 1385... | ||
1351 | 1385 | #define HAS_DDI(dev) (IS_HASWELL(dev)) |
|
1352 | #define HAS_DDI(dev) (IS_HASWELL(dev)) |
1386 | #define HAS_POWER_WELL(dev) (IS_HASWELL(dev)) |
1353 | 1387 | ||
1354 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
1388 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
Line 1360... | Line 1394... | ||
1360 | 1394 | ||
1361 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
1395 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
1362 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
1396 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
1363 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
1397 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
- | 1398 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
|
1364 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
1399 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
Line 1365... | Line 1400... | ||
1365 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
1400 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
Line 1366... | Line 1401... | ||
1366 | 1401 | ||
Line 1532... | Line 1567... | ||
1532 | void i915_gem_lastclose(struct drm_device *dev); |
1567 | void i915_gem_lastclose(struct drm_device *dev); |
Line 1533... | Line 1568... | ||
1533 | 1568 | ||
1534 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
1569 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
1535 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
1570 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
1536 | { |
1571 | { |
1537 | struct scatterlist *sg = obj->pages->sgl; |
- | |
1538 | int nents = obj->pages->nents; |
- | |
1539 | while (nents > SG_MAX_SINGLE_ALLOC) { |
- | |
1540 | if (n < SG_MAX_SINGLE_ALLOC - 1) |
- | |
1541 | break; |
1572 | struct sg_page_iter sg_iter; |
1542 | 1573 | ||
1543 | sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1); |
- | |
1544 | n -= SG_MAX_SINGLE_ALLOC - 1; |
1574 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) |
1545 | nents -= SG_MAX_SINGLE_ALLOC - 1; |
1575 | return sg_page_iter_page(&sg_iter); |
1546 | } |
1576 | |
1547 | return sg_page(sg+n); |
1577 | return NULL; |
1548 | } |
1578 | } |
1549 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
1579 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
1550 | { |
1580 | { |
1551 | BUG_ON(obj->pages == NULL); |
1581 | BUG_ON(obj->pages == NULL); |
Line 1627... | Line 1657... | ||
1627 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1657 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1628 | int __must_check i915_gem_init(struct drm_device *dev); |
1658 | int __must_check i915_gem_init(struct drm_device *dev); |
1629 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
1659 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
1630 | void i915_gem_l3_remap(struct drm_device *dev); |
1660 | void i915_gem_l3_remap(struct drm_device *dev); |
1631 | void i915_gem_init_swizzling(struct drm_device *dev); |
1661 | void i915_gem_init_swizzling(struct drm_device *dev); |
1632 | void i915_gem_init_ppgtt(struct drm_device *dev); |
- | |
1633 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
1662 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
1634 | int __must_check i915_gpu_idle(struct drm_device *dev); |
1663 | int __must_check i915_gpu_idle(struct drm_device *dev); |
1635 | int __must_check i915_gem_idle(struct drm_device *dev); |
1664 | int __must_check i915_gem_idle(struct drm_device *dev); |
1636 | int i915_add_request(struct intel_ring_buffer *ring, |
1665 | int i915_add_request(struct intel_ring_buffer *ring, |
1637 | struct drm_file *file, |
1666 | struct drm_file *file, |
Line 1668... | Line 1697... | ||
1668 | 1697 | ||
1669 | 1698 | ||
Line -... | Line 1699... | ||
- | 1699 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, |
|
- | 1700 | struct drm_gem_object *gem_obj, int flags); |
|
1670 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, |
1701 | |
1671 | struct drm_gem_object *gem_obj, int flags); |
1702 | void i915_gem_restore_fences(struct drm_device *dev); |
1672 | 1703 | ||
1673 | /* i915_gem_context.c */ |
1704 | /* i915_gem_context.c */ |
1674 | void i915_gem_context_init(struct drm_device *dev); |
1705 | void i915_gem_context_init(struct drm_device *dev); |
Line 1719... | Line 1750... | ||
1719 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); |
1750 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); |
1720 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); |
1751 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); |
1721 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
1752 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
1722 | struct drm_i915_gem_object * |
1753 | struct drm_i915_gem_object * |
1723 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); |
1754 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); |
- | 1755 | struct drm_i915_gem_object * |
|
- | 1756 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, |
|
- | 1757 | u32 stolen_offset, |
|
- | 1758 | u32 gtt_offset, |
|
- | 1759 | u32 size); |
|
1724 | void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); |
1760 | void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); |
Line 1725... | Line 1761... | ||
1725 | 1761 | ||
1726 | /* i915_gem_tiling.c */ |
1762 | /* i915_gem_tiling.c */ |
1727 | inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
1763 | inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
Line 1849... | Line 1885... | ||
1849 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); |
1885 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); |
1850 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
1886 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
Line 1851... | Line 1887... | ||
1851 | 1887 | ||
1852 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
1888 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
- | 1889 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); |
|
- | 1890 | int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val); |
|
Line 1853... | Line 1891... | ||
1853 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); |
1891 | int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); |
1854 | 1892 | ||
Line 1855... | Line 1893... | ||
1855 | #define __i915_read(x, y) \ |
1893 | #define __i915_read(x, y) \ |
Line 1902... | Line 1940... | ||
1902 | return VLV_VGACNTRL; |
1940 | return VLV_VGACNTRL; |
1903 | else |
1941 | else |
1904 | return VGACNTRL; |
1942 | return VGACNTRL; |
1905 | } |
1943 | } |
Line -... | Line 1944... | ||
- | 1944 | ||
- | 1945 | static inline void __user *to_user_ptr(u64 address) |
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- | 1946 | { |
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- | 1947 | return (void __user *)(uintptr_t)address; |
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- | 1948 | } |
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- | 1949 | ||
- | 1950 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
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- | 1951 | { |
|
- | 1952 | unsigned long j = msecs_to_jiffies(m); |
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- | 1953 | ||
- | 1954 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
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- | 1955 | } |
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- | 1956 | ||
- | 1957 | static inline unsigned long |
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- | 1958 | timespec_to_jiffies_timeout(const struct timespec *value) |
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- | 1959 | { |
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- | 1960 | unsigned long j = timespec_to_jiffies(value); |
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- | 1961 | ||
- | 1962 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
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- | 1963 | } |
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- | 1964 | ||
1906 | 1965 | ||
1907 | typedef struct |
1966 | typedef struct |
1908 | { |
1967 | { |
1909 | int width; |
1968 | int width; |
1910 | int height; |
1969 | int height; |