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1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ |
2 | */ |
3 | /* |
3 | /* |
4 | * |
4 | * |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. |
6 | * All Rights Reserved. |
7 | * |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a |
8 | * Permission is hereby granted, free of charge, to any person obtaining a |
9 | * copy of this software and associated documentation files (the |
9 | * copy of this software and associated documentation files (the |
10 | * "Software"), to deal in the Software without restriction, including |
10 | * "Software"), to deal in the Software without restriction, including |
11 | * without limitation the rights to use, copy, modify, merge, publish, |
11 | * without limitation the rights to use, copy, modify, merge, publish, |
12 | * distribute, sub license, and/or sell copies of the Software, and to |
12 | * distribute, sub license, and/or sell copies of the Software, and to |
13 | * permit persons to whom the Software is furnished to do so, subject to |
13 | * permit persons to whom the Software is furnished to do so, subject to |
14 | * the following conditions: |
14 | * the following conditions: |
15 | * |
15 | * |
16 | * The above copyright notice and this permission notice (including the |
16 | * The above copyright notice and this permission notice (including the |
17 | * next paragraph) shall be included in all copies or substantial portions |
17 | * next paragraph) shall be included in all copies or substantial portions |
18 | * of the Software. |
18 | * of the Software. |
19 | * |
19 | * |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
27 | * |
27 | * |
28 | */ |
28 | */ |
29 | 29 | ||
30 | #ifndef _I915_DRV_H_ |
30 | #ifndef _I915_DRV_H_ |
31 | #define _I915_DRV_H_ |
31 | #define _I915_DRV_H_ |
32 | 32 | ||
33 | #include "i915_reg.h" |
33 | #include "i915_reg.h" |
34 | #include "intel_bios.h" |
34 | #include "intel_bios.h" |
35 | #include "intel_ringbuffer.h" |
35 | #include "intel_ringbuffer.h" |
36 | //#include |
36 | //#include |
37 | #include |
37 | #include |
38 | #include |
38 | #include |
39 | //#include |
39 | //#include |
40 | 40 | ||
41 | #include |
41 | #include |
42 | 42 | ||
43 | /* General customization: |
43 | /* General customization: |
44 | */ |
44 | */ |
45 | 45 | ||
46 | #define I915_TILING_NONE 0 |
46 | #define I915_TILING_NONE 0 |
47 | 47 | ||
48 | 48 | ||
49 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." |
49 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." |
50 | 50 | ||
51 | #define DRIVER_NAME "i915" |
51 | #define DRIVER_NAME "i915" |
52 | #define DRIVER_DESC "Intel Graphics" |
52 | #define DRIVER_DESC "Intel Graphics" |
53 | #define DRIVER_DATE "20080730" |
53 | #define DRIVER_DATE "20080730" |
54 | 54 | ||
55 | enum pipe { |
55 | enum pipe { |
56 | PIPE_A = 0, |
56 | PIPE_A = 0, |
57 | PIPE_B, |
57 | PIPE_B, |
58 | PIPE_C, |
58 | PIPE_C, |
59 | I915_MAX_PIPES |
59 | I915_MAX_PIPES |
60 | }; |
60 | }; |
61 | #define pipe_name(p) ((p) + 'A') |
61 | #define pipe_name(p) ((p) + 'A') |
62 | 62 | ||
63 | enum plane { |
63 | enum plane { |
64 | PLANE_A = 0, |
64 | PLANE_A = 0, |
65 | PLANE_B, |
65 | PLANE_B, |
66 | PLANE_C, |
66 | PLANE_C, |
67 | }; |
67 | }; |
68 | #define plane_name(p) ((p) + 'A') |
68 | #define plane_name(p) ((p) + 'A') |
69 | 69 | ||
70 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
70 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
71 | 71 | ||
72 | #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
72 | #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
73 | 73 | ||
74 | /* Interface history: |
74 | /* Interface history: |
75 | * |
75 | * |
76 | * 1.1: Original. |
76 | * 1.1: Original. |
77 | * 1.2: Add Power Management |
77 | * 1.2: Add Power Management |
78 | * 1.3: Add vblank support |
78 | * 1.3: Add vblank support |
79 | * 1.4: Fix cmdbuffer path, add heap destroy |
79 | * 1.4: Fix cmdbuffer path, add heap destroy |
80 | * 1.5: Add vblank pipe configuration |
80 | * 1.5: Add vblank pipe configuration |
81 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
81 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
82 | * - Support vertical blank on secondary display pipe |
82 | * - Support vertical blank on secondary display pipe |
83 | */ |
83 | */ |
84 | #define DRIVER_MAJOR 1 |
84 | #define DRIVER_MAJOR 1 |
85 | #define DRIVER_MINOR 6 |
85 | #define DRIVER_MINOR 6 |
86 | #define DRIVER_PATCHLEVEL 0 |
86 | #define DRIVER_PATCHLEVEL 0 |
87 | 87 | ||
88 | #define WATCH_COHERENCY 0 |
88 | #define WATCH_COHERENCY 0 |
89 | #define WATCH_LISTS 0 |
89 | #define WATCH_LISTS 0 |
90 | 90 | ||
91 | #define I915_GEM_PHYS_CURSOR_0 1 |
91 | #define I915_GEM_PHYS_CURSOR_0 1 |
92 | #define I915_GEM_PHYS_CURSOR_1 2 |
92 | #define I915_GEM_PHYS_CURSOR_1 2 |
93 | #define I915_GEM_PHYS_OVERLAY_REGS 3 |
93 | #define I915_GEM_PHYS_OVERLAY_REGS 3 |
94 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) |
94 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) |
95 | 95 | ||
96 | struct mem_block { |
96 | struct mem_block { |
97 | struct mem_block *next; |
97 | struct mem_block *next; |
98 | struct mem_block *prev; |
98 | struct mem_block *prev; |
99 | int start; |
99 | int start; |
100 | int size; |
100 | int size; |
101 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
101 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
102 | }; |
102 | }; |
103 | 103 | ||
104 | struct opregion_header; |
104 | struct opregion_header; |
105 | struct opregion_acpi; |
105 | struct opregion_acpi; |
106 | struct opregion_swsci; |
106 | struct opregion_swsci; |
107 | struct opregion_asle; |
107 | struct opregion_asle; |
- | 108 | struct drm_i915_private; |
|
108 | 109 | ||
109 | struct intel_opregion { |
110 | struct intel_opregion { |
110 | struct opregion_header *header; |
111 | struct opregion_header *header; |
111 | struct opregion_acpi *acpi; |
112 | struct opregion_acpi *acpi; |
112 | struct opregion_swsci *swsci; |
113 | struct opregion_swsci *swsci; |
113 | struct opregion_asle *asle; |
114 | struct opregion_asle *asle; |
114 | void *vbt; |
115 | void *vbt; |
115 | u32 __iomem *lid_state; |
116 | u32 __iomem *lid_state; |
116 | }; |
117 | }; |
117 | #define OPREGION_SIZE (8*1024) |
118 | #define OPREGION_SIZE (8*1024) |
118 | 119 | ||
119 | struct intel_overlay; |
120 | struct intel_overlay; |
120 | struct intel_overlay_error_state; |
121 | struct intel_overlay_error_state; |
121 | 122 | ||
122 | struct drm_i915_master_private { |
123 | struct drm_i915_master_private { |
123 | drm_local_map_t *sarea; |
124 | drm_local_map_t *sarea; |
124 | struct _drm_i915_sarea *sarea_priv; |
125 | struct _drm_i915_sarea *sarea_priv; |
125 | }; |
126 | }; |
126 | #define I915_FENCE_REG_NONE -1 |
127 | #define I915_FENCE_REG_NONE -1 |
- | 128 | #define I915_MAX_NUM_FENCES 16 |
|
- | 129 | /* 16 fences + sign bit for FENCE_REG_NONE */ |
|
- | 130 | #define I915_MAX_NUM_FENCE_BITS 5 |
|
127 | 131 | ||
128 | struct drm_i915_fence_reg { |
132 | struct drm_i915_fence_reg { |
129 | struct list_head lru_list; |
133 | struct list_head lru_list; |
130 | struct drm_i915_gem_object *obj; |
134 | struct drm_i915_gem_object *obj; |
131 | uint32_t setup_seqno; |
135 | uint32_t setup_seqno; |
132 | }; |
136 | }; |
133 | 137 | ||
134 | struct sdvo_device_mapping { |
138 | struct sdvo_device_mapping { |
135 | u8 initialized; |
139 | u8 initialized; |
136 | u8 dvo_port; |
140 | u8 dvo_port; |
137 | u8 slave_addr; |
141 | u8 slave_addr; |
138 | u8 dvo_wiring; |
142 | u8 dvo_wiring; |
139 | u8 i2c_pin; |
143 | u8 i2c_pin; |
140 | u8 i2c_speed; |
- | |
141 | u8 ddc_pin; |
144 | u8 ddc_pin; |
142 | }; |
145 | }; |
143 | 146 | ||
144 | struct intel_display_error_state; |
147 | struct intel_display_error_state; |
145 | 148 | ||
146 | struct drm_i915_error_state { |
149 | struct drm_i915_error_state { |
147 | u32 eir; |
150 | u32 eir; |
148 | u32 pgtbl_er; |
151 | u32 pgtbl_er; |
149 | u32 pipestat[I915_MAX_PIPES]; |
152 | u32 pipestat[I915_MAX_PIPES]; |
150 | u32 ipeir; |
153 | u32 ipeir; |
151 | u32 ipehr; |
154 | u32 ipehr; |
152 | u32 instdone; |
155 | u32 instdone; |
153 | u32 acthd; |
156 | u32 acthd; |
154 | u32 error; /* gen6+ */ |
157 | u32 error; /* gen6+ */ |
155 | u32 bcs_acthd; /* gen6+ blt engine */ |
158 | u32 bcs_acthd; /* gen6+ blt engine */ |
156 | u32 bcs_ipehr; |
159 | u32 bcs_ipehr; |
157 | u32 bcs_ipeir; |
160 | u32 bcs_ipeir; |
158 | u32 bcs_instdone; |
161 | u32 bcs_instdone; |
159 | u32 bcs_seqno; |
162 | u32 bcs_seqno; |
160 | u32 vcs_acthd; /* gen6+ bsd engine */ |
163 | u32 vcs_acthd; /* gen6+ bsd engine */ |
161 | u32 vcs_ipehr; |
164 | u32 vcs_ipehr; |
162 | u32 vcs_ipeir; |
165 | u32 vcs_ipeir; |
163 | u32 vcs_instdone; |
166 | u32 vcs_instdone; |
164 | u32 vcs_seqno; |
167 | u32 vcs_seqno; |
165 | u32 instpm; |
168 | u32 instpm; |
166 | u32 instps; |
169 | u32 instps; |
167 | u32 instdone1; |
170 | u32 instdone1; |
168 | u32 seqno; |
171 | u32 seqno; |
169 | u64 bbaddr; |
172 | u64 bbaddr; |
170 | u64 fence[16]; |
173 | u64 fence[I915_MAX_NUM_FENCES]; |
171 | struct timeval time; |
174 | struct timeval time; |
172 | struct drm_i915_error_object { |
175 | struct drm_i915_error_object { |
173 | int page_count; |
176 | int page_count; |
174 | u32 gtt_offset; |
177 | u32 gtt_offset; |
175 | u32 *pages[0]; |
178 | u32 *pages[0]; |
176 | } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS]; |
179 | } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS]; |
177 | struct drm_i915_error_buffer { |
180 | struct drm_i915_error_buffer { |
178 | u32 size; |
181 | u32 size; |
179 | u32 name; |
182 | u32 name; |
180 | u32 seqno; |
183 | u32 seqno; |
181 | u32 gtt_offset; |
184 | u32 gtt_offset; |
182 | u32 read_domains; |
185 | u32 read_domains; |
183 | u32 write_domain; |
186 | u32 write_domain; |
184 | s32 fence_reg:5; |
187 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
185 | s32 pinned:2; |
188 | s32 pinned:2; |
186 | u32 tiling:2; |
189 | u32 tiling:2; |
187 | u32 dirty:1; |
190 | u32 dirty:1; |
188 | u32 purgeable:1; |
191 | u32 purgeable:1; |
189 | u32 ring:4; |
192 | u32 ring:4; |
190 | u32 cache_level:2; |
193 | u32 cache_level:2; |
191 | } *active_bo, *pinned_bo; |
194 | } *active_bo, *pinned_bo; |
192 | u32 active_bo_count, pinned_bo_count; |
195 | u32 active_bo_count, pinned_bo_count; |
193 | struct intel_overlay_error_state *overlay; |
196 | struct intel_overlay_error_state *overlay; |
194 | struct intel_display_error_state *display; |
197 | struct intel_display_error_state *display; |
195 | }; |
198 | }; |
196 | 199 | ||
197 | struct drm_i915_display_funcs { |
200 | struct drm_i915_display_funcs { |
198 | void (*dpms)(struct drm_crtc *crtc, int mode); |
201 | void (*dpms)(struct drm_crtc *crtc, int mode); |
199 | bool (*fbc_enabled)(struct drm_device *dev); |
202 | bool (*fbc_enabled)(struct drm_device *dev); |
200 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
203 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
201 | void (*disable_fbc)(struct drm_device *dev); |
204 | void (*disable_fbc)(struct drm_device *dev); |
202 | int (*get_display_clock_speed)(struct drm_device *dev); |
205 | int (*get_display_clock_speed)(struct drm_device *dev); |
203 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
206 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
204 | void (*update_wm)(struct drm_device *dev); |
207 | void (*update_wm)(struct drm_device *dev); |
- | 208 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, |
|
- | 209 | uint32_t sprite_width, int pixel_size); |
|
205 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
210 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
206 | struct drm_display_mode *mode, |
211 | struct drm_display_mode *mode, |
207 | struct drm_display_mode *adjusted_mode, |
212 | struct drm_display_mode *adjusted_mode, |
208 | int x, int y, |
213 | int x, int y, |
209 | struct drm_framebuffer *old_fb); |
214 | struct drm_framebuffer *old_fb); |
- | 215 | void (*write_eld)(struct drm_connector *connector, |
|
- | 216 | struct drm_crtc *crtc); |
|
210 | void (*fdi_link_train)(struct drm_crtc *crtc); |
217 | void (*fdi_link_train)(struct drm_crtc *crtc); |
211 | void (*init_clock_gating)(struct drm_device *dev); |
218 | void (*init_clock_gating)(struct drm_device *dev); |
212 | void (*init_pch_clock_gating)(struct drm_device *dev); |
219 | void (*init_pch_clock_gating)(struct drm_device *dev); |
213 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
220 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
214 | struct drm_framebuffer *fb, |
221 | struct drm_framebuffer *fb, |
215 | struct drm_i915_gem_object *obj); |
222 | struct drm_i915_gem_object *obj); |
216 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
223 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
217 | int x, int y); |
224 | int x, int y); |
- | 225 | void (*force_wake_get)(struct drm_i915_private *dev_priv); |
|
- | 226 | void (*force_wake_put)(struct drm_i915_private *dev_priv); |
|
218 | /* clock updates for mode set */ |
227 | /* clock updates for mode set */ |
219 | /* cursor updates */ |
228 | /* cursor updates */ |
220 | /* render clock increase/decrease */ |
229 | /* render clock increase/decrease */ |
221 | /* display clock increase/decrease */ |
230 | /* display clock increase/decrease */ |
222 | /* pll clock increase/decrease */ |
231 | /* pll clock increase/decrease */ |
223 | }; |
232 | }; |
224 | 233 | ||
225 | struct intel_device_info { |
234 | struct intel_device_info { |
226 | u8 gen; |
235 | u8 gen; |
227 | u8 is_mobile : 1; |
236 | u8 is_mobile:1; |
228 | u8 is_i85x : 1; |
237 | u8 is_i85x:1; |
229 | u8 is_i915g : 1; |
238 | u8 is_i915g:1; |
230 | u8 is_i945gm : 1; |
239 | u8 is_i945gm:1; |
231 | u8 is_g33 : 1; |
240 | u8 is_g33:1; |
232 | u8 need_gfx_hws : 1; |
241 | u8 need_gfx_hws:1; |
233 | u8 is_g4x : 1; |
242 | u8 is_g4x:1; |
234 | u8 is_pineview : 1; |
243 | u8 is_pineview:1; |
235 | u8 is_broadwater : 1; |
244 | u8 is_broadwater:1; |
236 | u8 is_crestline : 1; |
245 | u8 is_crestline:1; |
237 | u8 is_ivybridge : 1; |
246 | u8 is_ivybridge:1; |
238 | u8 has_fbc : 1; |
247 | u8 has_fbc:1; |
239 | u8 has_pipe_cxsr : 1; |
248 | u8 has_pipe_cxsr:1; |
240 | u8 has_hotplug : 1; |
249 | u8 has_hotplug:1; |
241 | u8 cursor_needs_physical : 1; |
250 | u8 cursor_needs_physical:1; |
242 | u8 has_overlay : 1; |
251 | u8 has_overlay:1; |
243 | u8 overlay_needs_physical : 1; |
252 | u8 overlay_needs_physical:1; |
244 | u8 supports_tv : 1; |
253 | u8 supports_tv:1; |
245 | u8 has_bsd_ring : 1; |
254 | u8 has_bsd_ring:1; |
246 | u8 has_blt_ring : 1; |
255 | u8 has_blt_ring:1; |
247 | }; |
256 | }; |
248 | 257 | ||
249 | enum no_fbc_reason { |
258 | enum no_fbc_reason { |
250 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
259 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
251 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
260 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
252 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ |
261 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ |
253 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ |
262 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ |
254 | FBC_BAD_PLANE, /* fbc not supported on plane */ |
263 | FBC_BAD_PLANE, /* fbc not supported on plane */ |
255 | FBC_NOT_TILED, /* buffer not tiled */ |
264 | FBC_NOT_TILED, /* buffer not tiled */ |
256 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
265 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
257 | FBC_MODULE_PARAM, |
266 | FBC_MODULE_PARAM, |
258 | }; |
267 | }; |
259 | 268 | ||
260 | enum intel_pch { |
269 | enum intel_pch { |
261 | PCH_IBX, /* Ibexpeak PCH */ |
270 | PCH_IBX, /* Ibexpeak PCH */ |
262 | PCH_CPT, /* Cougarpoint PCH */ |
271 | PCH_CPT, /* Cougarpoint PCH */ |
263 | }; |
272 | }; |
264 | 273 | ||
265 | #define QUIRK_PIPEA_FORCE (1<<0) |
274 | #define QUIRK_PIPEA_FORCE (1<<0) |
266 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
275 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
267 | 276 | ||
268 | struct intel_fbdev; |
277 | struct intel_fbdev; |
269 | struct intel_fbc_work; |
278 | struct intel_fbc_work; |
270 | 279 | ||
271 | typedef struct drm_i915_private { |
280 | typedef struct drm_i915_private { |
272 | struct drm_device *dev; |
281 | struct drm_device *dev; |
273 | 282 | ||
274 | const struct intel_device_info *info; |
283 | const struct intel_device_info *info; |
275 | 284 | ||
276 | int has_gem; |
285 | int has_gem; |
277 | int relative_constants_mode; |
286 | int relative_constants_mode; |
278 | 287 | ||
279 | void __iomem *regs; |
288 | void __iomem *regs; |
- | 289 | /** gt_fifo_count and the subsequent register write are synchronized |
|
- | 290 | * with dev->struct_mutex. */ |
|
280 | u32 gt_fifo_count; |
291 | unsigned gt_fifo_count; |
- | 292 | /** forcewake_count is protected by gt_lock */ |
|
- | 293 | unsigned forcewake_count; |
|
- | 294 | /** gt_lock is also taken in irq contexts. */ |
|
- | 295 | spinlock_t gt_lock; |
|
281 | 296 | ||
282 | struct intel_gmbus { |
297 | struct intel_gmbus { |
283 | struct i2c_adapter adapter; |
298 | struct i2c_adapter adapter; |
284 | struct i2c_adapter *force_bit; |
299 | struct i2c_adapter *force_bit; |
285 | u32 reg0; |
300 | u32 reg0; |
286 | } *gmbus; |
301 | } *gmbus; |
287 | 302 | ||
288 | struct pci_dev *bridge_dev; |
303 | struct pci_dev *bridge_dev; |
289 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
304 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
290 | uint32_t next_seqno; |
305 | uint32_t next_seqno; |
291 | 306 | ||
292 | drm_dma_handle_t *status_page_dmah; |
307 | drm_dma_handle_t *status_page_dmah; |
293 | uint32_t counter; |
308 | uint32_t counter; |
294 | drm_local_map_t hws_map; |
309 | drm_local_map_t hws_map; |
295 | struct drm_i915_gem_object *pwrctx; |
310 | struct drm_i915_gem_object *pwrctx; |
296 | struct drm_i915_gem_object *renderctx; |
311 | struct drm_i915_gem_object *renderctx; |
297 | 312 | ||
298 | // struct resource mch_res; |
313 | // struct resource mch_res; |
299 | 314 | ||
300 | unsigned int cpp; |
315 | unsigned int cpp; |
301 | int back_offset; |
316 | int back_offset; |
302 | int front_offset; |
317 | int front_offset; |
303 | int current_page; |
318 | int current_page; |
304 | int page_flipping; |
319 | int page_flipping; |
305 | 320 | ||
306 | atomic_t irq_received; |
321 | atomic_t irq_received; |
307 | 322 | ||
308 | /* protects the irq masks */ |
323 | /* protects the irq masks */ |
309 | spinlock_t irq_lock; |
324 | spinlock_t irq_lock; |
310 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
325 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
311 | u32 pipestat[2]; |
326 | u32 pipestat[2]; |
312 | u32 irq_mask; |
327 | u32 irq_mask; |
313 | u32 gt_irq_mask; |
328 | u32 gt_irq_mask; |
314 | u32 pch_irq_mask; |
329 | u32 pch_irq_mask; |
315 | 330 | ||
316 | u32 hotplug_supported_mask; |
331 | u32 hotplug_supported_mask; |
317 | // struct work_struct hotplug_work; |
332 | // struct work_struct hotplug_work; |
318 | 333 | ||
319 | int tex_lru_log_granularity; |
334 | int tex_lru_log_granularity; |
320 | int allow_batchbuffer; |
335 | int allow_batchbuffer; |
321 | struct mem_block *agp_heap; |
336 | struct mem_block *agp_heap; |
322 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
337 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
323 | int vblank_pipe; |
338 | int vblank_pipe; |
324 | int num_pipe; |
339 | int num_pipe; |
325 | 340 | ||
326 | /* For hangcheck timer */ |
341 | /* For hangcheck timer */ |
327 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
342 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
328 | struct timer_list hangcheck_timer; |
343 | struct timer_list hangcheck_timer; |
329 | int hangcheck_count; |
344 | int hangcheck_count; |
330 | uint32_t last_acthd; |
345 | uint32_t last_acthd; |
- | 346 | uint32_t last_acthd_bsd; |
|
- | 347 | uint32_t last_acthd_blt; |
|
331 | uint32_t last_instdone; |
348 | uint32_t last_instdone; |
332 | uint32_t last_instdone1; |
349 | uint32_t last_instdone1; |
333 | 350 | ||
334 | unsigned long cfb_size; |
351 | unsigned long cfb_size; |
335 | unsigned int cfb_fb; |
352 | unsigned int cfb_fb; |
336 | enum plane cfb_plane; |
353 | enum plane cfb_plane; |
337 | int cfb_y; |
354 | int cfb_y; |
338 | // struct intel_fbc_work *fbc_work; |
355 | // struct intel_fbc_work *fbc_work; |
339 | 356 | ||
340 | struct intel_opregion opregion; |
357 | struct intel_opregion opregion; |
341 | 358 | ||
342 | /* overlay */ |
359 | /* overlay */ |
343 | // struct intel_overlay *overlay; |
360 | // struct intel_overlay *overlay; |
- | 361 | bool sprite_scaling_enabled; |
|
344 | 362 | ||
345 | /* LVDS info */ |
363 | /* LVDS info */ |
346 | int backlight_level; /* restore backlight to this value */ |
364 | int backlight_level; /* restore backlight to this value */ |
347 | bool backlight_enabled; |
365 | bool backlight_enabled; |
348 | struct drm_display_mode *panel_fixed_mode; |
- | |
349 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
366 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
350 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
367 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
351 | 368 | ||
352 | /* Feature bits from the VBIOS */ |
369 | /* Feature bits from the VBIOS */ |
353 | unsigned int int_tv_support:1; |
370 | unsigned int int_tv_support:1; |
354 | unsigned int lvds_dither:1; |
371 | unsigned int lvds_dither:1; |
355 | unsigned int lvds_vbt:1; |
372 | unsigned int lvds_vbt:1; |
356 | unsigned int int_crt_support:1; |
373 | unsigned int int_crt_support:1; |
357 | unsigned int lvds_use_ssc:1; |
374 | unsigned int lvds_use_ssc:1; |
- | 375 | unsigned int display_clock_mode:1; |
|
358 | int lvds_ssc_freq; |
376 | int lvds_ssc_freq; |
359 | struct { |
377 | struct { |
360 | int rate; |
378 | int rate; |
361 | int lanes; |
379 | int lanes; |
362 | int preemphasis; |
380 | int preemphasis; |
363 | int vswing; |
381 | int vswing; |
364 | 382 | ||
365 | bool initialized; |
383 | bool initialized; |
366 | bool support; |
384 | bool support; |
367 | int bpp; |
385 | int bpp; |
368 | struct edp_power_seq pps; |
386 | struct edp_power_seq pps; |
369 | } edp; |
387 | } edp; |
370 | bool no_aux_handshake; |
388 | bool no_aux_handshake; |
371 | 389 | ||
372 | // struct notifier_block lid_notifier; |
390 | // struct notifier_block lid_notifier; |
373 | 391 | ||
374 | int crt_ddc_pin; |
392 | int crt_ddc_pin; |
375 | struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
393 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
376 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
394 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
377 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
395 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
378 | 396 | ||
379 | unsigned int fsb_freq, mem_freq, is_ddr3; |
397 | unsigned int fsb_freq, mem_freq, is_ddr3; |
380 | 398 | ||
381 | spinlock_t error_lock; |
399 | spinlock_t error_lock; |
382 | // struct drm_i915_error_state *first_error; |
400 | // struct drm_i915_error_state *first_error; |
383 | // struct work_struct error_work; |
401 | // struct work_struct error_work; |
384 | // struct completion error_completion; |
402 | // struct completion error_completion; |
385 | // struct workqueue_struct *wq; |
403 | // struct workqueue_struct *wq; |
386 | 404 | ||
387 | /* Display functions */ |
405 | /* Display functions */ |
388 | struct drm_i915_display_funcs display; |
406 | struct drm_i915_display_funcs display; |
389 | 407 | ||
390 | /* PCH chipset type */ |
408 | /* PCH chipset type */ |
391 | enum intel_pch pch_type; |
409 | enum intel_pch pch_type; |
392 | 410 | ||
393 | unsigned long quirks; |
411 | unsigned long quirks; |
394 | 412 | ||
395 | /* Register state */ |
413 | /* Register state */ |
396 | bool modeset_on_lid; |
414 | bool modeset_on_lid; |
397 | u8 saveLBB; |
415 | u8 saveLBB; |
398 | u32 saveDSPACNTR; |
416 | u32 saveDSPACNTR; |
399 | u32 saveDSPBCNTR; |
417 | u32 saveDSPBCNTR; |
400 | u32 saveDSPARB; |
418 | u32 saveDSPARB; |
401 | u32 saveHWS; |
419 | u32 saveHWS; |
402 | u32 savePIPEACONF; |
420 | u32 savePIPEACONF; |
403 | u32 savePIPEBCONF; |
421 | u32 savePIPEBCONF; |
404 | u32 savePIPEASRC; |
422 | u32 savePIPEASRC; |
405 | u32 savePIPEBSRC; |
423 | u32 savePIPEBSRC; |
406 | u32 saveFPA0; |
424 | u32 saveFPA0; |
407 | u32 saveFPA1; |
425 | u32 saveFPA1; |
408 | u32 saveDPLL_A; |
426 | u32 saveDPLL_A; |
409 | u32 saveDPLL_A_MD; |
427 | u32 saveDPLL_A_MD; |
410 | u32 saveHTOTAL_A; |
428 | u32 saveHTOTAL_A; |
411 | u32 saveHBLANK_A; |
429 | u32 saveHBLANK_A; |
412 | u32 saveHSYNC_A; |
430 | u32 saveHSYNC_A; |
413 | u32 saveVTOTAL_A; |
431 | u32 saveVTOTAL_A; |
414 | u32 saveVBLANK_A; |
432 | u32 saveVBLANK_A; |
415 | u32 saveVSYNC_A; |
433 | u32 saveVSYNC_A; |
416 | u32 saveBCLRPAT_A; |
434 | u32 saveBCLRPAT_A; |
417 | u32 saveTRANSACONF; |
435 | u32 saveTRANSACONF; |
418 | u32 saveTRANS_HTOTAL_A; |
436 | u32 saveTRANS_HTOTAL_A; |
419 | u32 saveTRANS_HBLANK_A; |
437 | u32 saveTRANS_HBLANK_A; |
420 | u32 saveTRANS_HSYNC_A; |
438 | u32 saveTRANS_HSYNC_A; |
421 | u32 saveTRANS_VTOTAL_A; |
439 | u32 saveTRANS_VTOTAL_A; |
422 | u32 saveTRANS_VBLANK_A; |
440 | u32 saveTRANS_VBLANK_A; |
423 | u32 saveTRANS_VSYNC_A; |
441 | u32 saveTRANS_VSYNC_A; |
424 | u32 savePIPEASTAT; |
442 | u32 savePIPEASTAT; |
425 | u32 saveDSPASTRIDE; |
443 | u32 saveDSPASTRIDE; |
426 | u32 saveDSPASIZE; |
444 | u32 saveDSPASIZE; |
427 | u32 saveDSPAPOS; |
445 | u32 saveDSPAPOS; |
428 | u32 saveDSPAADDR; |
446 | u32 saveDSPAADDR; |
429 | u32 saveDSPASURF; |
447 | u32 saveDSPASURF; |
430 | u32 saveDSPATILEOFF; |
448 | u32 saveDSPATILEOFF; |
431 | u32 savePFIT_PGM_RATIOS; |
449 | u32 savePFIT_PGM_RATIOS; |
432 | u32 saveBLC_HIST_CTL; |
450 | u32 saveBLC_HIST_CTL; |
433 | u32 saveBLC_PWM_CTL; |
451 | u32 saveBLC_PWM_CTL; |
434 | u32 saveBLC_PWM_CTL2; |
452 | u32 saveBLC_PWM_CTL2; |
435 | u32 saveBLC_CPU_PWM_CTL; |
453 | u32 saveBLC_CPU_PWM_CTL; |
436 | u32 saveBLC_CPU_PWM_CTL2; |
454 | u32 saveBLC_CPU_PWM_CTL2; |
437 | u32 saveFPB0; |
455 | u32 saveFPB0; |
438 | u32 saveFPB1; |
456 | u32 saveFPB1; |
439 | u32 saveDPLL_B; |
457 | u32 saveDPLL_B; |
440 | u32 saveDPLL_B_MD; |
458 | u32 saveDPLL_B_MD; |
441 | u32 saveHTOTAL_B; |
459 | u32 saveHTOTAL_B; |
442 | u32 saveHBLANK_B; |
460 | u32 saveHBLANK_B; |
443 | u32 saveHSYNC_B; |
461 | u32 saveHSYNC_B; |
444 | u32 saveVTOTAL_B; |
462 | u32 saveVTOTAL_B; |
445 | u32 saveVBLANK_B; |
463 | u32 saveVBLANK_B; |
446 | u32 saveVSYNC_B; |
464 | u32 saveVSYNC_B; |
447 | u32 saveBCLRPAT_B; |
465 | u32 saveBCLRPAT_B; |
448 | u32 saveTRANSBCONF; |
466 | u32 saveTRANSBCONF; |
449 | u32 saveTRANS_HTOTAL_B; |
467 | u32 saveTRANS_HTOTAL_B; |
450 | u32 saveTRANS_HBLANK_B; |
468 | u32 saveTRANS_HBLANK_B; |
451 | u32 saveTRANS_HSYNC_B; |
469 | u32 saveTRANS_HSYNC_B; |
452 | u32 saveTRANS_VTOTAL_B; |
470 | u32 saveTRANS_VTOTAL_B; |
453 | u32 saveTRANS_VBLANK_B; |
471 | u32 saveTRANS_VBLANK_B; |
454 | u32 saveTRANS_VSYNC_B; |
472 | u32 saveTRANS_VSYNC_B; |
455 | u32 savePIPEBSTAT; |
473 | u32 savePIPEBSTAT; |
456 | u32 saveDSPBSTRIDE; |
474 | u32 saveDSPBSTRIDE; |
457 | u32 saveDSPBSIZE; |
475 | u32 saveDSPBSIZE; |
458 | u32 saveDSPBPOS; |
476 | u32 saveDSPBPOS; |
459 | u32 saveDSPBADDR; |
477 | u32 saveDSPBADDR; |
460 | u32 saveDSPBSURF; |
478 | u32 saveDSPBSURF; |
461 | u32 saveDSPBTILEOFF; |
479 | u32 saveDSPBTILEOFF; |
462 | u32 saveVGA0; |
480 | u32 saveVGA0; |
463 | u32 saveVGA1; |
481 | u32 saveVGA1; |
464 | u32 saveVGA_PD; |
482 | u32 saveVGA_PD; |
465 | u32 saveVGACNTRL; |
483 | u32 saveVGACNTRL; |
466 | u32 saveADPA; |
484 | u32 saveADPA; |
467 | u32 saveLVDS; |
485 | u32 saveLVDS; |
468 | u32 savePP_ON_DELAYS; |
486 | u32 savePP_ON_DELAYS; |
469 | u32 savePP_OFF_DELAYS; |
487 | u32 savePP_OFF_DELAYS; |
470 | u32 saveDVOA; |
488 | u32 saveDVOA; |
471 | u32 saveDVOB; |
489 | u32 saveDVOB; |
472 | u32 saveDVOC; |
490 | u32 saveDVOC; |
473 | u32 savePP_ON; |
491 | u32 savePP_ON; |
474 | u32 savePP_OFF; |
492 | u32 savePP_OFF; |
475 | u32 savePP_CONTROL; |
493 | u32 savePP_CONTROL; |
476 | u32 savePP_DIVISOR; |
494 | u32 savePP_DIVISOR; |
477 | u32 savePFIT_CONTROL; |
495 | u32 savePFIT_CONTROL; |
478 | u32 save_palette_a[256]; |
496 | u32 save_palette_a[256]; |
479 | u32 save_palette_b[256]; |
497 | u32 save_palette_b[256]; |
480 | u32 saveDPFC_CB_BASE; |
498 | u32 saveDPFC_CB_BASE; |
481 | u32 saveFBC_CFB_BASE; |
499 | u32 saveFBC_CFB_BASE; |
482 | u32 saveFBC_LL_BASE; |
500 | u32 saveFBC_LL_BASE; |
483 | u32 saveFBC_CONTROL; |
501 | u32 saveFBC_CONTROL; |
484 | u32 saveFBC_CONTROL2; |
502 | u32 saveFBC_CONTROL2; |
485 | u32 saveIER; |
503 | u32 saveIER; |
486 | u32 saveIIR; |
504 | u32 saveIIR; |
487 | u32 saveIMR; |
505 | u32 saveIMR; |
488 | u32 saveDEIER; |
506 | u32 saveDEIER; |
489 | u32 saveDEIMR; |
507 | u32 saveDEIMR; |
490 | u32 saveGTIER; |
508 | u32 saveGTIER; |
491 | u32 saveGTIMR; |
509 | u32 saveGTIMR; |
492 | u32 saveFDI_RXA_IMR; |
510 | u32 saveFDI_RXA_IMR; |
493 | u32 saveFDI_RXB_IMR; |
511 | u32 saveFDI_RXB_IMR; |
494 | u32 saveCACHE_MODE_0; |
512 | u32 saveCACHE_MODE_0; |
495 | u32 saveMI_ARB_STATE; |
513 | u32 saveMI_ARB_STATE; |
496 | u32 saveSWF0[16]; |
514 | u32 saveSWF0[16]; |
497 | u32 saveSWF1[16]; |
515 | u32 saveSWF1[16]; |
498 | u32 saveSWF2[3]; |
516 | u32 saveSWF2[3]; |
499 | u8 saveMSR; |
517 | u8 saveMSR; |
500 | u8 saveSR[8]; |
518 | u8 saveSR[8]; |
501 | u8 saveGR[25]; |
519 | u8 saveGR[25]; |
502 | u8 saveAR_INDEX; |
520 | u8 saveAR_INDEX; |
503 | u8 saveAR[21]; |
521 | u8 saveAR[21]; |
504 | u8 saveDACMASK; |
522 | u8 saveDACMASK; |
505 | u8 saveCR[37]; |
523 | u8 saveCR[37]; |
506 | uint64_t saveFENCE[16]; |
524 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
507 | u32 saveCURACNTR; |
525 | u32 saveCURACNTR; |
508 | u32 saveCURAPOS; |
526 | u32 saveCURAPOS; |
509 | u32 saveCURABASE; |
527 | u32 saveCURABASE; |
510 | u32 saveCURBCNTR; |
528 | u32 saveCURBCNTR; |
511 | u32 saveCURBPOS; |
529 | u32 saveCURBPOS; |
512 | u32 saveCURBBASE; |
530 | u32 saveCURBBASE; |
513 | u32 saveCURSIZE; |
531 | u32 saveCURSIZE; |
514 | u32 saveDP_B; |
532 | u32 saveDP_B; |
515 | u32 saveDP_C; |
533 | u32 saveDP_C; |
516 | u32 saveDP_D; |
534 | u32 saveDP_D; |
517 | u32 savePIPEA_GMCH_DATA_M; |
535 | u32 savePIPEA_GMCH_DATA_M; |
518 | u32 savePIPEB_GMCH_DATA_M; |
536 | u32 savePIPEB_GMCH_DATA_M; |
519 | u32 savePIPEA_GMCH_DATA_N; |
537 | u32 savePIPEA_GMCH_DATA_N; |
520 | u32 savePIPEB_GMCH_DATA_N; |
538 | u32 savePIPEB_GMCH_DATA_N; |
521 | u32 savePIPEA_DP_LINK_M; |
539 | u32 savePIPEA_DP_LINK_M; |
522 | u32 savePIPEB_DP_LINK_M; |
540 | u32 savePIPEB_DP_LINK_M; |
523 | u32 savePIPEA_DP_LINK_N; |
541 | u32 savePIPEA_DP_LINK_N; |
524 | u32 savePIPEB_DP_LINK_N; |
542 | u32 savePIPEB_DP_LINK_N; |
525 | u32 saveFDI_RXA_CTL; |
543 | u32 saveFDI_RXA_CTL; |
526 | u32 saveFDI_TXA_CTL; |
544 | u32 saveFDI_TXA_CTL; |
527 | u32 saveFDI_RXB_CTL; |
545 | u32 saveFDI_RXB_CTL; |
528 | u32 saveFDI_TXB_CTL; |
546 | u32 saveFDI_TXB_CTL; |
529 | u32 savePFA_CTL_1; |
547 | u32 savePFA_CTL_1; |
530 | u32 savePFB_CTL_1; |
548 | u32 savePFB_CTL_1; |
531 | u32 savePFA_WIN_SZ; |
549 | u32 savePFA_WIN_SZ; |
532 | u32 savePFB_WIN_SZ; |
550 | u32 savePFB_WIN_SZ; |
533 | u32 savePFA_WIN_POS; |
551 | u32 savePFA_WIN_POS; |
534 | u32 savePFB_WIN_POS; |
552 | u32 savePFB_WIN_POS; |
535 | u32 savePCH_DREF_CONTROL; |
553 | u32 savePCH_DREF_CONTROL; |
536 | u32 saveDISP_ARB_CTL; |
554 | u32 saveDISP_ARB_CTL; |
537 | u32 savePIPEA_DATA_M1; |
555 | u32 savePIPEA_DATA_M1; |
538 | u32 savePIPEA_DATA_N1; |
556 | u32 savePIPEA_DATA_N1; |
539 | u32 savePIPEA_LINK_M1; |
557 | u32 savePIPEA_LINK_M1; |
540 | u32 savePIPEA_LINK_N1; |
558 | u32 savePIPEA_LINK_N1; |
541 | u32 savePIPEB_DATA_M1; |
559 | u32 savePIPEB_DATA_M1; |
542 | u32 savePIPEB_DATA_N1; |
560 | u32 savePIPEB_DATA_N1; |
543 | u32 savePIPEB_LINK_M1; |
561 | u32 savePIPEB_LINK_M1; |
544 | u32 savePIPEB_LINK_N1; |
562 | u32 savePIPEB_LINK_N1; |
545 | u32 saveMCHBAR_RENDER_STANDBY; |
563 | u32 saveMCHBAR_RENDER_STANDBY; |
546 | u32 savePCH_PORT_HOTPLUG; |
564 | u32 savePCH_PORT_HOTPLUG; |
547 | 565 | ||
548 | struct { |
566 | struct { |
549 | /** Bridge to intel-gtt-ko */ |
567 | /** Bridge to intel-gtt-ko */ |
550 | const struct intel_gtt *gtt; |
568 | const struct intel_gtt *gtt; |
551 | /** Memory allocator for GTT stolen memory */ |
569 | /** Memory allocator for GTT stolen memory */ |
552 | struct drm_mm stolen; |
570 | struct drm_mm stolen; |
553 | /** Memory allocator for GTT */ |
571 | /** Memory allocator for GTT */ |
554 | struct drm_mm gtt_space; |
572 | struct drm_mm gtt_space; |
555 | /** List of all objects in gtt_space. Used to restore gtt |
573 | /** List of all objects in gtt_space. Used to restore gtt |
556 | * mappings on resume */ |
574 | * mappings on resume */ |
557 | struct list_head gtt_list; |
575 | struct list_head gtt_list; |
558 | 576 | ||
559 | /** Usable portion of the GTT for GEM */ |
577 | /** Usable portion of the GTT for GEM */ |
560 | unsigned long gtt_start; |
578 | unsigned long gtt_start; |
561 | unsigned long gtt_mappable_end; |
579 | unsigned long gtt_mappable_end; |
562 | unsigned long gtt_end; |
580 | unsigned long gtt_end; |
563 | 581 | ||
564 | // struct io_mapping *gtt_mapping; |
582 | // struct io_mapping *gtt_mapping; |
565 | int gtt_mtrr; |
583 | int gtt_mtrr; |
566 | 584 | ||
567 | // struct shrinker inactive_shrinker; |
585 | // struct shrinker inactive_shrinker; |
568 | 586 | ||
569 | /** |
587 | /** |
570 | * List of objects currently involved in rendering. |
588 | * List of objects currently involved in rendering. |
571 | * |
589 | * |
572 | * Includes buffers having the contents of their GPU caches |
590 | * Includes buffers having the contents of their GPU caches |
573 | * flushed, not necessarily primitives. last_rendering_seqno |
591 | * flushed, not necessarily primitives. last_rendering_seqno |
574 | * represents when the rendering involved will be completed. |
592 | * represents when the rendering involved will be completed. |
575 | * |
593 | * |
576 | * A reference is held on the buffer while on this list. |
594 | * A reference is held on the buffer while on this list. |
577 | */ |
595 | */ |
578 | struct list_head active_list; |
596 | struct list_head active_list; |
579 | 597 | ||
580 | /** |
598 | /** |
581 | * List of objects which are not in the ringbuffer but which |
599 | * List of objects which are not in the ringbuffer but which |
582 | * still have a write_domain which needs to be flushed before |
600 | * still have a write_domain which needs to be flushed before |
583 | * unbinding. |
601 | * unbinding. |
584 | * |
602 | * |
585 | * last_rendering_seqno is 0 while an object is in this list. |
603 | * last_rendering_seqno is 0 while an object is in this list. |
586 | * |
604 | * |
587 | * A reference is held on the buffer while on this list. |
605 | * A reference is held on the buffer while on this list. |
588 | */ |
606 | */ |
589 | struct list_head flushing_list; |
607 | struct list_head flushing_list; |
590 | 608 | ||
591 | /** |
609 | /** |
592 | * LRU list of objects which are not in the ringbuffer and |
610 | * LRU list of objects which are not in the ringbuffer and |
593 | * are ready to unbind, but are still in the GTT. |
611 | * are ready to unbind, but are still in the GTT. |
594 | * |
612 | * |
595 | * last_rendering_seqno is 0 while an object is in this list. |
613 | * last_rendering_seqno is 0 while an object is in this list. |
596 | * |
614 | * |
597 | * A reference is not held on the buffer while on this list, |
615 | * A reference is not held on the buffer while on this list, |
598 | * as merely being GTT-bound shouldn't prevent its being |
616 | * as merely being GTT-bound shouldn't prevent its being |
599 | * freed, and we'll pull it off the list in the free path. |
617 | * freed, and we'll pull it off the list in the free path. |
600 | */ |
618 | */ |
601 | struct list_head inactive_list; |
619 | struct list_head inactive_list; |
602 | 620 | ||
603 | /** |
621 | /** |
604 | * LRU list of objects which are not in the ringbuffer but |
622 | * LRU list of objects which are not in the ringbuffer but |
605 | * are still pinned in the GTT. |
623 | * are still pinned in the GTT. |
606 | */ |
624 | */ |
607 | struct list_head pinned_list; |
625 | struct list_head pinned_list; |
608 | 626 | ||
609 | /** LRU list of objects with fence regs on them. */ |
627 | /** LRU list of objects with fence regs on them. */ |
610 | struct list_head fence_list; |
628 | struct list_head fence_list; |
611 | 629 | ||
612 | /** |
630 | /** |
613 | * List of objects currently pending being freed. |
631 | * List of objects currently pending being freed. |
614 | * |
632 | * |
615 | * These objects are no longer in use, but due to a signal |
633 | * These objects are no longer in use, but due to a signal |
616 | * we were prevented from freeing them at the appointed time. |
634 | * we were prevented from freeing them at the appointed time. |
617 | */ |
635 | */ |
618 | struct list_head deferred_free_list; |
636 | struct list_head deferred_free_list; |
619 | 637 | ||
620 | /** |
638 | /** |
621 | * We leave the user IRQ off as much as possible, |
639 | * We leave the user IRQ off as much as possible, |
622 | * but this means that requests will finish and never |
640 | * but this means that requests will finish and never |
623 | * be retired once the system goes idle. Set a timer to |
641 | * be retired once the system goes idle. Set a timer to |
624 | * fire periodically while the ring is running. When it |
642 | * fire periodically while the ring is running. When it |
625 | * fires, go retire requests. |
643 | * fires, go retire requests. |
626 | */ |
644 | */ |
627 | // struct delayed_work retire_work; |
645 | // struct delayed_work retire_work; |
628 | 646 | ||
629 | /** |
647 | /** |
630 | * Are we in a non-interruptible section of code like |
648 | * Are we in a non-interruptible section of code like |
631 | * modesetting? |
649 | * modesetting? |
632 | */ |
650 | */ |
633 | bool interruptible; |
651 | bool interruptible; |
634 | 652 | ||
635 | /** |
653 | /** |
636 | * Flag if the X Server, and thus DRM, is not currently in |
654 | * Flag if the X Server, and thus DRM, is not currently in |
637 | * control of the device. |
655 | * control of the device. |
638 | * |
656 | * |
639 | * This is set between LeaveVT and EnterVT. It needs to be |
657 | * This is set between LeaveVT and EnterVT. It needs to be |
640 | * replaced with a semaphore. It also needs to be |
658 | * replaced with a semaphore. It also needs to be |
641 | * transitioned away from for kernel modesetting. |
659 | * transitioned away from for kernel modesetting. |
642 | */ |
660 | */ |
643 | int suspended; |
661 | int suspended; |
644 | 662 | ||
645 | /** |
663 | /** |
646 | * Flag if the hardware appears to be wedged. |
664 | * Flag if the hardware appears to be wedged. |
647 | * |
665 | * |
648 | * This is set when attempts to idle the device timeout. |
666 | * This is set when attempts to idle the device timeout. |
649 | * It prevents command submission from occurring and makes |
667 | * It prevents command submission from occurring and makes |
650 | * every pending request fail |
668 | * every pending request fail |
651 | */ |
669 | */ |
652 | atomic_t wedged; |
670 | atomic_t wedged; |
653 | 671 | ||
654 | /** Bit 6 swizzling required for X tiling */ |
672 | /** Bit 6 swizzling required for X tiling */ |
655 | uint32_t bit_6_swizzle_x; |
673 | uint32_t bit_6_swizzle_x; |
656 | /** Bit 6 swizzling required for Y tiling */ |
674 | /** Bit 6 swizzling required for Y tiling */ |
657 | uint32_t bit_6_swizzle_y; |
675 | uint32_t bit_6_swizzle_y; |
658 | 676 | ||
659 | /* storage for physical objects */ |
677 | /* storage for physical objects */ |
660 | // struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; |
678 | // struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; |
661 | 679 | ||
662 | /* accounting, useful for userland debugging */ |
680 | /* accounting, useful for userland debugging */ |
663 | size_t gtt_total; |
681 | size_t gtt_total; |
664 | size_t mappable_gtt_total; |
682 | size_t mappable_gtt_total; |
665 | size_t object_memory; |
683 | size_t object_memory; |
666 | u32 object_count; |
684 | u32 object_count; |
667 | } mm; |
685 | } mm; |
668 | struct sdvo_device_mapping sdvo_mappings[2]; |
686 | struct sdvo_device_mapping sdvo_mappings[2]; |
669 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
687 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
670 | unsigned int lvds_border_bits; |
688 | unsigned int lvds_border_bits; |
671 | /* Panel fitter placement and size for Ironlake+ */ |
689 | /* Panel fitter placement and size for Ironlake+ */ |
672 | u32 pch_pf_pos, pch_pf_size; |
690 | u32 pch_pf_pos, pch_pf_size; |
673 | int panel_t3, panel_t12; |
- | |
674 | 691 | ||
675 | struct drm_crtc *plane_to_crtc_mapping[2]; |
692 | struct drm_crtc *plane_to_crtc_mapping[3]; |
676 | struct drm_crtc *pipe_to_crtc_mapping[2]; |
693 | struct drm_crtc *pipe_to_crtc_mapping[3]; |
677 | // wait_queue_head_t pending_flip_queue; |
694 | // wait_queue_head_t pending_flip_queue; |
678 | bool flip_pending_is_done; |
695 | bool flip_pending_is_done; |
679 | 696 | ||
680 | /* Reclocking support */ |
697 | /* Reclocking support */ |
681 | bool render_reclock_avail; |
698 | bool render_reclock_avail; |
682 | bool lvds_downclock_avail; |
699 | bool lvds_downclock_avail; |
683 | /* indicates the reduced downclock for LVDS*/ |
700 | /* indicates the reduced downclock for LVDS*/ |
684 | int lvds_downclock; |
701 | int lvds_downclock; |
685 | // struct work_struct idle_work; |
702 | // struct work_struct idle_work; |
686 | struct timer_list idle_timer; |
703 | struct timer_list idle_timer; |
687 | bool busy; |
704 | bool busy; |
688 | u16 orig_clock; |
705 | u16 orig_clock; |
689 | int child_dev_num; |
706 | int child_dev_num; |
690 | struct child_device_config *child_dev; |
707 | struct child_device_config *child_dev; |
691 | struct drm_connector *int_lvds_connector; |
708 | struct drm_connector *int_lvds_connector; |
692 | struct drm_connector *int_edp_connector; |
709 | struct drm_connector *int_edp_connector; |
693 | 710 | ||
694 | bool mchbar_need_disable; |
711 | bool mchbar_need_disable; |
695 | 712 | ||
696 | // struct work_struct rps_work; |
713 | // struct work_struct rps_work; |
697 | spinlock_t rps_lock; |
714 | spinlock_t rps_lock; |
698 | u32 pm_iir; |
715 | u32 pm_iir; |
699 | 716 | ||
700 | u8 cur_delay; |
717 | u8 cur_delay; |
701 | u8 min_delay; |
718 | u8 min_delay; |
702 | u8 max_delay; |
719 | u8 max_delay; |
703 | u8 fmax; |
720 | u8 fmax; |
704 | u8 fstart; |
721 | u8 fstart; |
705 | 722 | ||
706 | u64 last_count1; |
723 | u64 last_count1; |
707 | unsigned long last_time1; |
724 | unsigned long last_time1; |
- | 725 | unsigned long chipset_power; |
|
708 | u64 last_count2; |
726 | u64 last_count2; |
709 | struct timespec last_time2; |
727 | struct timespec last_time2; |
710 | unsigned long gfx_power; |
728 | unsigned long gfx_power; |
711 | int c_m; |
729 | int c_m; |
712 | int r_t; |
730 | int r_t; |
713 | u8 corr; |
731 | u8 corr; |
714 | spinlock_t *mchdev_lock; |
732 | spinlock_t *mchdev_lock; |
715 | 733 | ||
716 | enum no_fbc_reason no_fbc_reason; |
734 | enum no_fbc_reason no_fbc_reason; |
717 | 735 | ||
718 | // struct drm_mm_node *compressed_fb; |
736 | // struct drm_mm_node *compressed_fb; |
719 | // struct drm_mm_node *compressed_llb; |
737 | // struct drm_mm_node *compressed_llb; |
720 | 738 | ||
721 | unsigned long last_gpu_reset; |
739 | unsigned long last_gpu_reset; |
722 | 740 | ||
723 | /* list of fbdev register on this device */ |
741 | /* list of fbdev register on this device */ |
724 | struct intel_fbdev *fbdev; |
742 | struct intel_fbdev *fbdev; |
725 | 743 | ||
726 | // struct backlight_device *backlight; |
744 | // struct backlight_device *backlight; |
727 | 745 | ||
728 | // struct drm_property *broadcast_rgb_property; |
746 | // struct drm_property *broadcast_rgb_property; |
729 | // struct drm_property *force_audio_property; |
747 | // struct drm_property *force_audio_property; |
730 | - | ||
731 | atomic_t forcewake_count; |
- | |
732 | } drm_i915_private_t; |
748 | } drm_i915_private_t; |
733 | 749 | ||
734 | enum i915_cache_level { |
750 | enum i915_cache_level { |
735 | I915_CACHE_NONE, |
751 | I915_CACHE_NONE, |
736 | I915_CACHE_LLC, |
752 | I915_CACHE_LLC, |
737 | I915_CACHE_LLC_MLC, /* gen6+ */ |
753 | I915_CACHE_LLC_MLC, /* gen6+ */ |
738 | }; |
754 | }; |
739 | 755 | ||
740 | struct drm_i915_gem_object { |
756 | struct drm_i915_gem_object { |
741 | struct drm_gem_object base; |
757 | struct drm_gem_object base; |
742 | 758 | ||
743 | /** Current space allocated to this object in the GTT, if any. */ |
759 | /** Current space allocated to this object in the GTT, if any. */ |
744 | struct drm_mm_node *gtt_space; |
760 | struct drm_mm_node *gtt_space; |
745 | struct list_head gtt_list; |
761 | struct list_head gtt_list; |
746 | 762 | ||
747 | /** This object's place on the active/flushing/inactive lists */ |
763 | /** This object's place on the active/flushing/inactive lists */ |
748 | struct list_head ring_list; |
764 | struct list_head ring_list; |
749 | struct list_head mm_list; |
765 | struct list_head mm_list; |
750 | /** This object's place on GPU write list */ |
766 | /** This object's place on GPU write list */ |
751 | struct list_head gpu_write_list; |
767 | struct list_head gpu_write_list; |
752 | /** This object's place in the batchbuffer or on the eviction list */ |
768 | /** This object's place in the batchbuffer or on the eviction list */ |
753 | struct list_head exec_list; |
769 | struct list_head exec_list; |
754 | 770 | ||
755 | /** |
771 | /** |
756 | * This is set if the object is on the active or flushing lists |
772 | * This is set if the object is on the active or flushing lists |
757 | * (has pending rendering), and is not set if it's on inactive (ready |
773 | * (has pending rendering), and is not set if it's on inactive (ready |
758 | * to be unbound). |
774 | * to be unbound). |
759 | */ |
775 | */ |
760 | unsigned int active : 1; |
776 | unsigned int active:1; |
761 | 777 | ||
762 | /** |
778 | /** |
763 | * This is set if the object has been written to since last bound |
779 | * This is set if the object has been written to since last bound |
764 | * to the GTT |
780 | * to the GTT |
765 | */ |
781 | */ |
766 | unsigned int dirty : 1; |
782 | unsigned int dirty:1; |
767 | 783 | ||
768 | /** |
784 | /** |
769 | * This is set if the object has been written to since the last |
785 | * This is set if the object has been written to since the last |
770 | * GPU flush. |
786 | * GPU flush. |
771 | */ |
787 | */ |
772 | unsigned int pending_gpu_write : 1; |
788 | unsigned int pending_gpu_write:1; |
773 | 789 | ||
774 | /** |
790 | /** |
775 | * Fence register bits (if any) for this object. Will be set |
791 | * Fence register bits (if any) for this object. Will be set |
776 | * as needed when mapped into the GTT. |
792 | * as needed when mapped into the GTT. |
777 | * Protected by dev->struct_mutex. |
793 | * Protected by dev->struct_mutex. |
778 | * |
- | |
779 | * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE) |
- | |
780 | */ |
794 | */ |
781 | signed int fence_reg : 5; |
795 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
782 | 796 | ||
783 | /** |
797 | /** |
784 | * Advice: are the backing pages purgeable? |
798 | * Advice: are the backing pages purgeable? |
785 | */ |
799 | */ |
786 | unsigned int madv : 2; |
800 | unsigned int madv:2; |
787 | 801 | ||
788 | /** |
802 | /** |
789 | * Current tiling mode for the object. |
803 | * Current tiling mode for the object. |
790 | */ |
804 | */ |
791 | unsigned int tiling_mode : 2; |
805 | unsigned int tiling_mode:2; |
792 | unsigned int tiling_changed : 1; |
806 | unsigned int tiling_changed:1; |
793 | 807 | ||
794 | /** How many users have pinned this object in GTT space. The following |
808 | /** How many users have pinned this object in GTT space. The following |
795 | * users can each hold at most one reference: pwrite/pread, pin_ioctl |
809 | * users can each hold at most one reference: pwrite/pread, pin_ioctl |
796 | * (via user_pin_count), execbuffer (objects are not allowed multiple |
810 | * (via user_pin_count), execbuffer (objects are not allowed multiple |
797 | * times for the same batchbuffer), and the framebuffer code. When |
811 | * times for the same batchbuffer), and the framebuffer code. When |
798 | * switching/pageflipping, the framebuffer code has at most two buffers |
812 | * switching/pageflipping, the framebuffer code has at most two buffers |
799 | * pinned per crtc. |
813 | * pinned per crtc. |
800 | * |
814 | * |
801 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 |
815 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 |
802 | * bits with absolutely no headroom. So use 4 bits. */ |
816 | * bits with absolutely no headroom. So use 4 bits. */ |
803 | unsigned int pin_count : 4; |
817 | unsigned int pin_count:4; |
804 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
818 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
805 | 819 | ||
806 | /** |
820 | /** |
807 | * Is the object at the current location in the gtt mappable and |
821 | * Is the object at the current location in the gtt mappable and |
808 | * fenceable? Used to avoid costly recalculations. |
822 | * fenceable? Used to avoid costly recalculations. |
809 | */ |
823 | */ |
810 | unsigned int map_and_fenceable : 1; |
824 | unsigned int map_and_fenceable:1; |
811 | 825 | ||
812 | /** |
826 | /** |
813 | * Whether the current gtt mapping needs to be mappable (and isn't just |
827 | * Whether the current gtt mapping needs to be mappable (and isn't just |
814 | * mappable by accident). Track pin and fault separate for a more |
828 | * mappable by accident). Track pin and fault separate for a more |
815 | * accurate mappable working set. |
829 | * accurate mappable working set. |
816 | */ |
830 | */ |
817 | unsigned int fault_mappable : 1; |
831 | unsigned int fault_mappable:1; |
818 | unsigned int pin_mappable : 1; |
832 | unsigned int pin_mappable:1; |
819 | 833 | ||
820 | /* |
834 | /* |
821 | * Is the GPU currently using a fence to access this buffer, |
835 | * Is the GPU currently using a fence to access this buffer, |
822 | */ |
836 | */ |
823 | unsigned int pending_fenced_gpu_access:1; |
837 | unsigned int pending_fenced_gpu_access:1; |
824 | unsigned int fenced_gpu_access:1; |
838 | unsigned int fenced_gpu_access:1; |
825 | 839 | ||
826 | unsigned int cache_level:2; |
840 | unsigned int cache_level:2; |
827 | 841 | ||
828 | struct page **pages; |
842 | struct page **pages; |
829 | 843 | ||
830 | /** |
844 | /** |
831 | * DMAR support |
845 | * DMAR support |
832 | */ |
846 | */ |
833 | struct scatterlist *sg_list; |
847 | struct scatterlist *sg_list; |
834 | int num_sg; |
848 | int num_sg; |
835 | 849 | ||
836 | /** |
850 | /** |
837 | * Used for performing relocations during execbuffer insertion. |
851 | * Used for performing relocations during execbuffer insertion. |
838 | */ |
852 | */ |
839 | struct hlist_node exec_node; |
853 | struct hlist_node exec_node; |
840 | unsigned long exec_handle; |
854 | unsigned long exec_handle; |
841 | struct drm_i915_gem_exec_object2 *exec_entry; |
855 | struct drm_i915_gem_exec_object2 *exec_entry; |
842 | 856 | ||
843 | /** |
857 | /** |
844 | * Current offset of the object in GTT space. |
858 | * Current offset of the object in GTT space. |
845 | * |
859 | * |
846 | * This is the same as gtt_space->start |
860 | * This is the same as gtt_space->start |
847 | */ |
861 | */ |
848 | uint32_t gtt_offset; |
862 | uint32_t gtt_offset; |
849 | 863 | ||
850 | /** Breadcrumb of last rendering to the buffer. */ |
864 | /** Breadcrumb of last rendering to the buffer. */ |
851 | uint32_t last_rendering_seqno; |
865 | uint32_t last_rendering_seqno; |
852 | struct intel_ring_buffer *ring; |
866 | struct intel_ring_buffer *ring; |
853 | 867 | ||
854 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
868 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
855 | uint32_t last_fenced_seqno; |
869 | uint32_t last_fenced_seqno; |
856 | struct intel_ring_buffer *last_fenced_ring; |
870 | struct intel_ring_buffer *last_fenced_ring; |
857 | 871 | ||
858 | /** Current tiling stride for the object, if it's tiled. */ |
872 | /** Current tiling stride for the object, if it's tiled. */ |
859 | uint32_t stride; |
873 | uint32_t stride; |
860 | 874 | ||
861 | /** Record of address bit 17 of each page at last unbind. */ |
875 | /** Record of address bit 17 of each page at last unbind. */ |
862 | unsigned long *bit_17; |
876 | unsigned long *bit_17; |
863 | 877 | ||
864 | 878 | ||
865 | /** |
879 | /** |
866 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
880 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
867 | * flags which individual pages are valid. |
881 | * flags which individual pages are valid. |
868 | */ |
882 | */ |
869 | uint8_t *page_cpu_valid; |
883 | uint8_t *page_cpu_valid; |
870 | 884 | ||
871 | /** User space pin count and filp owning the pin */ |
885 | /** User space pin count and filp owning the pin */ |
872 | uint32_t user_pin_count; |
886 | uint32_t user_pin_count; |
873 | struct drm_file *pin_filp; |
887 | struct drm_file *pin_filp; |
874 | 888 | ||
875 | /** for phy allocated objects */ |
889 | /** for phy allocated objects */ |
876 | struct drm_i915_gem_phys_object *phys_obj; |
890 | struct drm_i915_gem_phys_object *phys_obj; |
877 | 891 | ||
878 | /** |
892 | /** |
879 | * Number of crtcs where this object is currently the fb, but |
893 | * Number of crtcs where this object is currently the fb, but |
880 | * will be page flipped away on the next vblank. When it |
894 | * will be page flipped away on the next vblank. When it |
881 | * reaches 0, dev_priv->pending_flip_queue will be woken up. |
895 | * reaches 0, dev_priv->pending_flip_queue will be woken up. |
882 | */ |
896 | */ |
883 | atomic_t pending_flip; |
897 | atomic_t pending_flip; |
884 | }; |
898 | }; |
885 | 899 | ||
886 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
900 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
887 | 901 | ||
888 | /** |
902 | /** |
889 | * Request queue structure. |
903 | * Request queue structure. |
890 | * |
904 | * |
891 | * The request queue allows us to note sequence numbers that have been emitted |
905 | * The request queue allows us to note sequence numbers that have been emitted |
892 | * and may be associated with active buffers to be retired. |
906 | * and may be associated with active buffers to be retired. |
893 | * |
907 | * |
894 | * By keeping this list, we can avoid having to do questionable |
908 | * By keeping this list, we can avoid having to do questionable |
895 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate |
909 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate |
896 | * an emission time with seqnos for tracking how far ahead of the GPU we are. |
910 | * an emission time with seqnos for tracking how far ahead of the GPU we are. |
897 | */ |
911 | */ |
898 | struct drm_i915_gem_request { |
912 | struct drm_i915_gem_request { |
899 | /** On Which ring this request was generated */ |
913 | /** On Which ring this request was generated */ |
900 | struct intel_ring_buffer *ring; |
914 | struct intel_ring_buffer *ring; |
901 | 915 | ||
902 | /** GEM sequence number associated with this request. */ |
916 | /** GEM sequence number associated with this request. */ |
903 | uint32_t seqno; |
917 | uint32_t seqno; |
904 | 918 | ||
905 | /** Time at which this request was emitted, in jiffies. */ |
919 | /** Time at which this request was emitted, in jiffies. */ |
906 | unsigned long emitted_jiffies; |
920 | unsigned long emitted_jiffies; |
907 | 921 | ||
908 | /** global list entry for this request */ |
922 | /** global list entry for this request */ |
909 | struct list_head list; |
923 | struct list_head list; |
910 | 924 | ||
911 | struct drm_i915_file_private *file_priv; |
925 | struct drm_i915_file_private *file_priv; |
912 | /** file_priv list entry for this request */ |
926 | /** file_priv list entry for this request */ |
913 | struct list_head client_list; |
927 | struct list_head client_list; |
914 | }; |
928 | }; |
915 | 929 | ||
916 | struct drm_i915_file_private { |
930 | struct drm_i915_file_private { |
917 | struct { |
931 | struct { |
918 | // struct spinlock lock; |
932 | spinlock_t lock; |
919 | struct list_head request_list; |
933 | struct list_head request_list; |
920 | } mm; |
934 | } mm; |
921 | }; |
935 | }; |
922 | 936 | ||
923 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
937 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
924 | 938 | ||
925 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) |
939 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) |
926 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) |
940 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) |
927 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
941 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
928 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) |
942 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) |
929 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
943 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
930 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) |
944 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) |
931 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) |
945 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) |
932 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
946 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
933 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
947 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
934 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) |
948 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) |
935 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
949 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
936 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
950 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
937 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) |
951 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) |
938 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) |
952 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) |
939 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
953 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
940 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
954 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
941 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) |
955 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) |
942 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) |
956 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) |
943 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
957 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
944 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
958 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
945 | 959 | ||
946 | /* |
960 | /* |
947 | * The genX designation typically refers to the render engine, so render |
961 | * The genX designation typically refers to the render engine, so render |
948 | * capability related checks should use IS_GEN, while display and other checks |
962 | * capability related checks should use IS_GEN, while display and other checks |
949 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular |
963 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular |
950 | * chips, etc.). |
964 | * chips, etc.). |
951 | */ |
965 | */ |
952 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
966 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
953 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) |
967 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) |
954 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) |
968 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) |
955 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) |
969 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) |
956 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) |
970 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) |
957 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
971 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
958 | 972 | ||
959 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) |
973 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) |
960 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) |
974 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) |
961 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
975 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
962 | 976 | ||
963 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
977 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
964 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
978 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
965 | 979 | ||
966 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
980 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
967 | * rows, which changed the alignment requirements and fence programming. |
981 | * rows, which changed the alignment requirements and fence programming. |
968 | */ |
982 | */ |
969 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ |
983 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ |
970 | IS_I915GM(dev))) |
984 | IS_I915GM(dev))) |
971 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) |
985 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) |
972 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
986 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
973 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
987 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
974 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) |
988 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) |
975 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
989 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
976 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
990 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
977 | /* dsparb controlled by hw only */ |
991 | /* dsparb controlled by hw only */ |
978 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
992 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
979 | 993 | ||
980 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) |
994 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) |
981 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
995 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
982 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
996 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
983 | 997 | ||
984 | #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
998 | #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
985 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
999 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
986 | 1000 | ||
987 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
1001 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
988 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
1002 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
989 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
1003 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
990 | 1004 | ||
991 | //#include "i915_trace.h" |
1005 | //#include "i915_trace.h" |
992 | 1006 | ||
993 | extern int i915_max_ioctl; |
1007 | extern int i915_max_ioctl; |
994 | extern unsigned int i915_fbpercrtc; |
1008 | extern unsigned int i915_fbpercrtc; |
995 | extern int i915_panel_ignore_lid; |
1009 | extern int i915_panel_ignore_lid; |
996 | extern unsigned int i915_powersave; |
1010 | extern unsigned int i915_powersave; |
997 | extern unsigned int i915_semaphores; |
1011 | extern unsigned int i915_semaphores; |
998 | extern unsigned int i915_lvds_downclock; |
1012 | extern unsigned int i915_lvds_downclock; |
999 | extern unsigned int i915_panel_use_ssc; |
1013 | extern unsigned int i915_panel_use_ssc; |
1000 | extern int i915_vbt_sdvo_panel_type; |
1014 | extern int i915_vbt_sdvo_panel_type; |
1001 | extern unsigned int i915_enable_rc6; |
1015 | extern unsigned int i915_enable_rc6; |
1002 | extern unsigned int i915_enable_fbc; |
1016 | extern unsigned int i915_enable_fbc; |
1003 | extern bool i915_enable_hangcheck; |
1017 | extern bool i915_enable_hangcheck; |
1004 | 1018 | ||
1005 | extern int i915_resume(struct drm_device *dev); |
1019 | extern int i915_resume(struct drm_device *dev); |
1006 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1020 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1007 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); |
1021 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); |
1008 | 1022 | ||
1009 | /* i915_dma.c */ |
1023 | /* i915_dma.c */ |
1010 | extern void i915_kernel_lost_context(struct drm_device * dev); |
1024 | extern void i915_kernel_lost_context(struct drm_device * dev); |
1011 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
1025 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
1012 | extern int i915_driver_unload(struct drm_device *); |
1026 | extern int i915_driver_unload(struct drm_device *); |
1013 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
1027 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
1014 | extern void i915_driver_lastclose(struct drm_device * dev); |
1028 | extern void i915_driver_lastclose(struct drm_device * dev); |
1015 | extern void i915_driver_preclose(struct drm_device *dev, |
1029 | extern void i915_driver_preclose(struct drm_device *dev, |
1016 | struct drm_file *file_priv); |
1030 | struct drm_file *file_priv); |
1017 | extern void i915_driver_postclose(struct drm_device *dev, |
1031 | extern void i915_driver_postclose(struct drm_device *dev, |
1018 | struct drm_file *file_priv); |
1032 | struct drm_file *file_priv); |
1019 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
1033 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
1020 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1034 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1021 | unsigned long arg); |
1035 | unsigned long arg); |
1022 | extern int i915_emit_box(struct drm_device *dev, |
1036 | extern int i915_emit_box(struct drm_device *dev, |
1023 | struct drm_clip_rect *box, |
1037 | struct drm_clip_rect *box, |
1024 | int DR1, int DR4); |
1038 | int DR1, int DR4); |
1025 | extern int i915_reset(struct drm_device *dev, u8 flags); |
1039 | extern int i915_reset(struct drm_device *dev, u8 flags); |
1026 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1040 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1027 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
1041 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
1028 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
1042 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
1029 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
1043 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
1030 | 1044 | ||
1031 | 1045 | ||
1032 | /* i915_irq.c */ |
1046 | /* i915_irq.c */ |
1033 | void i915_hangcheck_elapsed(unsigned long data); |
1047 | void i915_hangcheck_elapsed(unsigned long data); |
1034 | void i915_handle_error(struct drm_device *dev, bool wedged); |
1048 | void i915_handle_error(struct drm_device *dev, bool wedged); |
1035 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
1049 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
1036 | struct drm_file *file_priv); |
1050 | struct drm_file *file_priv); |
1037 | extern int i915_irq_wait(struct drm_device *dev, void *data, |
1051 | extern int i915_irq_wait(struct drm_device *dev, void *data, |
1038 | struct drm_file *file_priv); |
1052 | struct drm_file *file_priv); |
1039 | 1053 | ||
1040 | extern void intel_irq_init(struct drm_device *dev); |
1054 | extern void intel_irq_init(struct drm_device *dev); |
1041 | 1055 | ||
1042 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1056 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1043 | struct drm_file *file_priv); |
1057 | struct drm_file *file_priv); |
1044 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
1058 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
1045 | struct drm_file *file_priv); |
1059 | struct drm_file *file_priv); |
1046 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
1060 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
1047 | struct drm_file *file_priv); |
1061 | struct drm_file *file_priv); |
1048 | 1062 | ||
1049 | void |
1063 | void |
1050 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
1064 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
1051 | 1065 | ||
1052 | void |
1066 | void |
1053 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
1067 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
1054 | 1068 | ||
1055 | void intel_enable_asle (struct drm_device *dev); |
1069 | void intel_enable_asle(struct drm_device *dev); |
1056 | 1070 | ||
1057 | #ifdef CONFIG_DEBUG_FS |
1071 | #ifdef CONFIG_DEBUG_FS |
1058 | extern void i915_destroy_error_state(struct drm_device *dev); |
1072 | extern void i915_destroy_error_state(struct drm_device *dev); |
1059 | #else |
1073 | #else |
1060 | #define i915_destroy_error_state(x) |
1074 | #define i915_destroy_error_state(x) |
1061 | #endif |
1075 | #endif |
1062 | 1076 | ||
1063 | 1077 | ||
1064 | /* i915_mem.c */ |
1078 | /* i915_mem.c */ |
1065 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
1079 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
1066 | struct drm_file *file_priv); |
1080 | struct drm_file *file_priv); |
1067 | extern int i915_mem_free(struct drm_device *dev, void *data, |
1081 | extern int i915_mem_free(struct drm_device *dev, void *data, |
1068 | struct drm_file *file_priv); |
1082 | struct drm_file *file_priv); |
1069 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, |
1083 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, |
1070 | struct drm_file *file_priv); |
1084 | struct drm_file *file_priv); |
1071 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, |
1085 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, |
1072 | struct drm_file *file_priv); |
1086 | struct drm_file *file_priv); |
1073 | extern void i915_mem_takedown(struct mem_block **heap); |
1087 | extern void i915_mem_takedown(struct mem_block **heap); |
1074 | extern void i915_mem_release(struct drm_device * dev, |
1088 | extern void i915_mem_release(struct drm_device * dev, |
1075 | struct drm_file *file_priv, struct mem_block *heap); |
1089 | struct drm_file *file_priv, struct mem_block *heap); |
1076 | /* i915_gem.c */ |
1090 | /* i915_gem.c */ |
1077 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, |
1091 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, |
1078 | struct drm_file *file_priv); |
1092 | struct drm_file *file_priv); |
1079 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
1093 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
1080 | struct drm_file *file_priv); |
1094 | struct drm_file *file_priv); |
1081 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
1095 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
1082 | struct drm_file *file_priv); |
1096 | struct drm_file *file_priv); |
1083 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
1097 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
1084 | struct drm_file *file_priv); |
1098 | struct drm_file *file_priv); |
1085 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
1099 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
1086 | struct drm_file *file_priv); |
1100 | struct drm_file *file_priv); |
1087 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1101 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1088 | struct drm_file *file_priv); |
1102 | struct drm_file *file_priv); |
1089 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1103 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1090 | struct drm_file *file_priv); |
1104 | struct drm_file *file_priv); |
1091 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
1105 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
1092 | struct drm_file *file_priv); |
1106 | struct drm_file *file_priv); |
1093 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
1107 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
1094 | struct drm_file *file_priv); |
1108 | struct drm_file *file_priv); |
1095 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1109 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1096 | struct drm_file *file_priv); |
1110 | struct drm_file *file_priv); |
1097 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1111 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1098 | struct drm_file *file_priv); |
1112 | struct drm_file *file_priv); |
1099 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
1113 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
1100 | struct drm_file *file_priv); |
1114 | struct drm_file *file_priv); |
1101 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
1115 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
1102 | struct drm_file *file_priv); |
1116 | struct drm_file *file_priv); |
1103 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
1117 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
1104 | struct drm_file *file_priv); |
1118 | struct drm_file *file_priv); |
1105 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1119 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1106 | struct drm_file *file_priv); |
1120 | struct drm_file *file_priv); |
1107 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1121 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1108 | struct drm_file *file_priv); |
1122 | struct drm_file *file_priv); |
1109 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
1123 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
1110 | struct drm_file *file_priv); |
1124 | struct drm_file *file_priv); |
1111 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
1125 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
1112 | struct drm_file *file_priv); |
1126 | struct drm_file *file_priv); |
1113 | int i915_gem_get_tiling(struct drm_device *dev, void *data, |
1127 | int i915_gem_get_tiling(struct drm_device *dev, void *data, |
1114 | struct drm_file *file_priv); |
1128 | struct drm_file *file_priv); |
1115 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1129 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1116 | struct drm_file *file_priv); |
1130 | struct drm_file *file_priv); |
1117 | void i915_gem_load(struct drm_device *dev); |
1131 | void i915_gem_load(struct drm_device *dev); |
1118 | int i915_gem_init_object(struct drm_gem_object *obj); |
1132 | int i915_gem_init_object(struct drm_gem_object *obj); |
1119 | int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, |
1133 | int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, |
1120 | uint32_t invalidate_domains, |
1134 | uint32_t invalidate_domains, |
1121 | uint32_t flush_domains); |
1135 | uint32_t flush_domains); |
1122 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1136 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1123 | size_t size); |
1137 | size_t size); |
1124 | void i915_gem_free_object(struct drm_gem_object *obj); |
1138 | void i915_gem_free_object(struct drm_gem_object *obj); |
1125 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
1139 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
1126 | uint32_t alignment, |
1140 | uint32_t alignment, |
1127 | bool map_and_fenceable); |
1141 | bool map_and_fenceable); |
1128 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
1142 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
1129 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
1143 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
1130 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
1144 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
1131 | void i915_gem_lastclose(struct drm_device *dev); |
1145 | void i915_gem_lastclose(struct drm_device *dev); |
1132 | 1146 | ||
1133 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
1147 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
1134 | int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); |
1148 | int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); |
1135 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1149 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1136 | struct intel_ring_buffer *ring, |
1150 | struct intel_ring_buffer *ring, |
1137 | u32 seqno); |
1151 | u32 seqno); |
1138 | 1152 | ||
1139 | int i915_gem_dumb_create(struct drm_file *file_priv, |
1153 | int i915_gem_dumb_create(struct drm_file *file_priv, |
1140 | struct drm_device *dev, |
1154 | struct drm_device *dev, |
1141 | struct drm_mode_create_dumb *args); |
1155 | struct drm_mode_create_dumb *args); |
1142 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
1156 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
1143 | uint32_t handle, uint64_t *offset); |
1157 | uint32_t handle, uint64_t *offset); |
1144 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, |
1158 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, |
1145 | uint32_t handle); |
1159 | uint32_t handle); |
1146 | /** |
1160 | /** |
1147 | * Returns true if seq1 is later than seq2. |
1161 | * Returns true if seq1 is later than seq2. |
1148 | */ |
1162 | */ |
1149 | static inline bool |
1163 | static inline bool |
1150 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
1164 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
1151 | { |
1165 | { |
1152 | return (int32_t)(seq1 - seq2) >= 0; |
1166 | return (int32_t)(seq1 - seq2) >= 0; |
1153 | } |
1167 | } |
1154 | 1168 | ||
1155 | static inline u32 |
1169 | static inline u32 |
1156 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) |
1170 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) |
1157 | { |
1171 | { |
1158 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
1172 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
1159 | return ring->outstanding_lazy_request = dev_priv->next_seqno; |
1173 | return ring->outstanding_lazy_request = dev_priv->next_seqno; |
1160 | } |
1174 | } |
- | 1175 | ||
- | 1176 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
|
- | 1177 | struct intel_ring_buffer *pipelined); |
|
1161 | 1178 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
|
1162 | 1179 | ||
1163 | void i915_gem_retire_requests(struct drm_device *dev); |
1180 | void i915_gem_retire_requests(struct drm_device *dev); |
1164 | void i915_gem_reset(struct drm_device *dev); |
1181 | void i915_gem_reset(struct drm_device *dev); |
1165 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
1182 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
1166 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
1183 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
1167 | uint32_t read_domains, |
1184 | uint32_t read_domains, |
1168 | uint32_t write_domain); |
1185 | uint32_t write_domain); |
1169 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1186 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1170 | int __must_check i915_gem_init_ringbuffer(struct drm_device *dev); |
1187 | int __must_check i915_gem_init_ringbuffer(struct drm_device *dev); |
1171 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
1188 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
1172 | void i915_gem_do_init(struct drm_device *dev, |
1189 | void i915_gem_do_init(struct drm_device *dev, |
1173 | unsigned long start, |
1190 | unsigned long start, |
1174 | unsigned long mappable_end, |
1191 | unsigned long mappable_end, |
1175 | unsigned long end); |
1192 | unsigned long end); |
1176 | int __must_check i915_gpu_idle(struct drm_device *dev); |
1193 | int __must_check i915_gpu_idle(struct drm_device *dev); |
1177 | int __must_check i915_gem_idle(struct drm_device *dev); |
1194 | int __must_check i915_gem_idle(struct drm_device *dev); |
1178 | int __must_check i915_add_request(struct intel_ring_buffer *ring, |
1195 | int __must_check i915_add_request(struct intel_ring_buffer *ring, |
1179 | struct drm_file *file, |
1196 | struct drm_file *file, |
1180 | struct drm_i915_gem_request *request); |
1197 | struct drm_i915_gem_request *request); |
1181 | int __must_check i915_wait_request(struct intel_ring_buffer *ring, |
1198 | int __must_check i915_wait_request(struct intel_ring_buffer *ring, |
1182 | uint32_t seqno); |
1199 | uint32_t seqno); |
1183 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
1200 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
1184 | int __must_check |
1201 | int __must_check |
1185 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
1202 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
1186 | bool write); |
1203 | bool write); |
1187 | int __must_check |
1204 | int __must_check |
1188 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1205 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1189 | u32 alignment, |
1206 | u32 alignment, |
1190 | struct intel_ring_buffer *pipelined); |
1207 | struct intel_ring_buffer *pipelined); |
1191 | int i915_gem_attach_phys_object(struct drm_device *dev, |
1208 | int i915_gem_attach_phys_object(struct drm_device *dev, |
1192 | struct drm_i915_gem_object *obj, |
1209 | struct drm_i915_gem_object *obj, |
1193 | int id, |
1210 | int id, |
1194 | int align); |
1211 | int align); |
1195 | void i915_gem_detach_phys_object(struct drm_device *dev, |
1212 | void i915_gem_detach_phys_object(struct drm_device *dev, |
1196 | struct drm_i915_gem_object *obj); |
1213 | struct drm_i915_gem_object *obj); |
1197 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
1214 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
1198 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
1215 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
1199 | 1216 | ||
1200 | uint32_t |
1217 | uint32_t |
1201 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1218 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1202 | uint32_t size, |
1219 | uint32_t size, |
1203 | int tiling_mode); |
1220 | int tiling_mode); |
1204 | 1221 | ||
1205 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
1222 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
1206 | enum i915_cache_level cache_level); |
1223 | enum i915_cache_level cache_level); |
1207 | 1224 | ||
1208 | /* i915_gem_gtt.c */ |
1225 | /* i915_gem_gtt.c */ |
1209 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
1226 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
1210 | int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); |
1227 | int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); |
1211 | void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, |
1228 | void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, |
1212 | enum i915_cache_level cache_level); |
1229 | enum i915_cache_level cache_level); |
1213 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
1230 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
1214 | 1231 | ||
1215 | /* i915_gem_evict.c */ |
1232 | /* i915_gem_evict.c */ |
1216 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
1233 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
1217 | unsigned alignment, bool mappable); |
1234 | unsigned alignment, bool mappable); |
1218 | int __must_check i915_gem_evict_everything(struct drm_device *dev, |
1235 | int __must_check i915_gem_evict_everything(struct drm_device *dev, |
1219 | bool purgeable_only); |
1236 | bool purgeable_only); |
1220 | int __must_check i915_gem_evict_inactive(struct drm_device *dev, |
1237 | int __must_check i915_gem_evict_inactive(struct drm_device *dev, |
1221 | bool purgeable_only); |
1238 | bool purgeable_only); |
1222 | 1239 | ||
1223 | /* i915_gem_tiling.c */ |
1240 | /* i915_gem_tiling.c */ |
1224 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
1241 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
1225 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1242 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1226 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1243 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1227 | 1244 | ||
1228 | /* i915_gem_debug.c */ |
1245 | /* i915_gem_debug.c */ |
1229 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
1246 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
1230 | const char *where, uint32_t mark); |
1247 | const char *where, uint32_t mark); |
1231 | #if WATCH_LISTS |
1248 | #if WATCH_LISTS |
1232 | int i915_verify_lists(struct drm_device *dev); |
1249 | int i915_verify_lists(struct drm_device *dev); |
1233 | #else |
1250 | #else |
1234 | #define i915_verify_lists(dev) 0 |
1251 | #define i915_verify_lists(dev) 0 |
1235 | #endif |
1252 | #endif |
1236 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
1253 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
1237 | int handle); |
1254 | int handle); |
1238 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
1255 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
1239 | const char *where, uint32_t mark); |
1256 | const char *where, uint32_t mark); |
1240 | 1257 | ||
1241 | /* i915_debugfs.c */ |
1258 | /* i915_debugfs.c */ |
1242 | int i915_debugfs_init(struct drm_minor *minor); |
1259 | int i915_debugfs_init(struct drm_minor *minor); |
1243 | void i915_debugfs_cleanup(struct drm_minor *minor); |
1260 | void i915_debugfs_cleanup(struct drm_minor *minor); |
1244 | 1261 | ||
1245 | /* i915_suspend.c */ |
1262 | /* i915_suspend.c */ |
1246 | extern int i915_save_state(struct drm_device *dev); |
1263 | extern int i915_save_state(struct drm_device *dev); |
1247 | extern int i915_restore_state(struct drm_device *dev); |
1264 | extern int i915_restore_state(struct drm_device *dev); |
1248 | 1265 | ||
1249 | /* i915_suspend.c */ |
1266 | /* i915_suspend.c */ |
1250 | extern int i915_save_state(struct drm_device *dev); |
1267 | extern int i915_save_state(struct drm_device *dev); |
1251 | extern int i915_restore_state(struct drm_device *dev); |
1268 | extern int i915_restore_state(struct drm_device *dev); |
1252 | 1269 | ||
1253 | /* intel_i2c.c */ |
1270 | /* intel_i2c.c */ |
1254 | extern int intel_setup_gmbus(struct drm_device *dev); |
1271 | extern int intel_setup_gmbus(struct drm_device *dev); |
1255 | extern void intel_teardown_gmbus(struct drm_device *dev); |
1272 | extern void intel_teardown_gmbus(struct drm_device *dev); |
1256 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1273 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1257 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); |
1274 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); |
1258 | - | ||
1259 | //extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1275 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1260 | //{ |
1276 | { |
1261 | // return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
1277 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
1262 | //} |
- | |
1263 | 1278 | } |
|
1264 | extern void intel_i2c_reset(struct drm_device *dev); |
1279 | extern void intel_i2c_reset(struct drm_device *dev); |
1265 | 1280 | ||
1266 | /* intel_opregion.c */ |
1281 | /* intel_opregion.c */ |
1267 | extern int intel_opregion_setup(struct drm_device *dev); |
1282 | extern int intel_opregion_setup(struct drm_device *dev); |
1268 | #ifdef CONFIG_ACPI |
1283 | #ifdef CONFIG_ACPI |
1269 | extern void intel_opregion_init(struct drm_device *dev); |
1284 | extern void intel_opregion_init(struct drm_device *dev); |
1270 | extern void intel_opregion_fini(struct drm_device *dev); |
1285 | extern void intel_opregion_fini(struct drm_device *dev); |
1271 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1286 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1272 | extern void intel_opregion_gse_intr(struct drm_device *dev); |
1287 | extern void intel_opregion_gse_intr(struct drm_device *dev); |
1273 | extern void intel_opregion_enable_asle(struct drm_device *dev); |
1288 | extern void intel_opregion_enable_asle(struct drm_device *dev); |
1274 | #else |
1289 | #else |
1275 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1290 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1276 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } |
1291 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } |
1277 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1292 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1278 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } |
1293 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } |
1279 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } |
1294 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } |
1280 | #endif |
1295 | #endif |
1281 | 1296 | ||
1282 | /* intel_acpi.c */ |
1297 | /* intel_acpi.c */ |
1283 | #ifdef CONFIG_ACPI |
1298 | #ifdef CONFIG_ACPI |
1284 | extern void intel_register_dsm_handler(void); |
1299 | extern void intel_register_dsm_handler(void); |
1285 | extern void intel_unregister_dsm_handler(void); |
1300 | extern void intel_unregister_dsm_handler(void); |
1286 | #else |
1301 | #else |
1287 | static inline void intel_register_dsm_handler(void) { return; } |
1302 | static inline void intel_register_dsm_handler(void) { return; } |
1288 | static inline void intel_unregister_dsm_handler(void) { return; } |
1303 | static inline void intel_unregister_dsm_handler(void) { return; } |
1289 | #endif /* CONFIG_ACPI */ |
1304 | #endif /* CONFIG_ACPI */ |
1290 | 1305 | ||
1291 | /* modesetting */ |
1306 | /* modesetting */ |
1292 | extern void intel_modeset_init(struct drm_device *dev); |
1307 | extern void intel_modeset_init(struct drm_device *dev); |
1293 | extern void intel_modeset_gem_init(struct drm_device *dev); |
1308 | extern void intel_modeset_gem_init(struct drm_device *dev); |
1294 | extern void intel_modeset_cleanup(struct drm_device *dev); |
1309 | extern void intel_modeset_cleanup(struct drm_device *dev); |
1295 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
1310 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
1296 | extern bool intel_fbc_enabled(struct drm_device *dev); |
1311 | extern bool intel_fbc_enabled(struct drm_device *dev); |
1297 | extern void intel_disable_fbc(struct drm_device *dev); |
1312 | extern void intel_disable_fbc(struct drm_device *dev); |
1298 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
1313 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
- | 1314 | extern void ironlake_init_pch_refclk(struct drm_device *dev); |
|
1299 | extern void ironlake_enable_rc6(struct drm_device *dev); |
1315 | extern void ironlake_enable_rc6(struct drm_device *dev); |
1300 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
1316 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
1301 | extern void intel_detect_pch (struct drm_device *dev); |
1317 | extern void intel_detect_pch(struct drm_device *dev); |
1302 | extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); |
1318 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); |
- | 1319 | ||
- | 1320 | extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
|
- | 1321 | extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); |
|
- | 1322 | extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); |
|
- | 1323 | extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); |
|
1303 | 1324 | ||
1304 | /* overlay */ |
1325 | /* overlay */ |
1305 | #ifdef CONFIG_DEBUG_FS |
1326 | #ifdef CONFIG_DEBUG_FS |
1306 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1327 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1307 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); |
1328 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); |
1308 | 1329 | ||
1309 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); |
1330 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); |
1310 | extern void intel_display_print_error_state(struct seq_file *m, |
1331 | extern void intel_display_print_error_state(struct seq_file *m, |
1311 | struct drm_device *dev, |
1332 | struct drm_device *dev, |
1312 | struct intel_display_error_state *error); |
1333 | struct intel_display_error_state *error); |
1313 | #endif |
1334 | #endif |
1314 | 1335 | ||
1315 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
1336 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
1316 | 1337 | ||
1317 | #define BEGIN_LP_RING(n) \ |
1338 | #define BEGIN_LP_RING(n) \ |
1318 | intel_ring_begin(LP_RING(dev_priv), (n)) |
1339 | intel_ring_begin(LP_RING(dev_priv), (n)) |
1319 | 1340 | ||
1320 | #define OUT_RING(x) \ |
1341 | #define OUT_RING(x) \ |
1321 | intel_ring_emit(LP_RING(dev_priv), x) |
1342 | intel_ring_emit(LP_RING(dev_priv), x) |
1322 | 1343 | ||
1323 | #define ADVANCE_LP_RING() \ |
1344 | #define ADVANCE_LP_RING() \ |
1324 | intel_ring_advance(LP_RING(dev_priv)) |
1345 | intel_ring_advance(LP_RING(dev_priv)) |
1325 | 1346 | ||
1326 | /** |
1347 | /** |
1327 | * Lock test for when it's just for synchronization of ring access. |
1348 | * Lock test for when it's just for synchronization of ring access. |
1328 | * |
1349 | * |
1329 | * In that case, we don't need to do it when GEM is initialized as nobody else |
1350 | * In that case, we don't need to do it when GEM is initialized as nobody else |
1330 | * has access to the ring. |
1351 | * has access to the ring. |
1331 | */ |
1352 | */ |
1332 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ |
1353 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ |
1333 | if (LP_RING(dev->dev_private)->obj == NULL) \ |
1354 | if (LP_RING(dev->dev_private)->obj == NULL) \ |
1334 | LOCK_TEST_WITH_RETURN(dev, file); \ |
1355 | LOCK_TEST_WITH_RETURN(dev, file); \ |
1335 | } while (0) |
1356 | } while (0) |
1336 | 1357 | ||
1337 | /* On SNB platform, before reading ring registers forcewake bit |
1358 | /* On SNB platform, before reading ring registers forcewake bit |
1338 | * must be set to prevent GT core from power down and stale values being |
1359 | * must be set to prevent GT core from power down and stale values being |
1339 | * returned. |
1360 | * returned. |
1340 | */ |
1361 | */ |
1341 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1362 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1342 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); |
1363 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); |
1343 | void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
1364 | void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
1344 | 1365 | ||
1345 | /* We give fast paths for the really cool registers */ |
1366 | /* We give fast paths for the really cool registers */ |
1346 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
1367 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
1347 | (((dev_priv)->info->gen >= 6) && \ |
1368 | (((dev_priv)->info->gen >= 6) && \ |
1348 | ((reg) < 0x40000) && \ |
1369 | ((reg) < 0x40000) && \ |
1349 | ((reg) != FORCEWAKE)) |
1370 | ((reg) != FORCEWAKE)) |
1350 | 1371 | ||
1351 | #define __i915_read(x, y) \ |
1372 | #define __i915_read(x, y) \ |
1352 | static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
1373 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); |
1353 | u##x val = 0; \ |
- | |
1354 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
- | |
1355 | gen6_gt_force_wake_get(dev_priv); \ |
- | |
1356 | val = read##y(dev_priv->regs + reg); \ |
- | |
1357 | gen6_gt_force_wake_put(dev_priv); \ |
- | |
1358 | } else { \ |
- | |
1359 | val = read##y(dev_priv->regs + reg); \ |
- | |
1360 | } \ |
- | |
1361 | /* trace_i915_reg_rw(false, reg, val, sizeof(val)); */\ |
- | |
1362 | return val; \ |
- | |
1363 | } |
- | |
1364 | 1374 | ||
1365 | __i915_read(8, b) |
1375 | __i915_read(8, b) |
1366 | __i915_read(16, w) |
1376 | __i915_read(16, w) |
1367 | __i915_read(32, l) |
1377 | __i915_read(32, l) |
1368 | __i915_read(64, q) |
1378 | __i915_read(64, q) |
1369 | #undef __i915_read |
1379 | #undef __i915_read |
1370 | 1380 | ||
1371 | #define __i915_write(x, y) \ |
1381 | #define __i915_write(x, y) \ |
1372 | static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ |
1382 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); |
1373 | /* trace_i915_reg_rw(true, reg, val, sizeof(val));*/ \ |
- | |
1374 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
- | |
1375 | __gen6_gt_wait_for_fifo(dev_priv); \ |
- | |
1376 | } \ |
- | |
1377 | write##y(val, dev_priv->regs + reg); \ |
- | |
1378 | } |
1383 | |
1379 | __i915_write(8, b) |
1384 | __i915_write(8, b) |
1380 | __i915_write(16, w) |
1385 | __i915_write(16, w) |
1381 | __i915_write(32, l) |
1386 | __i915_write(32, l) |
1382 | __i915_write(64, q) |
1387 | __i915_write(64, q) |
1383 | #undef __i915_write |
1388 | #undef __i915_write |
1384 | 1389 | ||
1385 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) |
1390 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) |
1386 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) |
1391 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) |
1387 | 1392 | ||
1388 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) |
1393 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) |
1389 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) |
1394 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) |
1390 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) |
1395 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) |
1391 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) |
1396 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) |
1392 | 1397 | ||
1393 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) |
1398 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) |
1394 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) |
1399 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) |
1395 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1400 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1396 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) |
1401 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) |
1397 | 1402 | ||
1398 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) |
1403 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) |
1399 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) |
1404 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) |
1400 | 1405 | ||
1401 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
1406 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
1402 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
1407 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
1403 | 1408 | ||
1404 | typedef struct |
1409 | typedef struct |
1405 | { |
1410 | { |
1406 | int width; |
1411 | int width; |
1407 | int height; |
1412 | int height; |
1408 | int bpp; |
1413 | int bpp; |
1409 | int freq; |
1414 | int freq; |
1410 | }videomode_t; |
1415 | }videomode_t; |
1411 | 1416 | ||
1412 | #endif>1) |
1417 | #endif>1) |
1413 | 1418 | ||
1414 | struct><1) |
1419 | struct><1) |
1415 | 1420 | ||
1416 | struct>0) |
1421 | struct>0) |
1417 | #define><0) |
1422 | #define><0) |
1418 | #define>> |
1423 | #define>> |