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1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ |
2 | */ |
3 | /* |
3 | /* |
4 | * |
4 | * |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. |
6 | * All Rights Reserved. |
7 | * |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a |
8 | * Permission is hereby granted, free of charge, to any person obtaining a |
9 | * copy of this software and associated documentation files (the |
9 | * copy of this software and associated documentation files (the |
10 | * "Software"), to deal in the Software without restriction, including |
10 | * "Software"), to deal in the Software without restriction, including |
11 | * without limitation the rights to use, copy, modify, merge, publish, |
11 | * without limitation the rights to use, copy, modify, merge, publish, |
12 | * distribute, sub license, and/or sell copies of the Software, and to |
12 | * distribute, sub license, and/or sell copies of the Software, and to |
13 | * permit persons to whom the Software is furnished to do so, subject to |
13 | * permit persons to whom the Software is furnished to do so, subject to |
14 | * the following conditions: |
14 | * the following conditions: |
15 | * |
15 | * |
16 | * The above copyright notice and this permission notice (including the |
16 | * The above copyright notice and this permission notice (including the |
17 | * next paragraph) shall be included in all copies or substantial portions |
17 | * next paragraph) shall be included in all copies or substantial portions |
18 | * of the Software. |
18 | * of the Software. |
19 | * |
19 | * |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
27 | * |
27 | * |
28 | */ |
28 | */ |
29 | 29 | ||
30 | #ifndef _I915_DRV_H_ |
30 | #ifndef _I915_DRV_H_ |
31 | #define _I915_DRV_H_ |
31 | #define _I915_DRV_H_ |
32 | 32 | ||
33 | #include "i915_reg.h" |
33 | #include "i915_reg.h" |
34 | //#include "intel_bios.h" |
34 | //#include "intel_bios.h" |
35 | //#include "intel_ringbuffer.h" |
35 | #include "intel_ringbuffer.h" |
36 | //#include |
36 | //#include |
37 | //#include |
37 | //#include |
38 | //#include |
38 | //#include |
39 | //#include |
39 | //#include |
40 | 40 | ||
41 | #include |
41 | #include |
42 | 42 | ||
43 | /* General customization: |
43 | /* General customization: |
44 | */ |
44 | */ |
45 | 45 | ||
46 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." |
46 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." |
47 | 47 | ||
48 | #define DRIVER_NAME "i915" |
48 | #define DRIVER_NAME "i915" |
49 | #define DRIVER_DESC "Intel Graphics" |
49 | #define DRIVER_DESC "Intel Graphics" |
50 | #define DRIVER_DATE "20080730" |
50 | #define DRIVER_DATE "20080730" |
51 | 51 | ||
52 | enum pipe { |
52 | enum pipe { |
53 | PIPE_A = 0, |
53 | PIPE_A = 0, |
54 | PIPE_B, |
54 | PIPE_B, |
55 | PIPE_C, |
55 | PIPE_C, |
56 | I915_MAX_PIPES |
56 | I915_MAX_PIPES |
57 | }; |
57 | }; |
58 | #define pipe_name(p) ((p) + 'A') |
58 | #define pipe_name(p) ((p) + 'A') |
59 | 59 | ||
60 | enum plane { |
60 | enum plane { |
61 | PLANE_A = 0, |
61 | PLANE_A = 0, |
62 | PLANE_B, |
62 | PLANE_B, |
63 | PLANE_C, |
63 | PLANE_C, |
64 | }; |
64 | }; |
65 | #define plane_name(p) ((p) + 'A') |
65 | #define plane_name(p) ((p) + 'A') |
66 | 66 | ||
67 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
67 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
68 | 68 | ||
69 | #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
69 | #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
70 | 70 | ||
71 | /* Interface history: |
71 | /* Interface history: |
72 | * |
72 | * |
73 | * 1.1: Original. |
73 | * 1.1: Original. |
74 | * 1.2: Add Power Management |
74 | * 1.2: Add Power Management |
75 | * 1.3: Add vblank support |
75 | * 1.3: Add vblank support |
76 | * 1.4: Fix cmdbuffer path, add heap destroy |
76 | * 1.4: Fix cmdbuffer path, add heap destroy |
77 | * 1.5: Add vblank pipe configuration |
77 | * 1.5: Add vblank pipe configuration |
78 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
78 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
79 | * - Support vertical blank on secondary display pipe |
79 | * - Support vertical blank on secondary display pipe |
80 | */ |
80 | */ |
81 | #define DRIVER_MAJOR 1 |
81 | #define DRIVER_MAJOR 1 |
82 | #define DRIVER_MINOR 6 |
82 | #define DRIVER_MINOR 6 |
83 | #define DRIVER_PATCHLEVEL 0 |
83 | #define DRIVER_PATCHLEVEL 0 |
84 | 84 | ||
85 | #define WATCH_COHERENCY 0 |
85 | #define WATCH_COHERENCY 0 |
86 | #define WATCH_LISTS 0 |
86 | #define WATCH_LISTS 0 |
87 | 87 | ||
88 | #define I915_GEM_PHYS_CURSOR_0 1 |
88 | #define I915_GEM_PHYS_CURSOR_0 1 |
89 | #define I915_GEM_PHYS_CURSOR_1 2 |
89 | #define I915_GEM_PHYS_CURSOR_1 2 |
90 | #define I915_GEM_PHYS_OVERLAY_REGS 3 |
90 | #define I915_GEM_PHYS_OVERLAY_REGS 3 |
91 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) |
91 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) |
92 | 92 | ||
93 | struct mem_block { |
93 | struct mem_block { |
94 | struct mem_block *next; |
94 | struct mem_block *next; |
95 | struct mem_block *prev; |
95 | struct mem_block *prev; |
96 | int start; |
96 | int start; |
97 | int size; |
97 | int size; |
98 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
98 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
99 | }; |
99 | }; |
100 | 100 | ||
101 | struct opregion_header; |
101 | struct opregion_header; |
102 | struct opregion_acpi; |
102 | struct opregion_acpi; |
103 | struct opregion_swsci; |
103 | struct opregion_swsci; |
104 | struct opregion_asle; |
104 | struct opregion_asle; |
105 | 105 | ||
106 | struct intel_opregion { |
106 | struct intel_opregion { |
107 | struct opregion_header *header; |
107 | struct opregion_header *header; |
108 | struct opregion_acpi *acpi; |
108 | struct opregion_acpi *acpi; |
109 | struct opregion_swsci *swsci; |
109 | struct opregion_swsci *swsci; |
110 | struct opregion_asle *asle; |
110 | struct opregion_asle *asle; |
111 | void *vbt; |
111 | void *vbt; |
112 | u32 __iomem *lid_state; |
112 | u32 __iomem *lid_state; |
113 | }; |
113 | }; |
114 | #define OPREGION_SIZE (8*1024) |
114 | #define OPREGION_SIZE (8*1024) |
115 | 115 | ||
116 | struct intel_overlay; |
116 | struct intel_overlay; |
117 | struct intel_overlay_error_state; |
117 | struct intel_overlay_error_state; |
118 | 118 | ||
119 | 119 | ||
120 | #define I915_FENCE_REG_NONE -1 |
120 | #define I915_FENCE_REG_NONE -1 |
121 | 121 | ||
122 | struct drm_i915_fence_reg { |
122 | struct drm_i915_fence_reg { |
123 | struct list_head lru_list; |
123 | struct list_head lru_list; |
124 | struct drm_i915_gem_object *obj; |
124 | struct drm_i915_gem_object *obj; |
125 | uint32_t setup_seqno; |
125 | uint32_t setup_seqno; |
126 | }; |
126 | }; |
127 | 127 | ||
128 | struct sdvo_device_mapping { |
128 | struct sdvo_device_mapping { |
129 | u8 initialized; |
129 | u8 initialized; |
130 | u8 dvo_port; |
130 | u8 dvo_port; |
131 | u8 slave_addr; |
131 | u8 slave_addr; |
132 | u8 dvo_wiring; |
132 | u8 dvo_wiring; |
133 | u8 i2c_pin; |
133 | u8 i2c_pin; |
134 | u8 i2c_speed; |
134 | u8 i2c_speed; |
135 | u8 ddc_pin; |
135 | u8 ddc_pin; |
136 | }; |
136 | }; |
137 | 137 | ||
138 | struct intel_display_error_state; |
138 | struct intel_display_error_state; |
139 | 139 | ||
140 | struct drm_i915_error_state { |
140 | struct drm_i915_error_state { |
141 | u32 eir; |
141 | u32 eir; |
142 | u32 pgtbl_er; |
142 | u32 pgtbl_er; |
143 | u32 pipestat[I915_MAX_PIPES]; |
143 | u32 pipestat[I915_MAX_PIPES]; |
144 | u32 ipeir; |
144 | u32 ipeir; |
145 | u32 ipehr; |
145 | u32 ipehr; |
146 | u32 instdone; |
146 | u32 instdone; |
147 | u32 acthd; |
147 | u32 acthd; |
148 | u32 error; /* gen6+ */ |
148 | u32 error; /* gen6+ */ |
149 | u32 bcs_acthd; /* gen6+ blt engine */ |
149 | u32 bcs_acthd; /* gen6+ blt engine */ |
150 | u32 bcs_ipehr; |
150 | u32 bcs_ipehr; |
151 | u32 bcs_ipeir; |
151 | u32 bcs_ipeir; |
152 | u32 bcs_instdone; |
152 | u32 bcs_instdone; |
153 | u32 bcs_seqno; |
153 | u32 bcs_seqno; |
154 | u32 vcs_acthd; /* gen6+ bsd engine */ |
154 | u32 vcs_acthd; /* gen6+ bsd engine */ |
155 | u32 vcs_ipehr; |
155 | u32 vcs_ipehr; |
156 | u32 vcs_ipeir; |
156 | u32 vcs_ipeir; |
157 | u32 vcs_instdone; |
157 | u32 vcs_instdone; |
158 | u32 vcs_seqno; |
158 | u32 vcs_seqno; |
159 | u32 instpm; |
159 | u32 instpm; |
160 | u32 instps; |
160 | u32 instps; |
161 | u32 instdone1; |
161 | u32 instdone1; |
162 | u32 seqno; |
162 | u32 seqno; |
163 | u64 bbaddr; |
163 | u64 bbaddr; |
164 | u64 fence[16]; |
164 | u64 fence[16]; |
165 | struct timeval time; |
165 | struct timeval time; |
166 | struct drm_i915_error_object { |
166 | struct drm_i915_error_object { |
167 | int page_count; |
167 | int page_count; |
168 | u32 gtt_offset; |
168 | u32 gtt_offset; |
169 | u32 *pages[0]; |
169 | u32 *pages[0]; |
170 | } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS]; |
170 | } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS]; |
171 | struct drm_i915_error_buffer { |
171 | struct drm_i915_error_buffer { |
172 | u32 size; |
172 | u32 size; |
173 | u32 name; |
173 | u32 name; |
174 | u32 seqno; |
174 | u32 seqno; |
175 | u32 gtt_offset; |
175 | u32 gtt_offset; |
176 | u32 read_domains; |
176 | u32 read_domains; |
177 | u32 write_domain; |
177 | u32 write_domain; |
178 | s32 fence_reg:5; |
178 | s32 fence_reg:5; |
179 | s32 pinned:2; |
179 | s32 pinned:2; |
180 | u32 tiling:2; |
180 | u32 tiling:2; |
181 | u32 dirty:1; |
181 | u32 dirty:1; |
182 | u32 purgeable:1; |
182 | u32 purgeable:1; |
183 | u32 ring:4; |
183 | u32 ring:4; |
184 | u32 cache_level:2; |
184 | u32 cache_level:2; |
185 | } *active_bo, *pinned_bo; |
185 | } *active_bo, *pinned_bo; |
186 | u32 active_bo_count, pinned_bo_count; |
186 | u32 active_bo_count, pinned_bo_count; |
187 | struct intel_overlay_error_state *overlay; |
187 | struct intel_overlay_error_state *overlay; |
188 | struct intel_display_error_state *display; |
188 | struct intel_display_error_state *display; |
189 | }; |
189 | }; |
190 | 190 | ||
191 | struct drm_i915_display_funcs { |
191 | struct drm_i915_display_funcs { |
192 | void (*dpms)(struct drm_crtc *crtc, int mode); |
192 | void (*dpms)(struct drm_crtc *crtc, int mode); |
193 | bool (*fbc_enabled)(struct drm_device *dev); |
193 | bool (*fbc_enabled)(struct drm_device *dev); |
194 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
194 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
195 | void (*disable_fbc)(struct drm_device *dev); |
195 | void (*disable_fbc)(struct drm_device *dev); |
196 | int (*get_display_clock_speed)(struct drm_device *dev); |
196 | int (*get_display_clock_speed)(struct drm_device *dev); |
197 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
197 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
198 | void (*update_wm)(struct drm_device *dev); |
198 | void (*update_wm)(struct drm_device *dev); |
199 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
199 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
200 | struct drm_display_mode *mode, |
200 | struct drm_display_mode *mode, |
201 | struct drm_display_mode *adjusted_mode, |
201 | struct drm_display_mode *adjusted_mode, |
202 | int x, int y, |
202 | int x, int y, |
203 | struct drm_framebuffer *old_fb); |
203 | struct drm_framebuffer *old_fb); |
204 | void (*fdi_link_train)(struct drm_crtc *crtc); |
204 | void (*fdi_link_train)(struct drm_crtc *crtc); |
205 | void (*init_clock_gating)(struct drm_device *dev); |
205 | void (*init_clock_gating)(struct drm_device *dev); |
206 | void (*init_pch_clock_gating)(struct drm_device *dev); |
206 | void (*init_pch_clock_gating)(struct drm_device *dev); |
207 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
207 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
208 | struct drm_framebuffer *fb, |
208 | struct drm_framebuffer *fb, |
209 | struct drm_i915_gem_object *obj); |
209 | struct drm_i915_gem_object *obj); |
210 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
210 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
211 | int x, int y); |
211 | int x, int y); |
212 | /* clock updates for mode set */ |
212 | /* clock updates for mode set */ |
213 | /* cursor updates */ |
213 | /* cursor updates */ |
214 | /* render clock increase/decrease */ |
214 | /* render clock increase/decrease */ |
215 | /* display clock increase/decrease */ |
215 | /* display clock increase/decrease */ |
216 | /* pll clock increase/decrease */ |
216 | /* pll clock increase/decrease */ |
217 | }; |
217 | }; |
218 | 218 | ||
219 | struct intel_device_info { |
219 | struct intel_device_info { |
220 | u8 gen; |
220 | u8 gen; |
221 | u8 is_mobile : 1; |
221 | u8 is_mobile : 1; |
222 | u8 is_i85x : 1; |
222 | u8 is_i85x : 1; |
223 | u8 is_i915g : 1; |
223 | u8 is_i915g : 1; |
224 | u8 is_i945gm : 1; |
224 | u8 is_i945gm : 1; |
225 | u8 is_g33 : 1; |
225 | u8 is_g33 : 1; |
226 | u8 need_gfx_hws : 1; |
226 | u8 need_gfx_hws : 1; |
227 | u8 is_g4x : 1; |
227 | u8 is_g4x : 1; |
228 | u8 is_pineview : 1; |
228 | u8 is_pineview : 1; |
229 | u8 is_broadwater : 1; |
229 | u8 is_broadwater : 1; |
230 | u8 is_crestline : 1; |
230 | u8 is_crestline : 1; |
231 | u8 is_ivybridge : 1; |
231 | u8 is_ivybridge : 1; |
232 | u8 has_fbc : 1; |
232 | u8 has_fbc : 1; |
233 | u8 has_pipe_cxsr : 1; |
233 | u8 has_pipe_cxsr : 1; |
234 | u8 has_hotplug : 1; |
234 | u8 has_hotplug : 1; |
235 | u8 cursor_needs_physical : 1; |
235 | u8 cursor_needs_physical : 1; |
236 | u8 has_overlay : 1; |
236 | u8 has_overlay : 1; |
237 | u8 overlay_needs_physical : 1; |
237 | u8 overlay_needs_physical : 1; |
238 | u8 supports_tv : 1; |
238 | u8 supports_tv : 1; |
239 | u8 has_bsd_ring : 1; |
239 | u8 has_bsd_ring : 1; |
240 | u8 has_blt_ring : 1; |
240 | u8 has_blt_ring : 1; |
241 | }; |
241 | }; |
242 | 242 | ||
243 | enum no_fbc_reason { |
243 | enum no_fbc_reason { |
244 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
244 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
245 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
245 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
246 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ |
246 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ |
247 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ |
247 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ |
248 | FBC_BAD_PLANE, /* fbc not supported on plane */ |
248 | FBC_BAD_PLANE, /* fbc not supported on plane */ |
249 | FBC_NOT_TILED, /* buffer not tiled */ |
249 | FBC_NOT_TILED, /* buffer not tiled */ |
250 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
250 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
251 | FBC_MODULE_PARAM, |
251 | FBC_MODULE_PARAM, |
252 | }; |
252 | }; |
253 | 253 | ||
254 | enum intel_pch { |
254 | enum intel_pch { |
255 | PCH_IBX, /* Ibexpeak PCH */ |
255 | PCH_IBX, /* Ibexpeak PCH */ |
256 | PCH_CPT, /* Cougarpoint PCH */ |
256 | PCH_CPT, /* Cougarpoint PCH */ |
257 | }; |
257 | }; |
258 | 258 | ||
259 | #define QUIRK_PIPEA_FORCE (1<<0) |
259 | #define QUIRK_PIPEA_FORCE (1<<0) |
260 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
260 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
261 | 261 | ||
262 | struct intel_fbdev; |
262 | struct intel_fbdev; |
263 | struct intel_fbc_work; |
263 | struct intel_fbc_work; |
264 | 264 | ||
265 | 265 | ||
266 | typedef struct drm_i915_private { |
266 | typedef struct drm_i915_private { |
267 | struct drm_device *dev; |
267 | struct drm_device *dev; |
268 | 268 | ||
269 | const struct intel_device_info *info; |
269 | const struct intel_device_info *info; |
270 | 270 | ||
271 | int has_gem; |
271 | int has_gem; |
272 | int relative_constants_mode; |
272 | int relative_constants_mode; |
273 | 273 | ||
274 | void __iomem *regs; |
274 | void __iomem *regs; |
275 | u32 gt_fifo_count; |
275 | u32 gt_fifo_count; |
276 | 276 | ||
277 | // struct intel_gmbus { |
277 | struct intel_gmbus { |
278 | // struct i2c_adapter adapter; |
278 | struct i2c_adapter adapter; |
279 | // struct i2c_adapter *force_bit; |
279 | struct i2c_adapter *force_bit; |
280 | // u32 reg0; |
280 | u32 reg0; |
281 | // } *gmbus; |
281 | } *gmbus; |
282 | 282 | ||
283 | struct pci_dev *bridge_dev; |
283 | struct pci_dev *bridge_dev; |
284 | // struct intel_ring_buffer ring[I915_NUM_RINGS]; |
284 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
285 | uint32_t next_seqno; |
285 | uint32_t next_seqno; |
286 | 286 | ||
287 | // drm_dma_handle_t *status_page_dmah; |
287 | drm_dma_handle_t *status_page_dmah; |
288 | // uint32_t counter; |
288 | // uint32_t counter; |
289 | // drm_local_map_t hws_map; |
289 | // drm_local_map_t hws_map; |
290 | // struct drm_i915_gem_object *pwrctx; |
290 | // struct drm_i915_gem_object *pwrctx; |
291 | // struct drm_i915_gem_object *renderctx; |
291 | // struct drm_i915_gem_object *renderctx; |
292 | 292 | ||
293 | // struct resource mch_res; |
293 | // struct resource mch_res; |
294 | 294 | ||
295 | unsigned int cpp; |
295 | unsigned int cpp; |
296 | int back_offset; |
296 | int back_offset; |
297 | int front_offset; |
297 | int front_offset; |
298 | int current_page; |
298 | int current_page; |
299 | int page_flipping; |
299 | int page_flipping; |
300 | 300 | ||
301 | atomic_t irq_received; |
301 | atomic_t irq_received; |
302 | 302 | ||
303 | /* protects the irq masks */ |
303 | /* protects the irq masks */ |
304 | spinlock_t irq_lock; |
304 | spinlock_t irq_lock; |
305 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
305 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
306 | u32 pipestat[2]; |
306 | u32 pipestat[2]; |
307 | u32 irq_mask; |
307 | u32 irq_mask; |
308 | u32 gt_irq_mask; |
308 | u32 gt_irq_mask; |
309 | u32 pch_irq_mask; |
309 | u32 pch_irq_mask; |
310 | 310 | ||
311 | u32 hotplug_supported_mask; |
311 | u32 hotplug_supported_mask; |
312 | // struct work_struct hotplug_work; |
312 | // struct work_struct hotplug_work; |
313 | 313 | ||
314 | int tex_lru_log_granularity; |
314 | int tex_lru_log_granularity; |
315 | int allow_batchbuffer; |
315 | int allow_batchbuffer; |
316 | struct mem_block *agp_heap; |
316 | struct mem_block *agp_heap; |
317 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
317 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
318 | int vblank_pipe; |
318 | int vblank_pipe; |
319 | int num_pipe; |
319 | int num_pipe; |
320 | 320 | ||
321 | /* For hangcheck timer */ |
321 | /* For hangcheck timer */ |
322 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
322 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
323 | // struct timer_list hangcheck_timer; |
323 | // struct timer_list hangcheck_timer; |
324 | int hangcheck_count; |
324 | int hangcheck_count; |
325 | uint32_t last_acthd; |
325 | uint32_t last_acthd; |
326 | uint32_t last_instdone; |
326 | uint32_t last_instdone; |
327 | uint32_t last_instdone1; |
327 | uint32_t last_instdone1; |
328 | 328 | ||
329 | unsigned long cfb_size; |
329 | unsigned long cfb_size; |
330 | unsigned int cfb_fb; |
330 | unsigned int cfb_fb; |
331 | enum plane cfb_plane; |
331 | enum plane cfb_plane; |
332 | int cfb_y; |
332 | int cfb_y; |
333 | // struct intel_fbc_work *fbc_work; |
333 | // struct intel_fbc_work *fbc_work; |
334 | 334 | ||
335 | // struct intel_opregion opregion; |
335 | // struct intel_opregion opregion; |
336 | 336 | ||
337 | /* overlay */ |
337 | /* overlay */ |
338 | // struct intel_overlay *overlay; |
338 | // struct intel_overlay *overlay; |
339 | 339 | ||
340 | /* LVDS info */ |
340 | /* LVDS info */ |
341 | int backlight_level; /* restore backlight to this value */ |
341 | int backlight_level; /* restore backlight to this value */ |
342 | bool backlight_enabled; |
342 | bool backlight_enabled; |
343 | struct drm_display_mode *panel_fixed_mode; |
343 | struct drm_display_mode *panel_fixed_mode; |
344 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
344 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
345 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
345 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
346 | 346 | ||
347 | /* Feature bits from the VBIOS */ |
347 | /* Feature bits from the VBIOS */ |
348 | unsigned int int_tv_support:1; |
348 | unsigned int int_tv_support:1; |
349 | unsigned int lvds_dither:1; |
349 | unsigned int lvds_dither:1; |
350 | unsigned int lvds_vbt:1; |
350 | unsigned int lvds_vbt:1; |
351 | unsigned int int_crt_support:1; |
351 | unsigned int int_crt_support:1; |
352 | unsigned int lvds_use_ssc:1; |
352 | unsigned int lvds_use_ssc:1; |
353 | int lvds_ssc_freq; |
353 | int lvds_ssc_freq; |
354 | struct { |
354 | struct { |
355 | int rate; |
355 | int rate; |
356 | int lanes; |
356 | int lanes; |
357 | int preemphasis; |
357 | int preemphasis; |
358 | int vswing; |
358 | int vswing; |
359 | 359 | ||
360 | bool initialized; |
360 | bool initialized; |
361 | bool support; |
361 | bool support; |
362 | int bpp; |
362 | int bpp; |
363 | // struct edp_power_seq pps; |
363 | // struct edp_power_seq pps; |
364 | } edp; |
364 | } edp; |
365 | bool no_aux_handshake; |
365 | bool no_aux_handshake; |
366 | 366 | ||
367 | // struct notifier_block lid_notifier; |
367 | // struct notifier_block lid_notifier; |
368 | 368 | ||
369 | int crt_ddc_pin; |
369 | int crt_ddc_pin; |
370 | // struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
370 | struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
371 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
371 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
372 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
372 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
373 | 373 | ||
374 | unsigned int fsb_freq, mem_freq, is_ddr3; |
374 | unsigned int fsb_freq, mem_freq, is_ddr3; |
375 | 375 | ||
376 | spinlock_t error_lock; |
376 | spinlock_t error_lock; |
377 | // struct drm_i915_error_state *first_error; |
377 | // struct drm_i915_error_state *first_error; |
378 | // struct work_struct error_work; |
378 | // struct work_struct error_work; |
379 | // struct completion error_completion; |
379 | // struct completion error_completion; |
380 | // struct workqueue_struct *wq; |
380 | // struct workqueue_struct *wq; |
381 | 381 | ||
382 | /* Display functions */ |
382 | /* Display functions */ |
383 | // struct drm_i915_display_funcs display; |
383 | // struct drm_i915_display_funcs display; |
384 | 384 | ||
385 | /* PCH chipset type */ |
385 | /* PCH chipset type */ |
386 | enum intel_pch pch_type; |
386 | enum intel_pch pch_type; |
387 | 387 | ||
388 | unsigned long quirks; |
388 | unsigned long quirks; |
389 | 389 | ||
390 | /* Register state */ |
390 | /* Register state */ |
391 | bool modeset_on_lid; |
391 | bool modeset_on_lid; |
392 | u8 saveLBB; |
392 | u8 saveLBB; |
393 | u32 saveDSPACNTR; |
393 | u32 saveDSPACNTR; |
394 | u32 saveDSPBCNTR; |
394 | u32 saveDSPBCNTR; |
395 | u32 saveDSPARB; |
395 | u32 saveDSPARB; |
396 | u32 saveHWS; |
396 | u32 saveHWS; |
397 | u32 savePIPEACONF; |
397 | u32 savePIPEACONF; |
398 | u32 savePIPEBCONF; |
398 | u32 savePIPEBCONF; |
399 | u32 savePIPEASRC; |
399 | u32 savePIPEASRC; |
400 | u32 savePIPEBSRC; |
400 | u32 savePIPEBSRC; |
401 | u32 saveFPA0; |
401 | u32 saveFPA0; |
402 | u32 saveFPA1; |
402 | u32 saveFPA1; |
403 | u32 saveDPLL_A; |
403 | u32 saveDPLL_A; |
404 | u32 saveDPLL_A_MD; |
404 | u32 saveDPLL_A_MD; |
405 | u32 saveHTOTAL_A; |
405 | u32 saveHTOTAL_A; |
406 | u32 saveHBLANK_A; |
406 | u32 saveHBLANK_A; |
407 | u32 saveHSYNC_A; |
407 | u32 saveHSYNC_A; |
408 | u32 saveVTOTAL_A; |
408 | u32 saveVTOTAL_A; |
409 | u32 saveVBLANK_A; |
409 | u32 saveVBLANK_A; |
410 | u32 saveVSYNC_A; |
410 | u32 saveVSYNC_A; |
411 | u32 saveBCLRPAT_A; |
411 | u32 saveBCLRPAT_A; |
412 | u32 saveTRANSACONF; |
412 | u32 saveTRANSACONF; |
413 | u32 saveTRANS_HTOTAL_A; |
413 | u32 saveTRANS_HTOTAL_A; |
414 | u32 saveTRANS_HBLANK_A; |
414 | u32 saveTRANS_HBLANK_A; |
415 | u32 saveTRANS_HSYNC_A; |
415 | u32 saveTRANS_HSYNC_A; |
416 | u32 saveTRANS_VTOTAL_A; |
416 | u32 saveTRANS_VTOTAL_A; |
417 | u32 saveTRANS_VBLANK_A; |
417 | u32 saveTRANS_VBLANK_A; |
418 | u32 saveTRANS_VSYNC_A; |
418 | u32 saveTRANS_VSYNC_A; |
419 | u32 savePIPEASTAT; |
419 | u32 savePIPEASTAT; |
420 | u32 saveDSPASTRIDE; |
420 | u32 saveDSPASTRIDE; |
421 | u32 saveDSPASIZE; |
421 | u32 saveDSPASIZE; |
422 | u32 saveDSPAPOS; |
422 | u32 saveDSPAPOS; |
423 | u32 saveDSPAADDR; |
423 | u32 saveDSPAADDR; |
424 | u32 saveDSPASURF; |
424 | u32 saveDSPASURF; |
425 | u32 saveDSPATILEOFF; |
425 | u32 saveDSPATILEOFF; |
426 | u32 savePFIT_PGM_RATIOS; |
426 | u32 savePFIT_PGM_RATIOS; |
427 | u32 saveBLC_HIST_CTL; |
427 | u32 saveBLC_HIST_CTL; |
428 | u32 saveBLC_PWM_CTL; |
428 | u32 saveBLC_PWM_CTL; |
429 | u32 saveBLC_PWM_CTL2; |
429 | u32 saveBLC_PWM_CTL2; |
430 | u32 saveBLC_CPU_PWM_CTL; |
430 | u32 saveBLC_CPU_PWM_CTL; |
431 | u32 saveBLC_CPU_PWM_CTL2; |
431 | u32 saveBLC_CPU_PWM_CTL2; |
432 | u32 saveFPB0; |
432 | u32 saveFPB0; |
433 | u32 saveFPB1; |
433 | u32 saveFPB1; |
434 | u32 saveDPLL_B; |
434 | u32 saveDPLL_B; |
435 | u32 saveDPLL_B_MD; |
435 | u32 saveDPLL_B_MD; |
436 | u32 saveHTOTAL_B; |
436 | u32 saveHTOTAL_B; |
437 | u32 saveHBLANK_B; |
437 | u32 saveHBLANK_B; |
438 | u32 saveHSYNC_B; |
438 | u32 saveHSYNC_B; |
439 | u32 saveVTOTAL_B; |
439 | u32 saveVTOTAL_B; |
440 | u32 saveVBLANK_B; |
440 | u32 saveVBLANK_B; |
441 | u32 saveVSYNC_B; |
441 | u32 saveVSYNC_B; |
442 | u32 saveBCLRPAT_B; |
442 | u32 saveBCLRPAT_B; |
443 | u32 saveTRANSBCONF; |
443 | u32 saveTRANSBCONF; |
444 | u32 saveTRANS_HTOTAL_B; |
444 | u32 saveTRANS_HTOTAL_B; |
445 | u32 saveTRANS_HBLANK_B; |
445 | u32 saveTRANS_HBLANK_B; |
446 | u32 saveTRANS_HSYNC_B; |
446 | u32 saveTRANS_HSYNC_B; |
447 | u32 saveTRANS_VTOTAL_B; |
447 | u32 saveTRANS_VTOTAL_B; |
448 | u32 saveTRANS_VBLANK_B; |
448 | u32 saveTRANS_VBLANK_B; |
449 | u32 saveTRANS_VSYNC_B; |
449 | u32 saveTRANS_VSYNC_B; |
450 | u32 savePIPEBSTAT; |
450 | u32 savePIPEBSTAT; |
451 | u32 saveDSPBSTRIDE; |
451 | u32 saveDSPBSTRIDE; |
452 | u32 saveDSPBSIZE; |
452 | u32 saveDSPBSIZE; |
453 | u32 saveDSPBPOS; |
453 | u32 saveDSPBPOS; |
454 | u32 saveDSPBADDR; |
454 | u32 saveDSPBADDR; |
455 | u32 saveDSPBSURF; |
455 | u32 saveDSPBSURF; |
456 | u32 saveDSPBTILEOFF; |
456 | u32 saveDSPBTILEOFF; |
457 | u32 saveVGA0; |
457 | u32 saveVGA0; |
458 | u32 saveVGA1; |
458 | u32 saveVGA1; |
459 | u32 saveVGA_PD; |
459 | u32 saveVGA_PD; |
460 | u32 saveVGACNTRL; |
460 | u32 saveVGACNTRL; |
461 | u32 saveADPA; |
461 | u32 saveADPA; |
462 | u32 saveLVDS; |
462 | u32 saveLVDS; |
463 | u32 savePP_ON_DELAYS; |
463 | u32 savePP_ON_DELAYS; |
464 | u32 savePP_OFF_DELAYS; |
464 | u32 savePP_OFF_DELAYS; |
465 | u32 saveDVOA; |
465 | u32 saveDVOA; |
466 | u32 saveDVOB; |
466 | u32 saveDVOB; |
467 | u32 saveDVOC; |
467 | u32 saveDVOC; |
468 | u32 savePP_ON; |
468 | u32 savePP_ON; |
469 | u32 savePP_OFF; |
469 | u32 savePP_OFF; |
470 | u32 savePP_CONTROL; |
470 | u32 savePP_CONTROL; |
471 | u32 savePP_DIVISOR; |
471 | u32 savePP_DIVISOR; |
472 | u32 savePFIT_CONTROL; |
472 | u32 savePFIT_CONTROL; |
473 | u32 save_palette_a[256]; |
473 | u32 save_palette_a[256]; |
474 | u32 save_palette_b[256]; |
474 | u32 save_palette_b[256]; |
475 | u32 saveDPFC_CB_BASE; |
475 | u32 saveDPFC_CB_BASE; |
476 | u32 saveFBC_CFB_BASE; |
476 | u32 saveFBC_CFB_BASE; |
477 | u32 saveFBC_LL_BASE; |
477 | u32 saveFBC_LL_BASE; |
478 | u32 saveFBC_CONTROL; |
478 | u32 saveFBC_CONTROL; |
479 | u32 saveFBC_CONTROL2; |
479 | u32 saveFBC_CONTROL2; |
480 | u32 saveIER; |
480 | u32 saveIER; |
481 | u32 saveIIR; |
481 | u32 saveIIR; |
482 | u32 saveIMR; |
482 | u32 saveIMR; |
483 | u32 saveDEIER; |
483 | u32 saveDEIER; |
484 | u32 saveDEIMR; |
484 | u32 saveDEIMR; |
485 | u32 saveGTIER; |
485 | u32 saveGTIER; |
486 | u32 saveGTIMR; |
486 | u32 saveGTIMR; |
487 | u32 saveFDI_RXA_IMR; |
487 | u32 saveFDI_RXA_IMR; |
488 | u32 saveFDI_RXB_IMR; |
488 | u32 saveFDI_RXB_IMR; |
489 | u32 saveCACHE_MODE_0; |
489 | u32 saveCACHE_MODE_0; |
490 | u32 saveMI_ARB_STATE; |
490 | u32 saveMI_ARB_STATE; |
491 | u32 saveSWF0[16]; |
491 | u32 saveSWF0[16]; |
492 | u32 saveSWF1[16]; |
492 | u32 saveSWF1[16]; |
493 | u32 saveSWF2[3]; |
493 | u32 saveSWF2[3]; |
494 | u8 saveMSR; |
494 | u8 saveMSR; |
495 | u8 saveSR[8]; |
495 | u8 saveSR[8]; |
496 | u8 saveGR[25]; |
496 | u8 saveGR[25]; |
497 | u8 saveAR_INDEX; |
497 | u8 saveAR_INDEX; |
498 | u8 saveAR[21]; |
498 | u8 saveAR[21]; |
499 | u8 saveDACMASK; |
499 | u8 saveDACMASK; |
500 | u8 saveCR[37]; |
500 | u8 saveCR[37]; |
501 | uint64_t saveFENCE[16]; |
501 | uint64_t saveFENCE[16]; |
502 | u32 saveCURACNTR; |
502 | u32 saveCURACNTR; |
503 | u32 saveCURAPOS; |
503 | u32 saveCURAPOS; |
504 | u32 saveCURABASE; |
504 | u32 saveCURABASE; |
505 | u32 saveCURBCNTR; |
505 | u32 saveCURBCNTR; |
506 | u32 saveCURBPOS; |
506 | u32 saveCURBPOS; |
507 | u32 saveCURBBASE; |
507 | u32 saveCURBBASE; |
508 | u32 saveCURSIZE; |
508 | u32 saveCURSIZE; |
509 | u32 saveDP_B; |
509 | u32 saveDP_B; |
510 | u32 saveDP_C; |
510 | u32 saveDP_C; |
511 | u32 saveDP_D; |
511 | u32 saveDP_D; |
512 | u32 savePIPEA_GMCH_DATA_M; |
512 | u32 savePIPEA_GMCH_DATA_M; |
513 | u32 savePIPEB_GMCH_DATA_M; |
513 | u32 savePIPEB_GMCH_DATA_M; |
514 | u32 savePIPEA_GMCH_DATA_N; |
514 | u32 savePIPEA_GMCH_DATA_N; |
515 | u32 savePIPEB_GMCH_DATA_N; |
515 | u32 savePIPEB_GMCH_DATA_N; |
516 | u32 savePIPEA_DP_LINK_M; |
516 | u32 savePIPEA_DP_LINK_M; |
517 | u32 savePIPEB_DP_LINK_M; |
517 | u32 savePIPEB_DP_LINK_M; |
518 | u32 savePIPEA_DP_LINK_N; |
518 | u32 savePIPEA_DP_LINK_N; |
519 | u32 savePIPEB_DP_LINK_N; |
519 | u32 savePIPEB_DP_LINK_N; |
520 | u32 saveFDI_RXA_CTL; |
520 | u32 saveFDI_RXA_CTL; |
521 | u32 saveFDI_TXA_CTL; |
521 | u32 saveFDI_TXA_CTL; |
522 | u32 saveFDI_RXB_CTL; |
522 | u32 saveFDI_RXB_CTL; |
523 | u32 saveFDI_TXB_CTL; |
523 | u32 saveFDI_TXB_CTL; |
524 | u32 savePFA_CTL_1; |
524 | u32 savePFA_CTL_1; |
525 | u32 savePFB_CTL_1; |
525 | u32 savePFB_CTL_1; |
526 | u32 savePFA_WIN_SZ; |
526 | u32 savePFA_WIN_SZ; |
527 | u32 savePFB_WIN_SZ; |
527 | u32 savePFB_WIN_SZ; |
528 | u32 savePFA_WIN_POS; |
528 | u32 savePFA_WIN_POS; |
529 | u32 savePFB_WIN_POS; |
529 | u32 savePFB_WIN_POS; |
530 | u32 savePCH_DREF_CONTROL; |
530 | u32 savePCH_DREF_CONTROL; |
531 | u32 saveDISP_ARB_CTL; |
531 | u32 saveDISP_ARB_CTL; |
532 | u32 savePIPEA_DATA_M1; |
532 | u32 savePIPEA_DATA_M1; |
533 | u32 savePIPEA_DATA_N1; |
533 | u32 savePIPEA_DATA_N1; |
534 | u32 savePIPEA_LINK_M1; |
534 | u32 savePIPEA_LINK_M1; |
535 | u32 savePIPEA_LINK_N1; |
535 | u32 savePIPEA_LINK_N1; |
536 | u32 savePIPEB_DATA_M1; |
536 | u32 savePIPEB_DATA_M1; |
537 | u32 savePIPEB_DATA_N1; |
537 | u32 savePIPEB_DATA_N1; |
538 | u32 savePIPEB_LINK_M1; |
538 | u32 savePIPEB_LINK_M1; |
539 | u32 savePIPEB_LINK_N1; |
539 | u32 savePIPEB_LINK_N1; |
540 | u32 saveMCHBAR_RENDER_STANDBY; |
540 | u32 saveMCHBAR_RENDER_STANDBY; |
541 | u32 savePCH_PORT_HOTPLUG; |
541 | u32 savePCH_PORT_HOTPLUG; |
542 | 542 | ||
543 | struct { |
543 | struct { |
544 | /** Bridge to intel-gtt-ko */ |
544 | /** Bridge to intel-gtt-ko */ |
545 | const struct intel_gtt *gtt; |
545 | const struct intel_gtt *gtt; |
546 | /** Memory allocator for GTT stolen memory */ |
546 | /** Memory allocator for GTT stolen memory */ |
547 | // struct drm_mm stolen; |
547 | // struct drm_mm stolen; |
548 | /** Memory allocator for GTT */ |
548 | /** Memory allocator for GTT */ |
549 | // struct drm_mm gtt_space; |
549 | // struct drm_mm gtt_space; |
550 | /** List of all objects in gtt_space. Used to restore gtt |
550 | /** List of all objects in gtt_space. Used to restore gtt |
551 | * mappings on resume */ |
551 | * mappings on resume */ |
552 | struct list_head gtt_list; |
552 | struct list_head gtt_list; |
553 | 553 | ||
554 | /** Usable portion of the GTT for GEM */ |
554 | /** Usable portion of the GTT for GEM */ |
555 | unsigned long gtt_start; |
555 | unsigned long gtt_start; |
556 | unsigned long gtt_mappable_end; |
556 | unsigned long gtt_mappable_end; |
557 | unsigned long gtt_end; |
557 | unsigned long gtt_end; |
558 | 558 | ||
559 | // struct io_mapping *gtt_mapping; |
559 | // struct io_mapping *gtt_mapping; |
560 | int gtt_mtrr; |
560 | int gtt_mtrr; |
561 | 561 | ||
562 | // struct shrinker inactive_shrinker; |
562 | // struct shrinker inactive_shrinker; |
563 | 563 | ||
564 | /** |
564 | /** |
565 | * List of objects currently involved in rendering. |
565 | * List of objects currently involved in rendering. |
566 | * |
566 | * |
567 | * Includes buffers having the contents of their GPU caches |
567 | * Includes buffers having the contents of their GPU caches |
568 | * flushed, not necessarily primitives. last_rendering_seqno |
568 | * flushed, not necessarily primitives. last_rendering_seqno |
569 | * represents when the rendering involved will be completed. |
569 | * represents when the rendering involved will be completed. |
570 | * |
570 | * |
571 | * A reference is held on the buffer while on this list. |
571 | * A reference is held on the buffer while on this list. |
572 | */ |
572 | */ |
573 | struct list_head active_list; |
573 | struct list_head active_list; |
574 | 574 | ||
575 | /** |
575 | /** |
576 | * List of objects which are not in the ringbuffer but which |
576 | * List of objects which are not in the ringbuffer but which |
577 | * still have a write_domain which needs to be flushed before |
577 | * still have a write_domain which needs to be flushed before |
578 | * unbinding. |
578 | * unbinding. |
579 | * |
579 | * |
580 | * last_rendering_seqno is 0 while an object is in this list. |
580 | * last_rendering_seqno is 0 while an object is in this list. |
581 | * |
581 | * |
582 | * A reference is held on the buffer while on this list. |
582 | * A reference is held on the buffer while on this list. |
583 | */ |
583 | */ |
584 | struct list_head flushing_list; |
584 | struct list_head flushing_list; |
585 | 585 | ||
586 | /** |
586 | /** |
587 | * LRU list of objects which are not in the ringbuffer and |
587 | * LRU list of objects which are not in the ringbuffer and |
588 | * are ready to unbind, but are still in the GTT. |
588 | * are ready to unbind, but are still in the GTT. |
589 | * |
589 | * |
590 | * last_rendering_seqno is 0 while an object is in this list. |
590 | * last_rendering_seqno is 0 while an object is in this list. |
591 | * |
591 | * |
592 | * A reference is not held on the buffer while on this list, |
592 | * A reference is not held on the buffer while on this list, |
593 | * as merely being GTT-bound shouldn't prevent its being |
593 | * as merely being GTT-bound shouldn't prevent its being |
594 | * freed, and we'll pull it off the list in the free path. |
594 | * freed, and we'll pull it off the list in the free path. |
595 | */ |
595 | */ |
596 | struct list_head inactive_list; |
596 | struct list_head inactive_list; |
597 | 597 | ||
598 | /** |
598 | /** |
599 | * LRU list of objects which are not in the ringbuffer but |
599 | * LRU list of objects which are not in the ringbuffer but |
600 | * are still pinned in the GTT. |
600 | * are still pinned in the GTT. |
601 | */ |
601 | */ |
602 | struct list_head pinned_list; |
602 | struct list_head pinned_list; |
603 | 603 | ||
604 | /** LRU list of objects with fence regs on them. */ |
604 | /** LRU list of objects with fence regs on them. */ |
605 | struct list_head fence_list; |
605 | struct list_head fence_list; |
606 | 606 | ||
607 | /** |
607 | /** |
608 | * List of objects currently pending being freed. |
608 | * List of objects currently pending being freed. |
609 | * |
609 | * |
610 | * These objects are no longer in use, but due to a signal |
610 | * These objects are no longer in use, but due to a signal |
611 | * we were prevented from freeing them at the appointed time. |
611 | * we were prevented from freeing them at the appointed time. |
612 | */ |
612 | */ |
613 | struct list_head deferred_free_list; |
613 | struct list_head deferred_free_list; |
614 | 614 | ||
615 | /** |
615 | /** |
616 | * We leave the user IRQ off as much as possible, |
616 | * We leave the user IRQ off as much as possible, |
617 | * but this means that requests will finish and never |
617 | * but this means that requests will finish and never |
618 | * be retired once the system goes idle. Set a timer to |
618 | * be retired once the system goes idle. Set a timer to |
619 | * fire periodically while the ring is running. When it |
619 | * fire periodically while the ring is running. When it |
620 | * fires, go retire requests. |
620 | * fires, go retire requests. |
621 | */ |
621 | */ |
622 | // struct delayed_work retire_work; |
622 | // struct delayed_work retire_work; |
623 | 623 | ||
624 | /** |
624 | /** |
625 | * Are we in a non-interruptible section of code like |
625 | * Are we in a non-interruptible section of code like |
626 | * modesetting? |
626 | * modesetting? |
627 | */ |
627 | */ |
628 | bool interruptible; |
628 | bool interruptible; |
629 | 629 | ||
630 | /** |
630 | /** |
631 | * Flag if the X Server, and thus DRM, is not currently in |
631 | * Flag if the X Server, and thus DRM, is not currently in |
632 | * control of the device. |
632 | * control of the device. |
633 | * |
633 | * |
634 | * This is set between LeaveVT and EnterVT. It needs to be |
634 | * This is set between LeaveVT and EnterVT. It needs to be |
635 | * replaced with a semaphore. It also needs to be |
635 | * replaced with a semaphore. It also needs to be |
636 | * transitioned away from for kernel modesetting. |
636 | * transitioned away from for kernel modesetting. |
637 | */ |
637 | */ |
638 | int suspended; |
638 | int suspended; |
639 | 639 | ||
640 | /** |
640 | /** |
641 | * Flag if the hardware appears to be wedged. |
641 | * Flag if the hardware appears to be wedged. |
642 | * |
642 | * |
643 | * This is set when attempts to idle the device timeout. |
643 | * This is set when attempts to idle the device timeout. |
644 | * It prevents command submission from occurring and makes |
644 | * It prevents command submission from occurring and makes |
645 | * every pending request fail |
645 | * every pending request fail |
646 | */ |
646 | */ |
647 | atomic_t wedged; |
647 | atomic_t wedged; |
648 | 648 | ||
649 | /** Bit 6 swizzling required for X tiling */ |
649 | /** Bit 6 swizzling required for X tiling */ |
650 | uint32_t bit_6_swizzle_x; |
650 | uint32_t bit_6_swizzle_x; |
651 | /** Bit 6 swizzling required for Y tiling */ |
651 | /** Bit 6 swizzling required for Y tiling */ |
652 | uint32_t bit_6_swizzle_y; |
652 | uint32_t bit_6_swizzle_y; |
653 | 653 | ||
654 | /* storage for physical objects */ |
654 | /* storage for physical objects */ |
655 | // struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; |
655 | // struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; |
656 | 656 | ||
657 | /* accounting, useful for userland debugging */ |
657 | /* accounting, useful for userland debugging */ |
658 | size_t gtt_total; |
658 | size_t gtt_total; |
659 | size_t mappable_gtt_total; |
659 | size_t mappable_gtt_total; |
660 | size_t object_memory; |
660 | size_t object_memory; |
661 | u32 object_count; |
661 | u32 object_count; |
662 | } mm; |
662 | } mm; |
663 | // struct sdvo_device_mapping sdvo_mappings[2]; |
663 | // struct sdvo_device_mapping sdvo_mappings[2]; |
664 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
664 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
665 | unsigned int lvds_border_bits; |
665 | unsigned int lvds_border_bits; |
666 | /* Panel fitter placement and size for Ironlake+ */ |
666 | /* Panel fitter placement and size for Ironlake+ */ |
667 | u32 pch_pf_pos, pch_pf_size; |
667 | u32 pch_pf_pos, pch_pf_size; |
668 | int panel_t3, panel_t12; |
668 | int panel_t3, panel_t12; |
669 | 669 | ||
670 | // struct drm_crtc *plane_to_crtc_mapping[2]; |
670 | struct drm_crtc *plane_to_crtc_mapping[2]; |
671 | // struct drm_crtc *pipe_to_crtc_mapping[2]; |
671 | struct drm_crtc *pipe_to_crtc_mapping[2]; |
672 | // wait_queue_head_t pending_flip_queue; |
672 | // wait_queue_head_t pending_flip_queue; |
673 | bool flip_pending_is_done; |
673 | bool flip_pending_is_done; |
674 | 674 | ||
675 | /* Reclocking support */ |
675 | /* Reclocking support */ |
676 | bool render_reclock_avail; |
676 | bool render_reclock_avail; |
677 | bool lvds_downclock_avail; |
677 | bool lvds_downclock_avail; |
678 | /* indicates the reduced downclock for LVDS*/ |
678 | /* indicates the reduced downclock for LVDS*/ |
679 | int lvds_downclock; |
679 | int lvds_downclock; |
680 | // struct work_struct idle_work; |
680 | // struct work_struct idle_work; |
681 | // struct timer_list idle_timer; |
681 | // struct timer_list idle_timer; |
682 | bool busy; |
682 | bool busy; |
683 | u16 orig_clock; |
683 | u16 orig_clock; |
684 | int child_dev_num; |
684 | int child_dev_num; |
685 | // struct child_device_config *child_dev; |
685 | // struct child_device_config *child_dev; |
686 | // struct drm_connector *int_lvds_connector; |
686 | // struct drm_connector *int_lvds_connector; |
687 | // struct drm_connector *int_edp_connector; |
687 | // struct drm_connector *int_edp_connector; |
688 | 688 | ||
689 | bool mchbar_need_disable; |
689 | bool mchbar_need_disable; |
690 | 690 | ||
691 | // struct work_struct rps_work; |
691 | // struct work_struct rps_work; |
692 | spinlock_t rps_lock; |
692 | spinlock_t rps_lock; |
693 | u32 pm_iir; |
693 | u32 pm_iir; |
694 | 694 | ||
695 | u8 cur_delay; |
695 | u8 cur_delay; |
696 | u8 min_delay; |
696 | u8 min_delay; |
697 | u8 max_delay; |
697 | u8 max_delay; |
698 | u8 fmax; |
698 | u8 fmax; |
699 | u8 fstart; |
699 | u8 fstart; |
700 | 700 | ||
701 | u64 last_count1; |
701 | u64 last_count1; |
702 | unsigned long last_time1; |
702 | unsigned long last_time1; |
703 | u64 last_count2; |
703 | u64 last_count2; |
704 | // struct timespec last_time2; |
704 | // struct timespec last_time2; |
705 | unsigned long gfx_power; |
705 | unsigned long gfx_power; |
706 | int c_m; |
706 | int c_m; |
707 | int r_t; |
707 | int r_t; |
708 | u8 corr; |
708 | u8 corr; |
709 | spinlock_t *mchdev_lock; |
709 | spinlock_t *mchdev_lock; |
710 | 710 | ||
711 | // enum no_fbc_reason no_fbc_reason; |
711 | // enum no_fbc_reason no_fbc_reason; |
712 | 712 | ||
713 | // struct drm_mm_node *compressed_fb; |
713 | // struct drm_mm_node *compressed_fb; |
714 | // struct drm_mm_node *compressed_llb; |
714 | // struct drm_mm_node *compressed_llb; |
715 | 715 | ||
716 | unsigned long last_gpu_reset; |
716 | unsigned long last_gpu_reset; |
717 | 717 | ||
718 | /* list of fbdev register on this device */ |
718 | /* list of fbdev register on this device */ |
719 | // struct intel_fbdev *fbdev; |
719 | // struct intel_fbdev *fbdev; |
720 | 720 | ||
721 | // struct backlight_device *backlight; |
721 | // struct backlight_device *backlight; |
722 | 722 | ||
723 | // struct drm_property *broadcast_rgb_property; |
723 | // struct drm_property *broadcast_rgb_property; |
724 | // struct drm_property *force_audio_property; |
724 | // struct drm_property *force_audio_property; |
725 | 725 | ||
726 | atomic_t forcewake_count; |
726 | atomic_t forcewake_count; |
727 | } drm_i915_private_t; |
727 | } drm_i915_private_t; |
728 | 728 | ||
729 | enum i915_cache_level { |
729 | enum i915_cache_level { |
730 | I915_CACHE_NONE, |
730 | I915_CACHE_NONE, |
731 | I915_CACHE_LLC, |
731 | I915_CACHE_LLC, |
732 | I915_CACHE_LLC_MLC, /* gen6+ */ |
732 | I915_CACHE_LLC_MLC, /* gen6+ */ |
733 | }; |
733 | }; |
734 | 734 | ||
735 | 735 | ||
736 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
736 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
737 | 737 | ||
738 | /** |
738 | /** |
739 | * Request queue structure. |
739 | * Request queue structure. |
740 | * |
740 | * |
741 | * The request queue allows us to note sequence numbers that have been emitted |
741 | * The request queue allows us to note sequence numbers that have been emitted |
742 | * and may be associated with active buffers to be retired. |
742 | * and may be associated with active buffers to be retired. |
743 | * |
743 | * |
744 | * By keeping this list, we can avoid having to do questionable |
744 | * By keeping this list, we can avoid having to do questionable |
745 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate |
745 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate |
746 | * an emission time with seqnos for tracking how far ahead of the GPU we are. |
746 | * an emission time with seqnos for tracking how far ahead of the GPU we are. |
747 | */ |
747 | */ |
748 | struct drm_i915_gem_request { |
748 | struct drm_i915_gem_request { |
749 | /** On Which ring this request was generated */ |
749 | /** On Which ring this request was generated */ |
750 | struct intel_ring_buffer *ring; |
750 | struct intel_ring_buffer *ring; |
751 | 751 | ||
752 | /** GEM sequence number associated with this request. */ |
752 | /** GEM sequence number associated with this request. */ |
753 | uint32_t seqno; |
753 | uint32_t seqno; |
754 | 754 | ||
755 | /** Time at which this request was emitted, in jiffies. */ |
755 | /** Time at which this request was emitted, in jiffies. */ |
756 | unsigned long emitted_jiffies; |
756 | unsigned long emitted_jiffies; |
757 | 757 | ||
758 | /** global list entry for this request */ |
758 | /** global list entry for this request */ |
759 | struct list_head list; |
759 | struct list_head list; |
760 | 760 | ||
761 | struct drm_i915_file_private *file_priv; |
761 | struct drm_i915_file_private *file_priv; |
762 | /** file_priv list entry for this request */ |
762 | /** file_priv list entry for this request */ |
763 | struct list_head client_list; |
763 | struct list_head client_list; |
764 | }; |
764 | }; |
765 | 765 | ||
766 | struct drm_i915_file_private { |
766 | struct drm_i915_file_private { |
767 | struct { |
767 | struct { |
768 | // struct spinlock lock; |
768 | // struct spinlock lock; |
769 | struct list_head request_list; |
769 | struct list_head request_list; |
770 | } mm; |
770 | } mm; |
771 | }; |
771 | }; |
772 | 772 | ||
773 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
773 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
774 | 774 | ||
775 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) |
775 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) |
776 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) |
776 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) |
777 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
777 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
778 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) |
778 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) |
779 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
779 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
780 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) |
780 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) |
781 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) |
781 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) |
782 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
782 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
783 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
783 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
784 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) |
784 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) |
785 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
785 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
786 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
786 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
787 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) |
787 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) |
788 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) |
788 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) |
789 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
789 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
790 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
790 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
791 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) |
791 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) |
792 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) |
792 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) |
793 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
793 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
794 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
794 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
795 | 795 | ||
796 | /* |
796 | /* |
797 | * The genX designation typically refers to the render engine, so render |
797 | * The genX designation typically refers to the render engine, so render |
798 | * capability related checks should use IS_GEN, while display and other checks |
798 | * capability related checks should use IS_GEN, while display and other checks |
799 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular |
799 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular |
800 | * chips, etc.). |
800 | * chips, etc.). |
801 | */ |
801 | */ |
802 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
802 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
803 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) |
803 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) |
804 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) |
804 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) |
805 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) |
805 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) |
806 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) |
806 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) |
807 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
807 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
808 | 808 | ||
809 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) |
809 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) |
810 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) |
810 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) |
811 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
811 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
812 | 812 | ||
813 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
813 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
814 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
814 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
815 | 815 | ||
816 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
816 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
817 | * rows, which changed the alignment requirements and fence programming. |
817 | * rows, which changed the alignment requirements and fence programming. |
818 | */ |
818 | */ |
819 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ |
819 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ |
820 | IS_I915GM(dev))) |
820 | IS_I915GM(dev))) |
821 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) |
821 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) |
822 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
822 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
823 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
823 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
824 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) |
824 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) |
825 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
825 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
826 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
826 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
827 | /* dsparb controlled by hw only */ |
827 | /* dsparb controlled by hw only */ |
828 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
828 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
829 | 829 | ||
830 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) |
830 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) |
831 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
831 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
832 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
832 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
833 | 833 | ||
834 | #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
834 | #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
835 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
835 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
836 | 836 | ||
837 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
837 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
838 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
838 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
839 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
839 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
840 | 840 | ||
841 | //#include "i915_trace.h" |
841 | //#include "i915_trace.h" |
842 | 842 | ||
843 | extern int i915_max_ioctl; |
843 | extern int i915_max_ioctl; |
844 | extern unsigned int i915_fbpercrtc; |
844 | extern unsigned int i915_fbpercrtc; |
845 | extern int i915_panel_ignore_lid; |
845 | extern int i915_panel_ignore_lid; |
846 | extern unsigned int i915_powersave; |
846 | extern unsigned int i915_powersave; |
847 | extern unsigned int i915_semaphores; |
847 | extern unsigned int i915_semaphores; |
848 | extern unsigned int i915_lvds_downclock; |
848 | extern unsigned int i915_lvds_downclock; |
849 | extern unsigned int i915_panel_use_ssc; |
849 | extern unsigned int i915_panel_use_ssc; |
850 | extern int i915_vbt_sdvo_panel_type; |
850 | extern int i915_vbt_sdvo_panel_type; |
851 | extern unsigned int i915_enable_rc6; |
851 | extern unsigned int i915_enable_rc6; |
852 | extern unsigned int i915_enable_fbc; |
852 | extern unsigned int i915_enable_fbc; |
853 | extern bool i915_enable_hangcheck; |
853 | extern bool i915_enable_hangcheck; |
854 | 854 | ||
855 | extern int i915_resume(struct drm_device *dev); |
855 | extern int i915_resume(struct drm_device *dev); |
856 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
856 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
857 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); |
857 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); |
858 | 858 | ||
859 | /* i915_dma.c */ |
859 | /* i915_dma.c */ |
860 | extern void i915_kernel_lost_context(struct drm_device * dev); |
860 | extern void i915_kernel_lost_context(struct drm_device * dev); |
861 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
861 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
862 | extern int i915_driver_unload(struct drm_device *); |
862 | extern int i915_driver_unload(struct drm_device *); |
863 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
863 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
864 | extern void i915_driver_lastclose(struct drm_device * dev); |
864 | extern void i915_driver_lastclose(struct drm_device * dev); |
865 | extern void i915_driver_preclose(struct drm_device *dev, |
865 | extern void i915_driver_preclose(struct drm_device *dev, |
866 | struct drm_file *file_priv); |
866 | struct drm_file *file_priv); |
867 | extern void i915_driver_postclose(struct drm_device *dev, |
867 | extern void i915_driver_postclose(struct drm_device *dev, |
868 | struct drm_file *file_priv); |
868 | struct drm_file *file_priv); |
869 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
869 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
870 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
870 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
871 | unsigned long arg); |
871 | unsigned long arg); |
872 | extern int i915_emit_box(struct drm_device *dev, |
872 | extern int i915_emit_box(struct drm_device *dev, |
873 | struct drm_clip_rect *box, |
873 | struct drm_clip_rect *box, |
874 | int DR1, int DR4); |
874 | int DR1, int DR4); |
875 | extern int i915_reset(struct drm_device *dev, u8 flags); |
875 | extern int i915_reset(struct drm_device *dev, u8 flags); |
876 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
876 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
877 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
877 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
878 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
878 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
879 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
879 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
880 | 880 | ||
881 | 881 | ||
882 | /* i915_irq.c */ |
882 | /* i915_irq.c */ |
883 | void i915_hangcheck_elapsed(unsigned long data); |
883 | void i915_hangcheck_elapsed(unsigned long data); |
884 | void i915_handle_error(struct drm_device *dev, bool wedged); |
884 | void i915_handle_error(struct drm_device *dev, bool wedged); |
885 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
885 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
886 | struct drm_file *file_priv); |
886 | struct drm_file *file_priv); |
887 | extern int i915_irq_wait(struct drm_device *dev, void *data, |
887 | extern int i915_irq_wait(struct drm_device *dev, void *data, |
888 | struct drm_file *file_priv); |
888 | struct drm_file *file_priv); |
889 | 889 | ||
890 | extern void intel_irq_init(struct drm_device *dev); |
890 | extern void intel_irq_init(struct drm_device *dev); |
891 | 891 | ||
892 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
892 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
893 | struct drm_file *file_priv); |
893 | struct drm_file *file_priv); |
894 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
894 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
895 | struct drm_file *file_priv); |
895 | struct drm_file *file_priv); |
896 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
896 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
897 | struct drm_file *file_priv); |
897 | struct drm_file *file_priv); |
898 | 898 | ||
899 | void |
899 | void |
900 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
900 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
901 | 901 | ||
902 | void |
902 | void |
903 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
903 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
904 | 904 | ||
905 | void intel_enable_asle (struct drm_device *dev); |
905 | void intel_enable_asle (struct drm_device *dev); |
906 | 906 | ||
907 | #ifdef CONFIG_DEBUG_FS |
907 | #ifdef CONFIG_DEBUG_FS |
908 | extern void i915_destroy_error_state(struct drm_device *dev); |
908 | extern void i915_destroy_error_state(struct drm_device *dev); |
909 | #else |
909 | #else |
910 | #define i915_destroy_error_state(x) |
910 | #define i915_destroy_error_state(x) |
911 | #endif |
911 | #endif |
912 | 912 | ||
913 | 913 | ||
914 | /* i915_mem.c */ |
914 | /* i915_mem.c */ |
915 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
915 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
916 | struct drm_file *file_priv); |
916 | struct drm_file *file_priv); |
917 | extern int i915_mem_free(struct drm_device *dev, void *data, |
917 | extern int i915_mem_free(struct drm_device *dev, void *data, |
918 | struct drm_file *file_priv); |
918 | struct drm_file *file_priv); |
919 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, |
919 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, |
920 | struct drm_file *file_priv); |
920 | struct drm_file *file_priv); |
921 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, |
921 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, |
922 | struct drm_file *file_priv); |
922 | struct drm_file *file_priv); |
923 | extern void i915_mem_takedown(struct mem_block **heap); |
923 | extern void i915_mem_takedown(struct mem_block **heap); |
924 | extern void i915_mem_release(struct drm_device * dev, |
924 | extern void i915_mem_release(struct drm_device * dev, |
925 | struct drm_file *file_priv, struct mem_block *heap); |
925 | struct drm_file *file_priv, struct mem_block *heap); |
926 | /* i915_gem.c */ |
926 | /* i915_gem.c */ |
927 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, |
927 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, |
928 | struct drm_file *file_priv); |
928 | struct drm_file *file_priv); |
929 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
929 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
930 | struct drm_file *file_priv); |
930 | struct drm_file *file_priv); |
931 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
931 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
932 | struct drm_file *file_priv); |
932 | struct drm_file *file_priv); |
933 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
933 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
934 | struct drm_file *file_priv); |
934 | struct drm_file *file_priv); |
935 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
935 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
936 | struct drm_file *file_priv); |
936 | struct drm_file *file_priv); |
937 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
937 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
938 | struct drm_file *file_priv); |
938 | struct drm_file *file_priv); |
939 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
939 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
940 | struct drm_file *file_priv); |
940 | struct drm_file *file_priv); |
941 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
941 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
942 | struct drm_file *file_priv); |
942 | struct drm_file *file_priv); |
943 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
943 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
944 | struct drm_file *file_priv); |
944 | struct drm_file *file_priv); |
945 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
945 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
946 | struct drm_file *file_priv); |
946 | struct drm_file *file_priv); |
947 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
947 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
948 | struct drm_file *file_priv); |
948 | struct drm_file *file_priv); |
949 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
949 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
950 | struct drm_file *file_priv); |
950 | struct drm_file *file_priv); |
951 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
951 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
952 | struct drm_file *file_priv); |
952 | struct drm_file *file_priv); |
953 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
953 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
954 | struct drm_file *file_priv); |
954 | struct drm_file *file_priv); |
955 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
955 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
956 | struct drm_file *file_priv); |
956 | struct drm_file *file_priv); |
957 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
957 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
958 | struct drm_file *file_priv); |
958 | struct drm_file *file_priv); |
959 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
959 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
960 | struct drm_file *file_priv); |
960 | struct drm_file *file_priv); |
961 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
961 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
962 | struct drm_file *file_priv); |
962 | struct drm_file *file_priv); |
963 | int i915_gem_get_tiling(struct drm_device *dev, void *data, |
963 | int i915_gem_get_tiling(struct drm_device *dev, void *data, |
964 | struct drm_file *file_priv); |
964 | struct drm_file *file_priv); |
965 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
965 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
966 | struct drm_file *file_priv); |
966 | struct drm_file *file_priv); |
967 | void i915_gem_load(struct drm_device *dev); |
967 | void i915_gem_load(struct drm_device *dev); |
968 | int i915_gem_init_object(struct drm_gem_object *obj); |
968 | int i915_gem_init_object(struct drm_gem_object *obj); |
969 | int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, |
969 | int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, |
970 | uint32_t invalidate_domains, |
970 | uint32_t invalidate_domains, |
971 | uint32_t flush_domains); |
971 | uint32_t flush_domains); |
972 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
972 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
973 | size_t size); |
973 | size_t size); |
974 | void i915_gem_free_object(struct drm_gem_object *obj); |
974 | void i915_gem_free_object(struct drm_gem_object *obj); |
975 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
975 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
976 | uint32_t alignment, |
976 | uint32_t alignment, |
977 | bool map_and_fenceable); |
977 | bool map_and_fenceable); |
978 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
978 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
979 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
979 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
980 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
980 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
981 | void i915_gem_lastclose(struct drm_device *dev); |
981 | void i915_gem_lastclose(struct drm_device *dev); |
982 | 982 | ||
983 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
983 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
984 | int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); |
984 | int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); |
985 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
985 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
986 | struct intel_ring_buffer *ring, |
986 | struct intel_ring_buffer *ring, |
987 | u32 seqno); |
987 | u32 seqno); |
988 | 988 | ||
989 | int i915_gem_dumb_create(struct drm_file *file_priv, |
989 | int i915_gem_dumb_create(struct drm_file *file_priv, |
990 | struct drm_device *dev, |
990 | struct drm_device *dev, |
991 | struct drm_mode_create_dumb *args); |
991 | struct drm_mode_create_dumb *args); |
992 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
992 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
993 | uint32_t handle, uint64_t *offset); |
993 | uint32_t handle, uint64_t *offset); |
994 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, |
994 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, |
995 | uint32_t handle); |
995 | uint32_t handle); |
996 | /** |
996 | /** |
997 | * Returns true if seq1 is later than seq2. |
997 | * Returns true if seq1 is later than seq2. |
998 | */ |
998 | */ |
999 | //static inline bool |
999 | //static inline bool |
1000 | //i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
1000 | //i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
1001 | //{ |
1001 | //{ |
1002 | // return (int32_t)(seq1 - seq2) >= 0; |
1002 | // return (int32_t)(seq1 - seq2) >= 0; |
1003 | //} |
1003 | //} |
1004 | 1004 | ||
1005 | //static inline u32 |
1005 | //static inline u32 |
1006 | //i915_gem_next_request_seqno(struct intel_ring_buffer *ring) |
1006 | //i915_gem_next_request_seqno(struct intel_ring_buffer *ring) |
1007 | //{ |
1007 | //{ |
1008 | // drm_i915_private_t *dev_priv = ring->dev->dev_private; |
1008 | // drm_i915_private_t *dev_priv = ring->dev->dev_private; |
1009 | // return ring->outstanding_lazy_request = dev_priv->next_seqno; |
1009 | // return ring->outstanding_lazy_request = dev_priv->next_seqno; |
1010 | //} |
1010 | //} |
1011 | 1011 | ||
1012 | /* |
1012 | /* |
1013 | void i915_gem_retire_requests(struct drm_device *dev); |
1013 | void i915_gem_retire_requests(struct drm_device *dev); |
1014 | void i915_gem_reset(struct drm_device *dev); |
1014 | void i915_gem_reset(struct drm_device *dev); |
1015 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
1015 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
1016 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
1016 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
1017 | uint32_t read_domains, |
1017 | uint32_t read_domains, |
1018 | uint32_t write_domain); |
1018 | uint32_t write_domain); |
1019 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1019 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1020 | int __must_check i915_gem_init_ringbuffer(struct drm_device *dev); |
1020 | int __must_check i915_gem_init_ringbuffer(struct drm_device *dev); |
1021 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
1021 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
1022 | void i915_gem_do_init(struct drm_device *dev, |
1022 | void i915_gem_do_init(struct drm_device *dev, |
1023 | unsigned long start, |
1023 | unsigned long start, |
1024 | unsigned long mappable_end, |
1024 | unsigned long mappable_end, |
1025 | unsigned long end); |
1025 | unsigned long end); |
1026 | int __must_check i915_gpu_idle(struct drm_device *dev); |
1026 | int __must_check i915_gpu_idle(struct drm_device *dev); |
1027 | int __must_check i915_gem_idle(struct drm_device *dev); |
1027 | int __must_check i915_gem_idle(struct drm_device *dev); |
1028 | int __must_check i915_add_request(struct intel_ring_buffer *ring, |
1028 | int __must_check i915_add_request(struct intel_ring_buffer *ring, |
1029 | struct drm_file *file, |
1029 | struct drm_file *file, |
1030 | struct drm_i915_gem_request *request); |
1030 | struct drm_i915_gem_request *request); |
1031 | int __must_check i915_wait_request(struct intel_ring_buffer *ring, |
1031 | int __must_check i915_wait_request(struct intel_ring_buffer *ring, |
1032 | uint32_t seqno); |
1032 | uint32_t seqno); |
1033 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
1033 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
1034 | int __must_check |
1034 | int __must_check |
1035 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
1035 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
1036 | bool write); |
1036 | bool write); |
1037 | int __must_check |
1037 | int __must_check |
1038 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1038 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1039 | u32 alignment, |
1039 | u32 alignment, |
1040 | struct intel_ring_buffer *pipelined); |
1040 | struct intel_ring_buffer *pipelined); |
1041 | int i915_gem_attach_phys_object(struct drm_device *dev, |
1041 | int i915_gem_attach_phys_object(struct drm_device *dev, |
1042 | struct drm_i915_gem_object *obj, |
1042 | struct drm_i915_gem_object *obj, |
1043 | int id, |
1043 | int id, |
1044 | int align); |
1044 | int align); |
1045 | void i915_gem_detach_phys_object(struct drm_device *dev, |
1045 | void i915_gem_detach_phys_object(struct drm_device *dev, |
1046 | struct drm_i915_gem_object *obj); |
1046 | struct drm_i915_gem_object *obj); |
1047 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
1047 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
1048 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
1048 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
1049 | 1049 | ||
1050 | uint32_t |
1050 | uint32_t |
1051 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1051 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1052 | uint32_t size, |
1052 | uint32_t size, |
1053 | int tiling_mode); |
1053 | int tiling_mode); |
1054 | 1054 | ||
1055 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
1055 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
1056 | enum i915_cache_level cache_level); |
1056 | enum i915_cache_level cache_level); |
1057 | */ |
1057 | */ |
1058 | 1058 | ||
1059 | /* i915_gem_gtt.c */ |
1059 | /* i915_gem_gtt.c */ |
1060 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
1060 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
1061 | int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); |
1061 | int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); |
1062 | void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, |
1062 | void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, |
1063 | enum i915_cache_level cache_level); |
1063 | enum i915_cache_level cache_level); |
1064 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
1064 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
1065 | 1065 | ||
1066 | /* i915_gem_evict.c */ |
1066 | /* i915_gem_evict.c */ |
1067 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
1067 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
1068 | unsigned alignment, bool mappable); |
1068 | unsigned alignment, bool mappable); |
1069 | int __must_check i915_gem_evict_everything(struct drm_device *dev, |
1069 | int __must_check i915_gem_evict_everything(struct drm_device *dev, |
1070 | bool purgeable_only); |
1070 | bool purgeable_only); |
1071 | int __must_check i915_gem_evict_inactive(struct drm_device *dev, |
1071 | int __must_check i915_gem_evict_inactive(struct drm_device *dev, |
1072 | bool purgeable_only); |
1072 | bool purgeable_only); |
1073 | 1073 | ||
1074 | /* i915_gem_tiling.c */ |
1074 | /* i915_gem_tiling.c */ |
1075 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
1075 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
1076 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1076 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1077 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1077 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1078 | 1078 | ||
1079 | /* i915_gem_debug.c */ |
1079 | /* i915_gem_debug.c */ |
1080 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
1080 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
1081 | const char *where, uint32_t mark); |
1081 | const char *where, uint32_t mark); |
1082 | #if WATCH_LISTS |
1082 | #if WATCH_LISTS |
1083 | int i915_verify_lists(struct drm_device *dev); |
1083 | int i915_verify_lists(struct drm_device *dev); |
1084 | #else |
1084 | #else |
1085 | #define i915_verify_lists(dev) 0 |
1085 | #define i915_verify_lists(dev) 0 |
1086 | #endif |
1086 | #endif |
1087 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
1087 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
1088 | int handle); |
1088 | int handle); |
1089 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
1089 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
1090 | const char *where, uint32_t mark); |
1090 | const char *where, uint32_t mark); |
1091 | 1091 | ||
1092 | /* i915_debugfs.c */ |
1092 | /* i915_debugfs.c */ |
1093 | int i915_debugfs_init(struct drm_minor *minor); |
1093 | int i915_debugfs_init(struct drm_minor *minor); |
1094 | void i915_debugfs_cleanup(struct drm_minor *minor); |
1094 | void i915_debugfs_cleanup(struct drm_minor *minor); |
1095 | 1095 | ||
1096 | /* i915_suspend.c */ |
1096 | /* i915_suspend.c */ |
1097 | extern int i915_save_state(struct drm_device *dev); |
1097 | extern int i915_save_state(struct drm_device *dev); |
1098 | extern int i915_restore_state(struct drm_device *dev); |
1098 | extern int i915_restore_state(struct drm_device *dev); |
1099 | 1099 | ||
1100 | /* i915_suspend.c */ |
1100 | /* i915_suspend.c */ |
1101 | extern int i915_save_state(struct drm_device *dev); |
1101 | extern int i915_save_state(struct drm_device *dev); |
1102 | extern int i915_restore_state(struct drm_device *dev); |
1102 | extern int i915_restore_state(struct drm_device *dev); |
1103 | 1103 | ||
1104 | /* intel_i2c.c */ |
1104 | /* intel_i2c.c */ |
1105 | extern int intel_setup_gmbus(struct drm_device *dev); |
1105 | extern int intel_setup_gmbus(struct drm_device *dev); |
1106 | extern void intel_teardown_gmbus(struct drm_device *dev); |
1106 | extern void intel_teardown_gmbus(struct drm_device *dev); |
1107 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1107 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1108 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); |
1108 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); |
1109 | 1109 | ||
1110 | //extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1110 | //extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1111 | //{ |
1111 | //{ |
1112 | // return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
1112 | // return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
1113 | //} |
1113 | //} |
1114 | 1114 | ||
1115 | extern void intel_i2c_reset(struct drm_device *dev); |
1115 | extern void intel_i2c_reset(struct drm_device *dev); |
1116 | 1116 | ||
1117 | /* intel_opregion.c */ |
1117 | /* intel_opregion.c */ |
1118 | extern int intel_opregion_setup(struct drm_device *dev); |
1118 | extern int intel_opregion_setup(struct drm_device *dev); |
1119 | #ifdef CONFIG_ACPI |
1119 | #ifdef CONFIG_ACPI |
1120 | extern void intel_opregion_init(struct drm_device *dev); |
1120 | extern void intel_opregion_init(struct drm_device *dev); |
1121 | extern void intel_opregion_fini(struct drm_device *dev); |
1121 | extern void intel_opregion_fini(struct drm_device *dev); |
1122 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1122 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1123 | extern void intel_opregion_gse_intr(struct drm_device *dev); |
1123 | extern void intel_opregion_gse_intr(struct drm_device *dev); |
1124 | extern void intel_opregion_enable_asle(struct drm_device *dev); |
1124 | extern void intel_opregion_enable_asle(struct drm_device *dev); |
1125 | #else |
1125 | #else |
1126 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1126 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1127 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } |
1127 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } |
1128 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1128 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1129 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } |
1129 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } |
1130 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } |
1130 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } |
1131 | #endif |
1131 | #endif |
1132 | 1132 | ||
1133 | /* intel_acpi.c */ |
1133 | /* intel_acpi.c */ |
1134 | #ifdef CONFIG_ACPI |
1134 | #ifdef CONFIG_ACPI |
1135 | extern void intel_register_dsm_handler(void); |
1135 | extern void intel_register_dsm_handler(void); |
1136 | extern void intel_unregister_dsm_handler(void); |
1136 | extern void intel_unregister_dsm_handler(void); |
1137 | #else |
1137 | #else |
1138 | static inline void intel_register_dsm_handler(void) { return; } |
1138 | static inline void intel_register_dsm_handler(void) { return; } |
1139 | static inline void intel_unregister_dsm_handler(void) { return; } |
1139 | static inline void intel_unregister_dsm_handler(void) { return; } |
1140 | #endif /* CONFIG_ACPI */ |
1140 | #endif /* CONFIG_ACPI */ |
1141 | 1141 | ||
1142 | /* modesetting */ |
1142 | /* modesetting */ |
1143 | extern void intel_modeset_init(struct drm_device *dev); |
1143 | extern void intel_modeset_init(struct drm_device *dev); |
1144 | extern void intel_modeset_gem_init(struct drm_device *dev); |
1144 | extern void intel_modeset_gem_init(struct drm_device *dev); |
1145 | extern void intel_modeset_cleanup(struct drm_device *dev); |
1145 | extern void intel_modeset_cleanup(struct drm_device *dev); |
1146 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
1146 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
1147 | extern bool intel_fbc_enabled(struct drm_device *dev); |
1147 | extern bool intel_fbc_enabled(struct drm_device *dev); |
1148 | extern void intel_disable_fbc(struct drm_device *dev); |
1148 | extern void intel_disable_fbc(struct drm_device *dev); |
1149 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
1149 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
1150 | extern void ironlake_enable_rc6(struct drm_device *dev); |
1150 | extern void ironlake_enable_rc6(struct drm_device *dev); |
1151 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
1151 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
1152 | extern void intel_detect_pch (struct drm_device *dev); |
1152 | extern void intel_detect_pch (struct drm_device *dev); |
1153 | extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); |
1153 | extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); |
1154 | 1154 | ||
1155 | /* overlay */ |
1155 | /* overlay */ |
1156 | #ifdef CONFIG_DEBUG_FS |
1156 | #ifdef CONFIG_DEBUG_FS |
1157 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1157 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1158 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); |
1158 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); |
1159 | 1159 | ||
1160 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); |
1160 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); |
1161 | extern void intel_display_print_error_state(struct seq_file *m, |
1161 | extern void intel_display_print_error_state(struct seq_file *m, |
1162 | struct drm_device *dev, |
1162 | struct drm_device *dev, |
1163 | struct intel_display_error_state *error); |
1163 | struct intel_display_error_state *error); |
1164 | #endif |
1164 | #endif |
1165 | 1165 | ||
1166 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
1166 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
1167 | 1167 | ||
1168 | #define BEGIN_LP_RING(n) \ |
1168 | #define BEGIN_LP_RING(n) \ |
1169 | intel_ring_begin(LP_RING(dev_priv), (n)) |
1169 | intel_ring_begin(LP_RING(dev_priv), (n)) |
1170 | 1170 | ||
1171 | #define OUT_RING(x) \ |
1171 | #define OUT_RING(x) \ |
1172 | intel_ring_emit(LP_RING(dev_priv), x) |
1172 | intel_ring_emit(LP_RING(dev_priv), x) |
1173 | 1173 | ||
1174 | #define ADVANCE_LP_RING() \ |
1174 | #define ADVANCE_LP_RING() \ |
1175 | intel_ring_advance(LP_RING(dev_priv)) |
1175 | intel_ring_advance(LP_RING(dev_priv)) |
1176 | 1176 | ||
1177 | /** |
1177 | /** |
1178 | * Lock test for when it's just for synchronization of ring access. |
1178 | * Lock test for when it's just for synchronization of ring access. |
1179 | * |
1179 | * |
1180 | * In that case, we don't need to do it when GEM is initialized as nobody else |
1180 | * In that case, we don't need to do it when GEM is initialized as nobody else |
1181 | * has access to the ring. |
1181 | * has access to the ring. |
1182 | */ |
1182 | */ |
1183 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ |
1183 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ |
1184 | if (LP_RING(dev->dev_private)->obj == NULL) \ |
1184 | if (LP_RING(dev->dev_private)->obj == NULL) \ |
1185 | LOCK_TEST_WITH_RETURN(dev, file); \ |
1185 | LOCK_TEST_WITH_RETURN(dev, file); \ |
1186 | } while (0) |
1186 | } while (0) |
1187 | 1187 | ||
1188 | /* On SNB platform, before reading ring registers forcewake bit |
1188 | /* On SNB platform, before reading ring registers forcewake bit |
1189 | * must be set to prevent GT core from power down and stale values being |
1189 | * must be set to prevent GT core from power down and stale values being |
1190 | * returned. |
1190 | * returned. |
1191 | */ |
1191 | */ |
1192 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1192 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1193 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); |
1193 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); |
1194 | void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
1194 | void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
1195 | 1195 | ||
1196 | /* We give fast paths for the really cool registers */ |
1196 | /* We give fast paths for the really cool registers */ |
1197 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
1197 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
1198 | (((dev_priv)->info->gen >= 6) && \ |
1198 | (((dev_priv)->info->gen >= 6) && \ |
1199 | ((reg) < 0x40000) && \ |
1199 | ((reg) < 0x40000) && \ |
1200 | ((reg) != FORCEWAKE)) |
1200 | ((reg) != FORCEWAKE)) |
1201 | 1201 | ||
1202 | #define __i915_read(x, y) \ |
1202 | #define __i915_read(x, y) \ |
1203 | static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
1203 | static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
1204 | u##x val = 0; \ |
1204 | u##x val = 0; \ |
1205 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
1205 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
1206 | gen6_gt_force_wake_get(dev_priv); \ |
1206 | gen6_gt_force_wake_get(dev_priv); \ |
1207 | val = read##y(dev_priv->regs + reg); \ |
1207 | val = read##y(dev_priv->regs + reg); \ |
1208 | gen6_gt_force_wake_put(dev_priv); \ |
1208 | gen6_gt_force_wake_put(dev_priv); \ |
1209 | } else { \ |
1209 | } else { \ |
1210 | val = read##y(dev_priv->regs + reg); \ |
1210 | val = read##y(dev_priv->regs + reg); \ |
1211 | } \ |
1211 | } \ |
1212 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ |
1212 | /* trace_i915_reg_rw(false, reg, val, sizeof(val)); */\ |
1213 | return val; \ |
1213 | return val; \ |
1214 | } |
1214 | } |
1215 | 1215 | ||
1216 | __i915_read(8, b) |
1216 | __i915_read(8, b) |
1217 | __i915_read(16, w) |
1217 | __i915_read(16, w) |
1218 | __i915_read(32, l) |
1218 | __i915_read(32, l) |
1219 | __i915_read(64, q) |
1219 | __i915_read(64, q) |
1220 | #undef __i915_read |
1220 | #undef __i915_read |
1221 | 1221 | ||
1222 | #define __i915_write(x, y) \ |
1222 | #define __i915_write(x, y) \ |
1223 | static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ |
1223 | static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ |
1224 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
1224 | /* trace_i915_reg_rw(true, reg, val, sizeof(val));*/ \ |
1225 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
1225 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
1226 | __gen6_gt_wait_for_fifo(dev_priv); \ |
1226 | __gen6_gt_wait_for_fifo(dev_priv); \ |
1227 | } \ |
1227 | } \ |
1228 | write##y(val, dev_priv->regs + reg); \ |
1228 | write##y(val, dev_priv->regs + reg); \ |
1229 | } |
1229 | } |
1230 | __i915_write(8, b) |
1230 | __i915_write(8, b) |
1231 | __i915_write(16, w) |
1231 | __i915_write(16, w) |
1232 | __i915_write(32, l) |
1232 | __i915_write(32, l) |
1233 | __i915_write(64, q) |
1233 | __i915_write(64, q) |
1234 | #undef __i915_write |
1234 | #undef __i915_write |
1235 | 1235 | ||
1236 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) |
1236 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) |
1237 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) |
1237 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) |
1238 | 1238 | ||
1239 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) |
1239 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) |
1240 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) |
1240 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) |
1241 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) |
1241 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) |
1242 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) |
1242 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) |
1243 | 1243 | ||
1244 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) |
1244 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) |
1245 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) |
1245 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) |
1246 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1246 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1247 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) |
1247 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) |
1248 | 1248 | ||
1249 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) |
1249 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) |
1250 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) |
1250 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) |
1251 | 1251 | ||
1252 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
1252 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
1253 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
1253 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
1254 | 1254 | ||
1255 | 1255 | ||
1256 | #endif>1) |
1256 | #endif>1) |
1257 | 1257 | ||
1258 | struct><1) |
1258 | struct><1) |
1259 | 1259 | ||
1260 | struct>0) |
1260 | struct>0) |
1261 | #define><0) |
1261 | #define><0) |
1262 | #define>> |
1262 | #define>> |