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| 30 | #ifndef _I915_DRV_H_ |
30 | #ifndef _I915_DRV_H_ |
| 31 | #define _I915_DRV_H_ |
31 | #define _I915_DRV_H_ |
| Line 32... | Line 32... | ||
| 32 | 32 | ||
| 33 | #include "i915_reg.h" |
33 | #include "i915_reg.h" |
| 34 | //#include "intel_bios.h" |
34 | //#include "intel_bios.h" |
| 35 | //#include "intel_ringbuffer.h" |
35 | #include "intel_ringbuffer.h" |
| 36 | //#include |
36 | //#include |
| 37 | //#include |
37 | //#include |
| 38 | //#include |
38 | //#include |
| Line 272... | Line 272... | ||
| 272 | int relative_constants_mode; |
272 | int relative_constants_mode; |
| Line 273... | Line 273... | ||
| 273 | 273 | ||
| 274 | void __iomem *regs; |
274 | void __iomem *regs; |
| Line 275... | Line 275... | ||
| 275 | u32 gt_fifo_count; |
275 | u32 gt_fifo_count; |
| 276 | 276 | ||
| 277 | // struct intel_gmbus { |
277 | struct intel_gmbus { |
| 278 | // struct i2c_adapter adapter; |
278 | struct i2c_adapter adapter; |
| 279 | // struct i2c_adapter *force_bit; |
279 | struct i2c_adapter *force_bit; |
| Line 280... | Line 280... | ||
| 280 | // u32 reg0; |
280 | u32 reg0; |
| 281 | // } *gmbus; |
281 | } *gmbus; |
| 282 | 282 | ||
| Line 283... | Line 283... | ||
| 283 | struct pci_dev *bridge_dev; |
283 | struct pci_dev *bridge_dev; |
| 284 | // struct intel_ring_buffer ring[I915_NUM_RINGS]; |
284 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
| 285 | uint32_t next_seqno; |
285 | uint32_t next_seqno; |
| 286 | 286 | ||
| 287 | // drm_dma_handle_t *status_page_dmah; |
287 | drm_dma_handle_t *status_page_dmah; |
| Line 365... | Line 365... | ||
| 365 | bool no_aux_handshake; |
365 | bool no_aux_handshake; |
| Line 366... | Line 366... | ||
| 366 | 366 | ||
| Line 367... | Line 367... | ||
| 367 | // struct notifier_block lid_notifier; |
367 | // struct notifier_block lid_notifier; |
| 368 | 368 | ||
| 369 | int crt_ddc_pin; |
369 | int crt_ddc_pin; |
| 370 | // struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
370 | struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
| Line 371... | Line 371... | ||
| 371 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
371 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
| Line 665... | Line 665... | ||
| 665 | unsigned int lvds_border_bits; |
665 | unsigned int lvds_border_bits; |
| 666 | /* Panel fitter placement and size for Ironlake+ */ |
666 | /* Panel fitter placement and size for Ironlake+ */ |
| 667 | u32 pch_pf_pos, pch_pf_size; |
667 | u32 pch_pf_pos, pch_pf_size; |
| 668 | int panel_t3, panel_t12; |
668 | int panel_t3, panel_t12; |
| Line 669... | Line 669... | ||
| 669 | 669 | ||
| 670 | // struct drm_crtc *plane_to_crtc_mapping[2]; |
670 | struct drm_crtc *plane_to_crtc_mapping[2]; |
| 671 | // struct drm_crtc *pipe_to_crtc_mapping[2]; |
671 | struct drm_crtc *pipe_to_crtc_mapping[2]; |
| 672 | // wait_queue_head_t pending_flip_queue; |
672 | // wait_queue_head_t pending_flip_queue; |
| Line 673... | Line 673... | ||
| 673 | bool flip_pending_is_done; |
673 | bool flip_pending_is_done; |
| 674 | 674 | ||
| Line 1207... | Line 1207... | ||
| 1207 | val = read##y(dev_priv->regs + reg); \ |
1207 | val = read##y(dev_priv->regs + reg); \ |
| 1208 | gen6_gt_force_wake_put(dev_priv); \ |
1208 | gen6_gt_force_wake_put(dev_priv); \ |
| 1209 | } else { \ |
1209 | } else { \ |
| 1210 | val = read##y(dev_priv->regs + reg); \ |
1210 | val = read##y(dev_priv->regs + reg); \ |
| 1211 | } \ |
1211 | } \ |
| 1212 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ |
1212 | /* trace_i915_reg_rw(false, reg, val, sizeof(val)); */\ |
| 1213 | return val; \ |
1213 | return val; \ |
| 1214 | } |
1214 | } |
| Line 1215... | Line 1215... | ||
| 1215 | 1215 | ||
| 1216 | __i915_read(8, b) |
1216 | __i915_read(8, b) |
| Line 1219... | Line 1219... | ||
| 1219 | __i915_read(64, q) |
1219 | __i915_read(64, q) |
| 1220 | #undef __i915_read |
1220 | #undef __i915_read |
| Line 1221... | Line 1221... | ||
| 1221 | 1221 | ||
| 1222 | #define __i915_write(x, y) \ |
1222 | #define __i915_write(x, y) \ |
| 1223 | static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ |
1223 | static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ |
| 1224 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
1224 | /* trace_i915_reg_rw(true, reg, val, sizeof(val));*/ \ |
| 1225 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
1225 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 1226 | __gen6_gt_wait_for_fifo(dev_priv); \ |
1226 | __gen6_gt_wait_for_fifo(dev_priv); \ |
| 1227 | } \ |
1227 | } \ |
| 1228 | write##y(val, dev_priv->regs + reg); \ |
1228 | write##y(val, dev_priv->regs + reg); \ |