WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_drv.c


/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
 */
/*
 *
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */
 
#include 
#include 
#include 
#include 
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"
 
#include 
#include 
#include 
#include 
#include 
 
#include 
 
int init_display_kms(struct drm_device *dev);
 
extern int intel_agp_enabled;
 
static struct drm_driver driver;
 
#define GEN_DEFAULT_PIPEOFFSETS \
	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
			  PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
 
#define GEN_CHV_PIPEOFFSETS \
	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
			  CHV_PIPE_C_OFFSET }, \
	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
			   CHV_TRANSCODER_C_OFFSET, }, \
	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
			     CHV_PALETTE_C_OFFSET }
 
#define CURSOR_OFFSETS \
	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
 
#define IVB_CURSOR_OFFSETS \
	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
 
 
 
 
static const struct intel_device_info intel_i915g_info = {
	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.ring_mask = RENDER_RING,
	GEN_DEFAULT_PIPEOFFSETS,
	CURSOR_OFFSETS,
};
static const struct intel_device_info intel_i915gm_info = {
	.gen = 3, .is_mobile = 1, .num_pipes = 2,
	.cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.supports_tv = 1,
	.has_fbc = 1,
	.ring_mask = RENDER_RING,
	GEN_DEFAULT_PIPEOFFSETS,
	CURSOR_OFFSETS,
};
static const struct intel_device_info intel_i945g_info = {
	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.ring_mask = RENDER_RING,
	GEN_DEFAULT_PIPEOFFSETS,
	CURSOR_OFFSETS,
};
static const struct intel_device_info intel_i945gm_info = {
	.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
	.has_hotplug = 1, .cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.supports_tv = 1,
	.has_fbc = 1,
	.ring_mask = RENDER_RING,
	GEN_DEFAULT_PIPEOFFSETS,
	CURSOR_OFFSETS,
};
 
static const struct intel_device_info intel_i965g_info = {
	.gen = 4, .is_broadwater = 1, .num_pipes = 2,
	.has_hotplug = 1,
	.has_overlay = 1,
	.ring_mask = RENDER_RING,
	GEN_DEFAULT_PIPEOFFSETS,
	CURSOR_OFFSETS,
};
 
static const struct intel_device_info intel_i965gm_info = {
	.gen = 4, .is_crestline = 1, .num_pipes = 2,
	.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
	.has_overlay = 1,
	.supports_tv = 1,
	.ring_mask = RENDER_RING,
	GEN_DEFAULT_PIPEOFFSETS,
	CURSOR_OFFSETS,
};
 
static const struct intel_device_info intel_g33_info = {
	.gen = 3, .is_g33 = 1, .num_pipes = 2,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.has_overlay = 1,
	.ring_mask = RENDER_RING,
	GEN_DEFAULT_PIPEOFFSETS,
	CURSOR_OFFSETS,
};
 
static const struct intel_device_info intel_g45_info = {
	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
	.has_pipe_cxsr = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING,
	GEN_DEFAULT_PIPEOFFSETS,
	CURSOR_OFFSETS,
};
 
static const struct intel_device_info intel_gm45_info = {
	.gen = 4, .is_g4x = 1, .num_pipes = 2,
	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
	.has_pipe_cxsr = 1, .has_hotplug = 1,
	.supports_tv = 1,
	.ring_mask = RENDER_RING | BSD_RING,
	GEN_DEFAULT_PIPEOFFSETS,
	CURSOR_OFFSETS,
};
 
static const struct intel_device_info intel_pineview_info = {
	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.has_overlay = 1,
	GEN_DEFAULT_PIPEOFFSETS,
	CURSOR_OFFSETS,
};
 
static const struct intel_device_info intel_ironlake_d_info = {
	.gen = 5, .num_pipes = 2,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING,
	GEN_DEFAULT_PIPEOFFSETS,
	CURSOR_OFFSETS,
};
 
static const struct intel_device_info intel_ironlake_m_info = {
	.gen = 5, .is_mobile = 1, .num_pipes = 2,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.has_fbc = 1,
	.ring_mask = RENDER_RING | BSD_RING,
	GEN_DEFAULT_PIPEOFFSETS,
	CURSOR_OFFSETS,
};
 
static const struct intel_device_info intel_sandybridge_d_info = {
	.gen = 6, .num_pipes = 2,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.has_fbc = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
	.has_llc = 1,
	GEN_DEFAULT_PIPEOFFSETS,
	CURSOR_OFFSETS,
};
 
static const struct intel_device_info intel_sandybridge_m_info = {
	.gen = 6, .is_mobile = 1, .num_pipes = 2,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.has_fbc = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
	.has_llc = 1,
	GEN_DEFAULT_PIPEOFFSETS,
	CURSOR_OFFSETS,
};
 
#define GEN7_FEATURES  \
	.gen = 7, .num_pipes = 3, \
	.need_gfx_hws = 1, .has_hotplug = 1, \
	.has_fbc = 1, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
	.has_llc = 1, \
	GEN_DEFAULT_PIPEOFFSETS, \
	IVB_CURSOR_OFFSETS
 
static const struct intel_device_info intel_ivybridge_d_info = {
	GEN7_FEATURES,
	.is_ivybridge = 1,
};
 
static const struct intel_device_info intel_ivybridge_m_info = {
	GEN7_FEATURES,
	.is_ivybridge = 1,
	.is_mobile = 1,
};
 
static const struct intel_device_info intel_ivybridge_q_info = {
	GEN7_FEATURES,
	.is_ivybridge = 1,
	.num_pipes = 0, /* legal, last one wins */
};
 
#define VLV_FEATURES  \
	.gen = 7, .num_pipes = 2, \
	.need_gfx_hws = 1, .has_hotplug = 1, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
	.display_mmio_offset = VLV_DISPLAY_BASE, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS
 
static const struct intel_device_info intel_valleyview_m_info = {
	VLV_FEATURES,
	.is_valleyview = 1,
	.is_mobile = 1,
};
 
static const struct intel_device_info intel_valleyview_d_info = {
	VLV_FEATURES,
	.is_valleyview = 1,
};
 
#define HSW_FEATURES  \
	GEN7_FEATURES, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
	.has_ddi = 1, \
	.has_fpga_dbg = 1
 
static const struct intel_device_info intel_haswell_d_info = {
	HSW_FEATURES,
	.is_haswell = 1,
};
 
static const struct intel_device_info intel_haswell_m_info = {
	HSW_FEATURES,
	.is_haswell = 1,
	.is_mobile = 1,
};
 
static const struct intel_device_info intel_broadwell_d_info = {
	HSW_FEATURES,
	.gen = 8,
};
 
static const struct intel_device_info intel_broadwell_m_info = {
	HSW_FEATURES,
	.gen = 8, .is_mobile = 1,
};
 
static const struct intel_device_info intel_broadwell_gt3d_info = {
	HSW_FEATURES,
	.gen = 8,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
 
static const struct intel_device_info intel_broadwell_gt3m_info = {
	HSW_FEATURES,
	.gen = 8, .is_mobile = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
 
static const struct intel_device_info intel_cherryview_info = {
	.gen = 8, .num_pipes = 3,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.is_cherryview = 1,
	.display_mmio_offset = VLV_DISPLAY_BASE,
	GEN_CHV_PIPEOFFSETS,
	CURSOR_OFFSETS,
};
 
static const struct intel_device_info intel_skylake_info = {
	HSW_FEATURES,
	.is_skylake = 1,
	.gen = 9,
};
 
static const struct intel_device_info intel_skylake_gt3_info = {
	HSW_FEATURES,
	.is_skylake = 1,
	.gen = 9,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
 
static const struct intel_device_info intel_broxton_info = {
	.is_preliminary = 1,
	.is_broxton = 1,
	.gen = 9,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.num_pipes = 3,
	.has_ddi = 1,
	.has_fpga_dbg = 1,
	.has_fbc = 1,
	GEN_DEFAULT_PIPEOFFSETS,
	IVB_CURSOR_OFFSETS,
};
 
static const struct intel_device_info intel_kabylake_info = {
	HSW_FEATURES,
	.is_preliminary = 1,
	.is_kabylake = 1,
	.gen = 9,
};
 
static const struct intel_device_info intel_kabylake_gt3_info = {
	HSW_FEATURES,
	.is_preliminary = 1,
	.is_kabylake = 1,
	.gen = 9,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
 
/*
 * Make sure any device matches here are from most specific to most
 * general.  For example, since the Quanta match is based on the subsystem
 * and subvendor IDs, we need it to come before the more general IVB
 * PCI ID matches, otherwise we'll use the wrong info struct above.
 */
static const struct pci_device_id pciidlist[] = {
	INTEL_I915G_IDS(&intel_i915g_info),
	INTEL_I915GM_IDS(&intel_i915gm_info),
	INTEL_I945G_IDS(&intel_i945g_info),
	INTEL_I945GM_IDS(&intel_i945gm_info),
	INTEL_I965G_IDS(&intel_i965g_info),
	INTEL_G33_IDS(&intel_g33_info),
	INTEL_I965GM_IDS(&intel_i965gm_info),
	INTEL_GM45_IDS(&intel_gm45_info),
	INTEL_G45_IDS(&intel_g45_info),
	INTEL_PINEVIEW_IDS(&intel_pineview_info),
	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
	INTEL_HSW_D_IDS(&intel_haswell_d_info),
	INTEL_HSW_M_IDS(&intel_haswell_m_info),
	INTEL_VLV_M_IDS(&intel_valleyview_m_info),
	INTEL_VLV_D_IDS(&intel_valleyview_d_info),
	INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
	INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
	INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
	INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
	INTEL_CHV_IDS(&intel_cherryview_info),
	INTEL_SKL_GT1_IDS(&intel_skylake_info),
	INTEL_SKL_GT2_IDS(&intel_skylake_info),
	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
	INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
	INTEL_BXT_IDS(&intel_broxton_info),
	INTEL_KBL_GT1_IDS(&intel_kabylake_info),
	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
	{0, 0, 0}
};
 
 
 
static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
{
	enum intel_pch ret = PCH_NOP;
 
	/*
	 * In a virtualized passthrough environment we can be in a
	 * setup where the ISA bridge is not able to be passed through.
	 * In this case, a south bridge can be emulated and we have to
	 * make an educated guess as to which PCH is really there.
	 */
 
	if (IS_GEN5(dev)) {
		ret = PCH_IBX;
		DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
	} else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
		ret = PCH_CPT;
		DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
		ret = PCH_LPT;
		DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
	} else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
		ret = PCH_SPT;
		DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
	}
 
	return ret;
}
 
void intel_detect_pch(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct pci_dev *pch = NULL;
 
	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
	 * (which really amounts to a PCH but no South Display).
	 */
	if (INTEL_INFO(dev)->num_pipes == 0) {
		dev_priv->pch_type = PCH_NOP;
		return;
	}
 
	/*
	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
	 * make graphics device passthrough work easy for VMM, that only
	 * need to expose ISA bridge to let driver know the real hardware
	 * underneath. This is a requirement from virtualization team.
	 *
	 * In some virtualized environments (e.g. XEN), there is irrelevant
	 * ISA bridge in the system. To work reliably, we should scan trhough
	 * all the ISA bridge devices and check for the first match, instead
	 * of only checking the first one.
	 */
	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
		if (pch->vendor == PCI_VENDOR_ID_INTEL) {
			unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
			dev_priv->pch_id = id;
 
			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_IBX;
				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
				WARN_ON(!IS_GEN5(dev));
			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_CPT;
				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
				/* PantherPoint is CPT compatible */
				dev_priv->pch_type = PCH_CPT;
				DRM_DEBUG_KMS("Found PantherPoint PCH\n");
				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
				WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
				WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
				WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
				WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
			} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_SPT;
				DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
				WARN_ON(!IS_SKYLAKE(dev) &&
					!IS_KABYLAKE(dev));
			} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_SPT;
				DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
				WARN_ON(!IS_SKYLAKE(dev) &&
					!IS_KABYLAKE(dev));
			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
				    pch->subsystem_vendor == 0x1af4 &&
				    pch->subsystem_device == 0x1100)) {
				dev_priv->pch_type = intel_virt_detect_pch(dev);
			} else
				continue;
 
			break;
		}
	}
	if (!pch)
		DRM_DEBUG_KMS("No PCH found.\n");
 
//	pci_dev_put(pch);
}
 
bool i915_semaphore_is_enabled(struct drm_device *dev)
{
	if (INTEL_INFO(dev)->gen < 6)
		return false;
 
	if (i915.semaphores >= 0)
		return i915.semaphores;
 
	/* TODO: make semaphores and Execlists play nicely together */
	if (i915.enable_execlists)
		return false;
 
	/* Until we get further testing... */
	if (IS_GEN8(dev))
		return false;
 
#ifdef CONFIG_INTEL_IOMMU
	/* Enable semaphores on SNB when IO remapping is off */
	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
		return false;
#endif
 
	return true;
}
 
#if 0
 
static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	struct intel_encoder *encoder;
 
	drm_modeset_lock_all(dev);
	for_each_intel_encoder(dev, encoder)
		if (encoder->suspend)
			encoder->suspend(encoder);
	drm_modeset_unlock_all(dev);
}
 
static int intel_suspend_complete(struct drm_i915_private *dev_priv);
static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
			      bool rpm_resume);
static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
 
static bool suspend_to_idle(struct drm_i915_private *dev_priv)
{
#if IS_ENABLED(CONFIG_ACPI_SLEEP)
	if (acpi_target_system_state() < ACPI_STATE_S3)
		return true;
#endif
	return false;
}
 
static int i915_drm_suspend(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	pci_power_t opregion_target_state;
	int error;
 
	/* ignore lid events during suspend */
	mutex_lock(&dev_priv->modeset_restore_lock);
	dev_priv->modeset_restore = MODESET_SUSPENDED;
	mutex_unlock(&dev_priv->modeset_restore_lock);
 
	disable_rpm_wakeref_asserts(dev_priv);
 
	/* We do a lot of poking in a lot of registers, make sure they work
	 * properly. */
	intel_display_set_init_power(dev_priv, true);
 
	drm_kms_helper_poll_disable(dev);
 
	pci_save_state(dev->pdev);
 
	error = i915_gem_suspend(dev);
	if (error) {
		dev_err(&dev->pdev->dev,
			"GEM idle failed, resume might fail\n");
		goto out;
	}
 
	intel_guc_suspend(dev);
 
	intel_suspend_gt_powersave(dev);
 
 
 
 
 
 
 
	intel_display_suspend(dev);
 
	intel_dp_mst_suspend(dev);
 
	intel_runtime_pm_disable_interrupts(dev_priv);
	intel_hpd_cancel_work(dev_priv);
 
	intel_suspend_encoders(dev_priv);
 
	intel_suspend_hw(dev);
 
	i915_gem_suspend_gtt_mappings(dev);
 
	i915_save_state(dev);
 
	opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
	intel_opregion_notify_adapter(dev, opregion_target_state);
 
	intel_uncore_forcewake_reset(dev, false);
	intel_opregion_fini(dev);
 
	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
 
	dev_priv->suspend_count++;
 
	intel_display_set_init_power(dev_priv, false);
 
	if (HAS_CSR(dev_priv))
		flush_work(&dev_priv->csr.work);
 
out:
	enable_rpm_wakeref_asserts(dev_priv);
 
	return error;
}
 
static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
{
	struct drm_i915_private *dev_priv = drm_dev->dev_private;
	bool fw_csr;
	int ret;
 
	disable_rpm_wakeref_asserts(dev_priv);
 
	fw_csr = suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
	/*
	 * In case of firmware assisted context save/restore don't manually
	 * deinit the power domains. This also means the CSR/DMC firmware will
	 * stay active, it will power down any HW resources as required and
	 * also enable deeper system power states that would be blocked if the
	 * firmware was inactive.
	 */
	if (!fw_csr)
		intel_power_domains_suspend(dev_priv);
 
	ret = intel_suspend_complete(dev_priv);
 
	if (ret) {
		DRM_ERROR("Suspend complete failed: %d\n", ret);
		if (!fw_csr)
			intel_power_domains_init_hw(dev_priv, true);
 
		goto out;
	}
 
	pci_disable_device(drm_dev->pdev);
	/*
	 * During hibernation on some platforms the BIOS may try to access
	 * the device even though it's already in D3 and hang the machine. So
	 * leave the device in D0 on those platforms and hope the BIOS will
	 * power down the device properly. The issue was seen on multiple old
	 * GENs with different BIOS vendors, so having an explicit blacklist
	 * is inpractical; apply the workaround on everything pre GEN6. The
	 * platforms where the issue was seen:
	 * Lenovo Thinkpad X301, X61s, X60, T60, X41
	 * Fujitsu FSC S7110
	 * Acer Aspire 1830T
	 */
	if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
		pci_set_power_state(drm_dev->pdev, PCI_D3hot);
 
	dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
 
out:
	enable_rpm_wakeref_asserts(dev_priv);
 
	return ret;
}
 
int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
{
	int error;
 
	if (!dev || !dev->dev_private) {
		DRM_ERROR("dev: %p\n", dev);
		DRM_ERROR("DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}
 
	if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
			 state.event != PM_EVENT_FREEZE))
		return -EINVAL;
 
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
 
	error = i915_drm_suspend(dev);
	if (error)
		return error;
 
	return i915_drm_suspend_late(dev, false);
}
 
static int i915_drm_resume(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
 
	disable_rpm_wakeref_asserts(dev_priv);
 
	mutex_lock(&dev->struct_mutex);
	i915_gem_restore_gtt_mappings(dev);
	mutex_unlock(&dev->struct_mutex);
 
	i915_restore_state(dev);
	intel_opregion_setup(dev);
 
	intel_init_pch_refclk(dev);
	drm_mode_config_reset(dev);
 
	/*
	 * Interrupts have to be enabled before any batches are run. If not the
	 * GPU will hang. i915_gem_init_hw() will initiate batches to
	 * update/restore the context.
	 *
	 * Modeset enabling in intel_modeset_init_hw() also needs working
	 * interrupts.
	 */
	intel_runtime_pm_enable_interrupts(dev_priv);
 
	mutex_lock(&dev->struct_mutex);
	if (i915_gem_init_hw(dev)) {
		DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
			atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
	}
	mutex_unlock(&dev->struct_mutex);
 
	intel_guc_resume(dev);
 
	intel_modeset_init_hw(dev);
 
	spin_lock_irq(&dev_priv->irq_lock);
	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
	spin_unlock_irq(&dev_priv->irq_lock);
 
 
 
 
 
	intel_dp_mst_resume(dev);
 
	intel_display_resume(dev);
 
	/*
	 * ... but also need to make sure that hotplug processing
	 * doesn't cause havoc. Like in the driver load code we don't
	 * bother with the tiny race here where we might loose hotplug
	 * notifications.
	 * */
	intel_hpd_init(dev_priv);
	/* Config may have changed between suspend and resume */
	drm_helper_hpd_irq_event(dev);
 
	intel_opregion_init(dev);
 
	intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 
	mutex_lock(&dev_priv->modeset_restore_lock);
	dev_priv->modeset_restore = MODESET_DONE;
	mutex_unlock(&dev_priv->modeset_restore_lock);
 
	intel_opregion_notify_adapter(dev, PCI_D0);
 
	drm_kms_helper_poll_enable(dev);
 
	enable_rpm_wakeref_asserts(dev_priv);
 
	return 0;
}
 
static int i915_drm_resume_early(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;
 
	/*
	 * We have a resume ordering issue with the snd-hda driver also
	 * requiring our device to be power up. Due to the lack of a
	 * parent/child relationship we currently solve this with an early
	 * resume hook.
	 *
	 * FIXME: This should be solved with a special hdmi sink device or
	 * similar so that power domains can be employed.
	 */
 
	/*
	 * Note that we need to set the power state explicitly, since we
	 * powered off the device during freeze and the PCI core won't power
	 * it back up for us during thaw. Powering off the device during
	 * freeze is not a hard requirement though, and during the
	 * suspend/resume phases the PCI core makes sure we get here with the
	 * device powered on. So in case we change our freeze logic and keep
	 * the device powered we can also remove the following set power state
	 * call.
	 */
	ret = pci_set_power_state(dev->pdev, PCI_D0);
	if (ret) {
		DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
		goto out;
	}
 
	/*
	 * Note that pci_enable_device() first enables any parent bridge
	 * device and only then sets the power state for this device. The
	 * bridge enabling is a nop though, since bridge devices are resumed
	 * first. The order of enabling power and enabling the device is
	 * imposed by the PCI core as described above, so here we preserve the
	 * same order for the freeze/thaw phases.
	 *
	 * TODO: eventually we should remove pci_disable_device() /
	 * pci_enable_enable_device() from suspend/resume. Due to how they
	 * depend on the device enable refcount we can't anyway depend on them
	 * disabling/enabling the device.
	 */
	if (pci_enable_device(dev->pdev)) {
		ret = -EIO;
		goto out;
	}
 
	pci_set_master(dev->pdev);
 
	disable_rpm_wakeref_asserts(dev_priv);
 
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
		ret = vlv_resume_prepare(dev_priv, false);
	if (ret)
		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
			  ret);
 
	intel_uncore_early_sanitize(dev, true);
 
	if (IS_BROXTON(dev))
		ret = bxt_resume_prepare(dev_priv);
	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
		hsw_disable_pc8(dev_priv);
 
	intel_uncore_sanitize(dev);
 
	if (!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
		intel_power_domains_init_hw(dev_priv, true);
 
out:
	dev_priv->suspended_to_idle = false;
 
	enable_rpm_wakeref_asserts(dev_priv);
 
	return ret;
}
 
int i915_resume_switcheroo(struct drm_device *dev)
{
	int ret;
 
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
 
	ret = i915_drm_resume_early(dev);
	if (ret)
		return ret;
 
	return i915_drm_resume(dev);
}
#endif
 
/**
 * i915_reset - reset chip after a hang
 * @dev: drm device to reset
 *
 * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 * reset or otherwise an error code.
 *
 * Procedure is fairly simple:
 *   - reset the chip using the reset reg
 *   - re-init context state
 *   - re-init hardware status page
 *   - re-init ring buffer
 *   - re-init interrupt state
 *   - re-init display
 */
int i915_reset(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	bool simulated;
	int ret;
 
	intel_reset_gt_powersave(dev);
 
	mutex_lock(&dev->struct_mutex);
 
	i915_gem_reset(dev);
 
	simulated = dev_priv->gpu_error.stop_rings != 0;
 
	ret = intel_gpu_reset(dev);
 
	/* Also reset the gpu hangman. */
	if (simulated) {
		DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
		dev_priv->gpu_error.stop_rings = 0;
		if (ret == -ENODEV) {
			DRM_INFO("Reset not implemented, but ignoring "
				 "error for simulated gpu hangs\n");
			ret = 0;
		}
	}
 
	if (i915_stop_ring_allow_warn(dev_priv))
		pr_notice("drm/i915: Resetting chip after gpu hang\n");
 
	if (ret) {
		DRM_ERROR("Failed to reset chip: %i\n", ret);
		mutex_unlock(&dev->struct_mutex);
		return ret;
	}
 
//	intel_overlay_reset(dev_priv);
 
	/* Ok, now get things going again... */
 
	/*
	 * Everything depends on having the GTT running, so we need to start
	 * there.  Fortunately we don't need to do this unless we reset the
	 * chip at a PCI level.
	 *
	 * Next we need to restore the context, but we don't use those
	 * yet either...
	 *
	 * Ring buffer needs to be re-initialized in the KMS case, or if X
	 * was running at the time of the reset (i.e. we weren't VT
	 * switched away).
	 */
 
	/* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
	dev_priv->gpu_error.reload_in_reset = true;
 
	ret = i915_gem_init_hw(dev);
 
	dev_priv->gpu_error.reload_in_reset = false;
 
	mutex_unlock(&dev->struct_mutex);
	if (ret) {
		DRM_ERROR("Failed hw init on reset %d\n", ret);
		return ret;
	}
 
	/*
	 * rps/rc6 re-init is necessary to restore state lost after the
	 * reset and the re-install of gt irqs. Skip for ironlake per
	 * previous concerns that it doesn't respond well to some forms
	 * of re-init after reset.
	 */
	if (INTEL_INFO(dev)->gen > 5)
		intel_enable_gt_powersave(dev);
 
	return 0;
}
 
#if 0
static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	struct intel_device_info *intel_info =
		(struct intel_device_info *) ent->driver_data;
 
	if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
		DRM_INFO("This hardware requires preliminary hardware support.\n"
			 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
		return -ENODEV;
	}
 
	/* Only bind to function 0 of the device. Early generations
	 * used function 1 as a placeholder for multi-head. This causes
	 * us confusion instead, especially on the systems where both
	 * functions have the same PCI-ID!
	 */
	if (PCI_FUNC(pdev->devfn))
		return -ENODEV;
 
	return drm_get_pci_dev(pdev, ent, &driver);
}
 
static void
i915_pci_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
 
	drm_put_dev(dev);
}
 
static int i915_pm_suspend(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);
 
	if (!drm_dev || !drm_dev->dev_private) {
		dev_err(dev, "DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}
 
	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
 
	return i915_drm_suspend(drm_dev);
}
 
static int i915_pm_suspend_late(struct device *dev)
{
	struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 
	/*
	 * We have a suspend ordering issue with the snd-hda driver also
	 * requiring our device to be power up. Due to the lack of a
	 * parent/child relationship we currently solve this with an late
	 * suspend hook.
	 *
	 * FIXME: This should be solved with a special hdmi sink device or
	 * similar so that power domains can be employed.
	 */
	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
 
	return i915_drm_suspend_late(drm_dev, false);
}
 
static int i915_pm_poweroff_late(struct device *dev)
{
	struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 
	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
 
	return i915_drm_suspend_late(drm_dev, true);
}
 
static int i915_pm_resume_early(struct device *dev)
{
	struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 
	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
 
	return i915_drm_resume_early(drm_dev);
}
 
static int i915_pm_resume(struct device *dev)
{
	struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 
	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
 
	return i915_drm_resume(drm_dev);
}
 
static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
{
	hsw_enable_pc8(dev_priv);
 
	return 0;
}
 
static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
 
	/* TODO: when DC5 support is added disable DC5 here. */
 
	broxton_ddi_phy_uninit(dev);
	broxton_uninit_cdclk(dev);
	bxt_enable_dc9(dev_priv);
 
	return 0;
}
 
static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
 
	/* TODO: when CSR FW support is added make sure the FW is loaded */
 
	bxt_disable_dc9(dev_priv);
 
	/*
	 * TODO: when DC5 support is added enable DC5 here if the CSR FW
	 * is available.
	 */
	broxton_init_cdclk(dev);
	broxton_ddi_phy_init(dev);
 
 
	return 0;
}
 
/*
 * Save all Gunit registers that may be lost after a D3 and a subsequent
 * S0i[R123] transition. The list of registers needing a save/restore is
 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
 * registers in the following way:
 * - Driver: saved/restored by the driver
 * - Punit : saved/restored by the Punit firmware
 * - No, w/o marking: no need to save/restore, since the register is R/O or
 *                    used internally by the HW in a way that doesn't depend
 *                    keeping the content across a suspend/resume.
 * - Debug : used for debugging
 *
 * We save/restore all registers marked with 'Driver', with the following
 * exceptions:
 * - Registers out of use, including also registers marked with 'Debug'.
 *   These have no effect on the driver's operation, so we don't save/restore
 *   them to reduce the overhead.
 * - Registers that are fully setup by an initialization function called from
 *   the resume path. For example many clock gating and RPS/RC6 registers.
 * - Registers that provide the right functionality with their reset defaults.
 *
 * TODO: Except for registers that based on the above 3 criteria can be safely
 * ignored, we save/restore all others, practically treating the HW context as
 * a black-box for the driver. Further investigation is needed to reduce the
 * saved/restored registers even further, by following the same 3 criteria.
 */
static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
{
	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
	int i;
 
	/* GAM 0x4000-0x4770 */
	s->wr_watermark		= I915_READ(GEN7_WR_WATERMARK);
	s->gfx_prio_ctrl	= I915_READ(GEN7_GFX_PRIO_CTRL);
	s->arb_mode		= I915_READ(ARB_MODE);
	s->gfx_pend_tlb0	= I915_READ(GEN7_GFX_PEND_TLB0);
	s->gfx_pend_tlb1	= I915_READ(GEN7_GFX_PEND_TLB1);
 
	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
 
	s->media_max_req_count	= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
	s->gfx_max_req_count	= I915_READ(GEN7_GFX_MAX_REQ_COUNT);
 
	s->render_hwsp		= I915_READ(RENDER_HWS_PGA_GEN7);
	s->ecochk		= I915_READ(GAM_ECOCHK);
	s->bsd_hwsp		= I915_READ(BSD_HWS_PGA_GEN7);
	s->blt_hwsp		= I915_READ(BLT_HWS_PGA_GEN7);
 
	s->tlb_rd_addr		= I915_READ(GEN7_TLB_RD_ADDR);
 
	/* MBC 0x9024-0x91D0, 0x8500 */
	s->g3dctl		= I915_READ(VLV_G3DCTL);
	s->gsckgctl		= I915_READ(VLV_GSCKGCTL);
	s->mbctl		= I915_READ(GEN6_MBCTL);
 
	/* GCP 0x9400-0x9424, 0x8100-0x810C */
	s->ucgctl1		= I915_READ(GEN6_UCGCTL1);
	s->ucgctl3		= I915_READ(GEN6_UCGCTL3);
	s->rcgctl1		= I915_READ(GEN6_RCGCTL1);
	s->rcgctl2		= I915_READ(GEN6_RCGCTL2);
	s->rstctl		= I915_READ(GEN6_RSTCTL);
	s->misccpctl		= I915_READ(GEN7_MISCCPCTL);
 
	/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
	s->gfxpause		= I915_READ(GEN6_GFXPAUSE);
	s->rpdeuhwtc		= I915_READ(GEN6_RPDEUHWTC);
	s->rpdeuc		= I915_READ(GEN6_RPDEUC);
	s->ecobus		= I915_READ(ECOBUS);
	s->pwrdwnupctl		= I915_READ(VLV_PWRDWNUPCTL);
	s->rp_down_timeout	= I915_READ(GEN6_RP_DOWN_TIMEOUT);
	s->rp_deucsw		= I915_READ(GEN6_RPDEUCSW);
	s->rcubmabdtmr		= I915_READ(GEN6_RCUBMABDTMR);
	s->rcedata		= I915_READ(VLV_RCEDATA);
	s->spare2gh		= I915_READ(VLV_SPAREG2H);
 
	/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
	s->gt_imr		= I915_READ(GTIMR);
	s->gt_ier		= I915_READ(GTIER);
	s->pm_imr		= I915_READ(GEN6_PMIMR);
	s->pm_ier		= I915_READ(GEN6_PMIER);
 
	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
 
	/* GT SA CZ domain, 0x100000-0x138124 */
	s->tilectl		= I915_READ(TILECTL);
	s->gt_fifoctl		= I915_READ(GTFIFOCTL);
	s->gtlc_wake_ctrl	= I915_READ(VLV_GTLC_WAKE_CTRL);
	s->gtlc_survive		= I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	s->pmwgicz		= I915_READ(VLV_PMWGICZ);
 
	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
	s->gu_ctl0		= I915_READ(VLV_GU_CTL0);
	s->gu_ctl1		= I915_READ(VLV_GU_CTL1);
	s->pcbr			= I915_READ(VLV_PCBR);
	s->clock_gate_dis2	= I915_READ(VLV_GUNIT_CLOCK_GATE2);
 
	/*
	 * Not saving any of:
	 * DFT,		0x9800-0x9EC0
	 * SARB,	0xB000-0xB1FC
	 * GAC,		0x5208-0x524C, 0x14000-0x14C000
	 * PCI CFG
	 */
}
 
static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
{
	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
	u32 val;
	int i;
 
	/* GAM 0x4000-0x4770 */
	I915_WRITE(GEN7_WR_WATERMARK,	s->wr_watermark);
	I915_WRITE(GEN7_GFX_PRIO_CTRL,	s->gfx_prio_ctrl);
	I915_WRITE(ARB_MODE,		s->arb_mode | (0xffff << 16));
	I915_WRITE(GEN7_GFX_PEND_TLB0,	s->gfx_pend_tlb0);
	I915_WRITE(GEN7_GFX_PEND_TLB1,	s->gfx_pend_tlb1);
 
	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
		I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
 
	I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
	I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
 
	I915_WRITE(RENDER_HWS_PGA_GEN7,	s->render_hwsp);
	I915_WRITE(GAM_ECOCHK,		s->ecochk);
	I915_WRITE(BSD_HWS_PGA_GEN7,	s->bsd_hwsp);
	I915_WRITE(BLT_HWS_PGA_GEN7,	s->blt_hwsp);
 
	I915_WRITE(GEN7_TLB_RD_ADDR,	s->tlb_rd_addr);
 
	/* MBC 0x9024-0x91D0, 0x8500 */
	I915_WRITE(VLV_G3DCTL,		s->g3dctl);
	I915_WRITE(VLV_GSCKGCTL,	s->gsckgctl);
	I915_WRITE(GEN6_MBCTL,		s->mbctl);
 
	/* GCP 0x9400-0x9424, 0x8100-0x810C */
	I915_WRITE(GEN6_UCGCTL1,	s->ucgctl1);
	I915_WRITE(GEN6_UCGCTL3,	s->ucgctl3);
	I915_WRITE(GEN6_RCGCTL1,	s->rcgctl1);
	I915_WRITE(GEN6_RCGCTL2,	s->rcgctl2);
	I915_WRITE(GEN6_RSTCTL,		s->rstctl);
	I915_WRITE(GEN7_MISCCPCTL,	s->misccpctl);
 
	/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
	I915_WRITE(GEN6_GFXPAUSE,	s->gfxpause);
	I915_WRITE(GEN6_RPDEUHWTC,	s->rpdeuhwtc);
	I915_WRITE(GEN6_RPDEUC,		s->rpdeuc);
	I915_WRITE(ECOBUS,		s->ecobus);
	I915_WRITE(VLV_PWRDWNUPCTL,	s->pwrdwnupctl);
	I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
	I915_WRITE(GEN6_RPDEUCSW,	s->rp_deucsw);
	I915_WRITE(GEN6_RCUBMABDTMR,	s->rcubmabdtmr);
	I915_WRITE(VLV_RCEDATA,		s->rcedata);
	I915_WRITE(VLV_SPAREG2H,	s->spare2gh);
 
	/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
	I915_WRITE(GTIMR,		s->gt_imr);
	I915_WRITE(GTIER,		s->gt_ier);
	I915_WRITE(GEN6_PMIMR,		s->pm_imr);
	I915_WRITE(GEN6_PMIER,		s->pm_ier);
 
	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
		I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
 
	/* GT SA CZ domain, 0x100000-0x138124 */
	I915_WRITE(TILECTL,			s->tilectl);
	I915_WRITE(GTFIFOCTL,			s->gt_fifoctl);
	/*
	 * Preserve the GT allow wake and GFX force clock bit, they are not
	 * be restored, as they are used to control the s0ix suspend/resume
	 * sequence by the caller.
	 */
	val = I915_READ(VLV_GTLC_WAKE_CTRL);
	val &= VLV_GTLC_ALLOWWAKEREQ;
	val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
	I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
 
	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	val &= VLV_GFX_CLK_FORCE_ON_BIT;
	val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
 
	I915_WRITE(VLV_PMWGICZ,			s->pmwgicz);
 
	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
	I915_WRITE(VLV_GU_CTL0,			s->gu_ctl0);
	I915_WRITE(VLV_GU_CTL1,			s->gu_ctl1);
	I915_WRITE(VLV_PCBR,			s->pcbr);
	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);
}
#endif
 
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
{
	u32 val;
	int err;
 
#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
 
	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
	if (force_on)
		val |= VLV_GFX_CLK_FORCE_ON_BIT;
	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
 
	if (!force_on)
		return 0;
 
	err = wait_for(COND, 20);
	if (err)
		DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
			  I915_READ(VLV_GTLC_SURVIVABILITY_REG));
 
	return err;
#undef COND
}
#if 0
static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
{
	u32 val;
	int err = 0;
 
	val = I915_READ(VLV_GTLC_WAKE_CTRL);
	val &= ~VLV_GTLC_ALLOWWAKEREQ;
	if (allow)
		val |= VLV_GTLC_ALLOWWAKEREQ;
	I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
	POSTING_READ(VLV_GTLC_WAKE_CTRL);
 
#define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
	      allow)
	err = wait_for(COND, 1);
	if (err)
		DRM_ERROR("timeout disabling GT waking\n");
	return err;
#undef COND
}
 
static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
				 bool wait_for_on)
{
	u32 mask;
	u32 val;
	int err;
 
	mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
	val = wait_for_on ? mask : 0;
#define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
	if (COND)
		return 0;
 
	DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
		      onoff(wait_for_on),
		      I915_READ(VLV_GTLC_PW_STATUS));
 
	/*
	 * RC6 transitioning can be delayed up to 2 msec (see
	 * valleyview_enable_rps), use 3 msec for safety.
	 */
	err = wait_for(COND, 3);
	if (err)
		DRM_ERROR("timeout waiting for GT wells to go %s\n",
			  onoff(wait_for_on));
 
	return err;
#undef COND
}
 
static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
{
	if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
		return;
 
	DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
	I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
}
 
static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
{
	u32 mask;
	int err;
 
	/*
	 * Bspec defines the following GT well on flags as debug only, so
	 * don't treat them as hard failures.
	 */
	(void)vlv_wait_for_gt_wells(dev_priv, false);
 
	mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
	WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
 
	vlv_check_no_gt_access(dev_priv);
 
	err = vlv_force_gfx_clock(dev_priv, true);
	if (err)
		goto err1;
 
	err = vlv_allow_gt_wake(dev_priv, false);
	if (err)
		goto err2;
 
	if (!IS_CHERRYVIEW(dev_priv->dev))
		vlv_save_gunit_s0ix_state(dev_priv);
 
	err = vlv_force_gfx_clock(dev_priv, false);
	if (err)
		goto err2;
 
	return 0;
 
err2:
	/* For safety always re-enable waking and disable gfx clock forcing */
	vlv_allow_gt_wake(dev_priv, true);
err1:
	vlv_force_gfx_clock(dev_priv, false);
 
	return err;
}
 
static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
				bool rpm_resume)
{
	struct drm_device *dev = dev_priv->dev;
	int err;
	int ret;
 
	/*
	 * If any of the steps fail just try to continue, that's the best we
	 * can do at this point. Return the first error code (which will also
	 * leave RPM permanently disabled).
	 */
	ret = vlv_force_gfx_clock(dev_priv, true);
 
	if (!IS_CHERRYVIEW(dev_priv->dev))
		vlv_restore_gunit_s0ix_state(dev_priv);
 
	err = vlv_allow_gt_wake(dev_priv, true);
	if (!ret)
		ret = err;
 
	err = vlv_force_gfx_clock(dev_priv, false);
	if (!ret)
		ret = err;
 
	vlv_check_no_gt_access(dev_priv);
 
	if (rpm_resume) {
		intel_init_clock_gating(dev);
		i915_gem_restore_fences(dev);
	}
 
	return ret;
}
 
static int intel_runtime_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;
 
	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
		return -ENODEV;
 
	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
		return -ENODEV;
 
	DRM_DEBUG_KMS("Suspending device\n");
 
	/*
	 * We could deadlock here in case another thread holding struct_mutex
	 * calls RPM suspend concurrently, since the RPM suspend will wait
	 * first for this RPM suspend to finish. In this case the concurrent
	 * RPM resume will be followed by its RPM suspend counterpart. Still
	 * for consistency return -EAGAIN, which will reschedule this suspend.
	 */
	if (!mutex_trylock(&dev->struct_mutex)) {
		DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
		/*
		 * Bump the expiration timestamp, otherwise the suspend won't
		 * be rescheduled.
		 */
		pm_runtime_mark_last_busy(device);
 
		return -EAGAIN;
	}
 
	disable_rpm_wakeref_asserts(dev_priv);
 
	/*
	 * We are safe here against re-faults, since the fault handler takes
	 * an RPM reference.
	 */
	i915_gem_release_all_mmaps(dev_priv);
	mutex_unlock(&dev->struct_mutex);
 
	cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
 
	intel_guc_suspend(dev);
 
	intel_suspend_gt_powersave(dev);
	intel_runtime_pm_disable_interrupts(dev_priv);
 
	ret = intel_suspend_complete(dev_priv);
	if (ret) {
		DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
		intel_runtime_pm_enable_interrupts(dev_priv);
 
		enable_rpm_wakeref_asserts(dev_priv);
 
		return ret;
	}
 
	intel_uncore_forcewake_reset(dev, false);
 
	enable_rpm_wakeref_asserts(dev_priv);
	WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
 
	if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
		DRM_ERROR("Unclaimed access detected prior to suspending\n");
 
	dev_priv->pm.suspended = true;
 
	/*
	 * FIXME: We really should find a document that references the arguments
	 * used below!
	 */
	if (IS_BROADWELL(dev)) {
		/*
		 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
		 * being detected, and the call we do at intel_runtime_resume()
		 * won't be able to restore them. Since PCI_D3hot matches the
		 * actual specification and appears to be working, use it.
		 */
		intel_opregion_notify_adapter(dev, PCI_D3hot);
	} else {
		/*
		 * current versions of firmware which depend on this opregion
		 * notification have repurposed the D1 definition to mean
		 * "runtime suspended" vs. what you would normally expect (D3)
		 * to distinguish it from notifications that might be sent via
		 * the suspend path.
		 */
		intel_opregion_notify_adapter(dev, PCI_D1);
	}
 
	assert_forcewakes_inactive(dev_priv);
 
	DRM_DEBUG_KMS("Device suspended\n");
	return 0;
}
 
static int intel_runtime_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret = 0;
 
	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
		return -ENODEV;
 
	DRM_DEBUG_KMS("Resuming device\n");
 
	WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
	disable_rpm_wakeref_asserts(dev_priv);
 
	intel_opregion_notify_adapter(dev, PCI_D0);
	dev_priv->pm.suspended = false;
	if (intel_uncore_unclaimed_mmio(dev_priv))
		DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
	intel_guc_resume(dev);
 
	if (IS_GEN6(dev_priv))
		intel_init_pch_refclk(dev);
 
	if (IS_BROXTON(dev))
		ret = bxt_resume_prepare(dev_priv);
	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
		hsw_disable_pc8(dev_priv);
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
		ret = vlv_resume_prepare(dev_priv, true);
 
	/*
	 * No point of rolling back things in case of an error, as the best
	 * we can do is to hope that things will still work (and disable RPM).
	 */
	i915_gem_init_swizzling(dev);
	gen6_update_ring_freq(dev);
 
	intel_runtime_pm_enable_interrupts(dev_priv);
 
	/*
	 * On VLV/CHV display interrupts are part of the display
	 * power well, so hpd is reinitialized from there. For
	 * everyone else do it here.
	 */
	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
		intel_hpd_init(dev_priv);
 
	intel_enable_gt_powersave(dev);
 
	enable_rpm_wakeref_asserts(dev_priv);
 
	if (ret)
		DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
	else
		DRM_DEBUG_KMS("Device resumed\n");
 
	return ret;
}
 
/*
 * This function implements common functionality of runtime and system
 * suspend sequence.
 */
static int intel_suspend_complete(struct drm_i915_private *dev_priv)
{
	int ret;
 
	if (IS_BROXTON(dev_priv))
		ret = bxt_suspend_complete(dev_priv);
	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
		ret = hsw_suspend_complete(dev_priv);
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
		ret = vlv_suspend_complete(dev_priv);
	else
		ret = 0;
 
	return ret;
}
 
static const struct dev_pm_ops i915_pm_ops = {
	/*
	 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
	 * PMSG_RESUME]
	 */
	.suspend = i915_pm_suspend,
	.suspend_late = i915_pm_suspend_late,
	.resume_early = i915_pm_resume_early,
	.resume = i915_pm_resume,
 
	/*
	 * S4 event handlers
	 * @freeze, @freeze_late    : called (1) before creating the
	 *                            hibernation image [PMSG_FREEZE] and
	 *                            (2) after rebooting, before restoring
	 *                            the image [PMSG_QUIESCE]
	 * @thaw, @thaw_early       : called (1) after creating the hibernation
	 *                            image, before writing it [PMSG_THAW]
	 *                            and (2) after failing to create or
	 *                            restore the image [PMSG_RECOVER]
	 * @poweroff, @poweroff_late: called after writing the hibernation
	 *                            image, before rebooting [PMSG_HIBERNATE]
	 * @restore, @restore_early : called after rebooting and restoring the
	 *                            hibernation image [PMSG_RESTORE]
	 */
	.freeze = i915_pm_suspend,
	.freeze_late = i915_pm_suspend_late,
	.thaw_early = i915_pm_resume_early,
	.thaw = i915_pm_resume,
	.poweroff = i915_pm_suspend,
	.poweroff_late = i915_pm_poweroff_late,
	.restore_early = i915_pm_resume_early,
	.restore = i915_pm_resume,
 
	/* S0ix (via runtime suspend) event handlers */
	.runtime_suspend = intel_runtime_suspend,
	.runtime_resume = intel_runtime_resume,
};
 
static const struct vm_operations_struct i915_gem_vm_ops = {
	.fault = i915_gem_fault,
	.open = drm_gem_vm_open,
	.close = drm_gem_vm_close,
};
 
static const struct file_operations i915_driver_fops = {
	.owner = THIS_MODULE,
	.open = drm_open,
	.release = drm_release,
	.unlocked_ioctl = drm_ioctl,
	.mmap = drm_gem_mmap,
	.poll = drm_poll,
	.read = drm_read,
#ifdef CONFIG_COMPAT
	.compat_ioctl = i915_compat_ioctl,
#endif
	.llseek = noop_llseek,
};
#endif
 
static struct drm_driver driver = {
	/* Don't use MTRRs here; the Xserver or userspace app should
	 * deal with them for Intel hardware.
	 */
	.driver_features =
	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
	    DRIVER_RENDER | DRIVER_MODESET,
	.load = i915_driver_load,
//    .unload = i915_driver_unload,
      .open = i915_driver_open,
//    .lastclose = i915_driver_lastclose,
//    .preclose = i915_driver_preclose,
//    .postclose = i915_driver_postclose,
//	.set_busid = drm_pci_set_busid,
 
#if defined(CONFIG_DEBUG_FS)
	.debugfs_init = i915_debugfs_init,
	.debugfs_cleanup = i915_debugfs_cleanup,
#endif
    .gem_free_object = i915_gem_free_object,
 
//    .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
//    .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
//    .gem_prime_export = i915_gem_prime_export,
//    .gem_prime_import = i915_gem_prime_import,
 
//    .dumb_create = i915_gem_dumb_create,
//    .dumb_map_offset = i915_gem_mmap_gtt,
//    .dumb_destroy = i915_gem_dumb_destroy,
//    .ioctls = i915_ioctls,
//    .fops = &i915_driver_fops,
//    .name = DRIVER_NAME,
//    .desc = DRIVER_DESC,
//    .date = DRIVER_DATE,
//    .major = DRIVER_MAJOR,
//    .minor = DRIVER_MINOR,
//    .patchlevel = DRIVER_PATCHLEVEL,
};
 
 
 
 
int i915_init(void)
{
    static pci_dev_t device;
    const struct pci_device_id  *ent;
    int  err;
 
    ent = find_pci_device(&device, pciidlist);
    if( unlikely(ent == NULL) )
    {
        dbgprintf("device not found\n");
        return -ENODEV;
    };
 
    drm_core_init();
 
    DRM_INFO("device %x:%x\n", device.pci_dev.vendor,
                                device.pci_dev.device);
 
    driver.driver_features |= DRIVER_MODESET+DRIVER_ATOMIC;
 
    err = drm_get_pci_dev(&device.pci_dev, ent, &driver);
 
    return err;
}
 
 
MODULE_AUTHOR("Tungsten Graphics, Inc.");
MODULE_AUTHOR("Intel Corporation");
 
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL and additional rights");

Rev 6937	Rev 7144
1	/* i915_drv.c -- i830,i845,i855,i865,i915 driver -- linux-c --	1	/* i915_drv.c -- i830,i845,i855,i865,i915 driver -- linux-c --
2	*/	2	*/
3	/*	3	/*
4	*	4	*
5	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.	5	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6	* All Rights Reserved.	6	* All Rights Reserved.
7	*	7	*
8	* Permission is hereby granted, free of charge, to any person obtaining a	8	* Permission is hereby granted, free of charge, to any person obtaining a
9	* copy of this software and associated documentation files (the	9	* copy of this software and associated documentation files (the
10	* "Software"), to deal in the Software without restriction, including	10	* "Software"), to deal in the Software without restriction, including
11	* without limitation the rights to use, copy, modify, merge, publish,	11	* without limitation the rights to use, copy, modify, merge, publish,
12	* distribute, sub license, and/or sell copies of the Software, and to	12	* distribute, sub license, and/or sell copies of the Software, and to
13	* permit persons to whom the Software is furnished to do so, subject to	13	* permit persons to whom the Software is furnished to do so, subject to
14	* the following conditions:	14	* the following conditions:
15	*	15	*
16	* The above copyright notice and this permission notice (including the	16	* The above copyright notice and this permission notice (including the
17	* next paragraph) shall be included in all copies or substantial portions	17	* next paragraph) shall be included in all copies or substantial portions
18	* of the Software.	18	* of the Software.
19	*	19	*
20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS	20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF	21	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.	22	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR	23	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,	24	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE	25	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.	26	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27	*	27	*
28	*/	28	*/
29		29
30	#include	30	#include
31	#include	31	#include
32	#include	32	#include
33	#include	33	#include
34	#include "i915_drv.h"	34	#include "i915_drv.h"
35	#include "i915_trace.h"	35	#include "i915_trace.h"
36	#include "intel_drv.h"	36	#include "intel_drv.h"
37		37
38	#include	38	#include
39	#include	39	#include
-		40	#include
-		41	#include
40	#include	42	#include
41		43
42	#include	44	#include
43		45
44	int init_display_kms(struct drm_device *dev);	46	int init_display_kms(struct drm_device *dev);
45		47
46	extern int intel_agp_enabled;	48	extern int intel_agp_enabled;
47		49
48	static struct drm_driver driver;	50	static struct drm_driver driver;
49		51
50	#define GEN_DEFAULT_PIPEOFFSETS \	52	#define GEN_DEFAULT_PIPEOFFSETS \
51	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \	53	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
52	PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \	54	PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
53	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \	55	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
54	TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \	56	TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
55	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }	57	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
56		58
57	#define GEN_CHV_PIPEOFFSETS \	59	#define GEN_CHV_PIPEOFFSETS \
58	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \	60	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
59	CHV_PIPE_C_OFFSET }, \	61	CHV_PIPE_C_OFFSET }, \
60	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \	62	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
61	CHV_TRANSCODER_C_OFFSET, }, \	63	CHV_TRANSCODER_C_OFFSET, }, \
62	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \	64	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
63	CHV_PALETTE_C_OFFSET }	65	CHV_PALETTE_C_OFFSET }
64		66
65	#define CURSOR_OFFSETS \	67	#define CURSOR_OFFSETS \
66	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }	68	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
67		69
68	#define IVB_CURSOR_OFFSETS \	70	#define IVB_CURSOR_OFFSETS \
69	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }	71	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
70		72
71		73
72		74
73		75
74	static const struct intel_device_info intel_i915g_info = {	76	static const struct intel_device_info intel_i915g_info = {
75	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,	77	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
76	.has_overlay = 1, .overlay_needs_physical = 1,	78	.has_overlay = 1, .overlay_needs_physical = 1,
77	.ring_mask = RENDER_RING,	79	.ring_mask = RENDER_RING,
78	GEN_DEFAULT_PIPEOFFSETS,	80	GEN_DEFAULT_PIPEOFFSETS,
79	CURSOR_OFFSETS,	81	CURSOR_OFFSETS,
80	};	82	};
81	static const struct intel_device_info intel_i915gm_info = {	83	static const struct intel_device_info intel_i915gm_info = {
82	.gen = 3, .is_mobile = 1, .num_pipes = 2,	84	.gen = 3, .is_mobile = 1, .num_pipes = 2,
83	.cursor_needs_physical = 1,	85	.cursor_needs_physical = 1,
84	.has_overlay = 1, .overlay_needs_physical = 1,	86	.has_overlay = 1, .overlay_needs_physical = 1,
85	.supports_tv = 1,	87	.supports_tv = 1,
86	.has_fbc = 1,	88	.has_fbc = 1,
87	.ring_mask = RENDER_RING,	89	.ring_mask = RENDER_RING,
88	GEN_DEFAULT_PIPEOFFSETS,	90	GEN_DEFAULT_PIPEOFFSETS,
89	CURSOR_OFFSETS,	91	CURSOR_OFFSETS,
90	};	92	};
91	static const struct intel_device_info intel_i945g_info = {	93	static const struct intel_device_info intel_i945g_info = {
92	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,	94	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
93	.has_overlay = 1, .overlay_needs_physical = 1,	95	.has_overlay = 1, .overlay_needs_physical = 1,
94	.ring_mask = RENDER_RING,	96	.ring_mask = RENDER_RING,
95	GEN_DEFAULT_PIPEOFFSETS,	97	GEN_DEFAULT_PIPEOFFSETS,
96	CURSOR_OFFSETS,	98	CURSOR_OFFSETS,
97	};	99	};
98	static const struct intel_device_info intel_i945gm_info = {	100	static const struct intel_device_info intel_i945gm_info = {
99	.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,	101	.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
100	.has_hotplug = 1, .cursor_needs_physical = 1,	102	.has_hotplug = 1, .cursor_needs_physical = 1,
101	.has_overlay = 1, .overlay_needs_physical = 1,	103	.has_overlay = 1, .overlay_needs_physical = 1,
102	.supports_tv = 1,	104	.supports_tv = 1,
103	.has_fbc = 1,	105	.has_fbc = 1,
104	.ring_mask = RENDER_RING,	106	.ring_mask = RENDER_RING,
105	GEN_DEFAULT_PIPEOFFSETS,	107	GEN_DEFAULT_PIPEOFFSETS,
106	CURSOR_OFFSETS,	108	CURSOR_OFFSETS,
107	};	109	};
108		110
109	static const struct intel_device_info intel_i965g_info = {	111	static const struct intel_device_info intel_i965g_info = {
110	.gen = 4, .is_broadwater = 1, .num_pipes = 2,	112	.gen = 4, .is_broadwater = 1, .num_pipes = 2,
111	.has_hotplug = 1,	113	.has_hotplug = 1,
112	.has_overlay = 1,	114	.has_overlay = 1,
113	.ring_mask = RENDER_RING,	115	.ring_mask = RENDER_RING,
114	GEN_DEFAULT_PIPEOFFSETS,	116	GEN_DEFAULT_PIPEOFFSETS,
115	CURSOR_OFFSETS,	117	CURSOR_OFFSETS,
116	};	118	};
117		119
118	static const struct intel_device_info intel_i965gm_info = {	120	static const struct intel_device_info intel_i965gm_info = {
119	.gen = 4, .is_crestline = 1, .num_pipes = 2,	121	.gen = 4, .is_crestline = 1, .num_pipes = 2,
120	.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,	122	.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
121	.has_overlay = 1,	123	.has_overlay = 1,
122	.supports_tv = 1,	124	.supports_tv = 1,
123	.ring_mask = RENDER_RING,	125	.ring_mask = RENDER_RING,
124	GEN_DEFAULT_PIPEOFFSETS,	126	GEN_DEFAULT_PIPEOFFSETS,
125	CURSOR_OFFSETS,	127	CURSOR_OFFSETS,
126	};	128	};
127		129
128	static const struct intel_device_info intel_g33_info = {	130	static const struct intel_device_info intel_g33_info = {
129	.gen = 3, .is_g33 = 1, .num_pipes = 2,	131	.gen = 3, .is_g33 = 1, .num_pipes = 2,
130	.need_gfx_hws = 1, .has_hotplug = 1,	132	.need_gfx_hws = 1, .has_hotplug = 1,
131	.has_overlay = 1,	133	.has_overlay = 1,
132	.ring_mask = RENDER_RING,	134	.ring_mask = RENDER_RING,
133	GEN_DEFAULT_PIPEOFFSETS,	135	GEN_DEFAULT_PIPEOFFSETS,
134	CURSOR_OFFSETS,	136	CURSOR_OFFSETS,
135	};	137	};
136		138
137	static const struct intel_device_info intel_g45_info = {	139	static const struct intel_device_info intel_g45_info = {
138	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,	140	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
139	.has_pipe_cxsr = 1, .has_hotplug = 1,	141	.has_pipe_cxsr = 1, .has_hotplug = 1,
140	.ring_mask = RENDER_RING \| BSD_RING,	142	.ring_mask = RENDER_RING \| BSD_RING,
141	GEN_DEFAULT_PIPEOFFSETS,	143	GEN_DEFAULT_PIPEOFFSETS,
142	CURSOR_OFFSETS,	144	CURSOR_OFFSETS,
143	};	145	};
144		146
145	static const struct intel_device_info intel_gm45_info = {	147	static const struct intel_device_info intel_gm45_info = {
146	.gen = 4, .is_g4x = 1, .num_pipes = 2,	148	.gen = 4, .is_g4x = 1, .num_pipes = 2,
147	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,	149	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
148	.has_pipe_cxsr = 1, .has_hotplug = 1,	150	.has_pipe_cxsr = 1, .has_hotplug = 1,
149	.supports_tv = 1,	151	.supports_tv = 1,
150	.ring_mask = RENDER_RING \| BSD_RING,	152	.ring_mask = RENDER_RING \| BSD_RING,
151	GEN_DEFAULT_PIPEOFFSETS,	153	GEN_DEFAULT_PIPEOFFSETS,
152	CURSOR_OFFSETS,	154	CURSOR_OFFSETS,
153	};	155	};
154		156
155	static const struct intel_device_info intel_pineview_info = {	157	static const struct intel_device_info intel_pineview_info = {
156	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,	158	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
157	.need_gfx_hws = 1, .has_hotplug = 1,	159	.need_gfx_hws = 1, .has_hotplug = 1,
158	.has_overlay = 1,	160	.has_overlay = 1,
159	GEN_DEFAULT_PIPEOFFSETS,	161	GEN_DEFAULT_PIPEOFFSETS,
160	CURSOR_OFFSETS,	162	CURSOR_OFFSETS,
161	};	163	};
162		164
163	static const struct intel_device_info intel_ironlake_d_info = {	165	static const struct intel_device_info intel_ironlake_d_info = {
164	.gen = 5, .num_pipes = 2,	166	.gen = 5, .num_pipes = 2,
165	.need_gfx_hws = 1, .has_hotplug = 1,	167	.need_gfx_hws = 1, .has_hotplug = 1,
166	.ring_mask = RENDER_RING \| BSD_RING,	168	.ring_mask = RENDER_RING \| BSD_RING,
167	GEN_DEFAULT_PIPEOFFSETS,	169	GEN_DEFAULT_PIPEOFFSETS,
168	CURSOR_OFFSETS,	170	CURSOR_OFFSETS,
169	};	171	};
170		172
171	static const struct intel_device_info intel_ironlake_m_info = {	173	static const struct intel_device_info intel_ironlake_m_info = {
172	.gen = 5, .is_mobile = 1, .num_pipes = 2,	174	.gen = 5, .is_mobile = 1, .num_pipes = 2,
173	.need_gfx_hws = 1, .has_hotplug = 1,	175	.need_gfx_hws = 1, .has_hotplug = 1,
174	.has_fbc = 1,	176	.has_fbc = 1,
175	.ring_mask = RENDER_RING \| BSD_RING,	177	.ring_mask = RENDER_RING \| BSD_RING,
176	GEN_DEFAULT_PIPEOFFSETS,	178	GEN_DEFAULT_PIPEOFFSETS,
177	CURSOR_OFFSETS,	179	CURSOR_OFFSETS,
178	};	180	};
179		181
180	static const struct intel_device_info intel_sandybridge_d_info = {	182	static const struct intel_device_info intel_sandybridge_d_info = {
181	.gen = 6, .num_pipes = 2,	183	.gen = 6, .num_pipes = 2,
182	.need_gfx_hws = 1, .has_hotplug = 1,	184	.need_gfx_hws = 1, .has_hotplug = 1,
183	.has_fbc = 1,	185	.has_fbc = 1,
184	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING,	186	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING,
185	.has_llc = 1,	187	.has_llc = 1,
186	GEN_DEFAULT_PIPEOFFSETS,	188	GEN_DEFAULT_PIPEOFFSETS,
187	CURSOR_OFFSETS,	189	CURSOR_OFFSETS,
188	};	190	};
189		191
190	static const struct intel_device_info intel_sandybridge_m_info = {	192	static const struct intel_device_info intel_sandybridge_m_info = {
191	.gen = 6, .is_mobile = 1, .num_pipes = 2,	193	.gen = 6, .is_mobile = 1, .num_pipes = 2,
192	.need_gfx_hws = 1, .has_hotplug = 1,	194	.need_gfx_hws = 1, .has_hotplug = 1,
193	.has_fbc = 1,	195	.has_fbc = 1,
194	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING,	196	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING,
195	.has_llc = 1,	197	.has_llc = 1,
196	GEN_DEFAULT_PIPEOFFSETS,	198	GEN_DEFAULT_PIPEOFFSETS,
197	CURSOR_OFFSETS,	199	CURSOR_OFFSETS,
198	};	200	};
199		201
200	#define GEN7_FEATURES \	202	#define GEN7_FEATURES \
201	.gen = 7, .num_pipes = 3, \	203	.gen = 7, .num_pipes = 3, \
202	.need_gfx_hws = 1, .has_hotplug = 1, \	204	.need_gfx_hws = 1, .has_hotplug = 1, \
203	.has_fbc = 1, \	205	.has_fbc = 1, \
204	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING, \	206	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING, \
205	.has_llc = 1, \	207	.has_llc = 1, \
206	GEN_DEFAULT_PIPEOFFSETS, \	208	GEN_DEFAULT_PIPEOFFSETS, \
207	IVB_CURSOR_OFFSETS	209	IVB_CURSOR_OFFSETS
208		210
209	static const struct intel_device_info intel_ivybridge_d_info = {	211	static const struct intel_device_info intel_ivybridge_d_info = {
210	GEN7_FEATURES,	212	GEN7_FEATURES,
211	.is_ivybridge = 1,	213	.is_ivybridge = 1,
212	};	214	};
213		215
214	static const struct intel_device_info intel_ivybridge_m_info = {	216	static const struct intel_device_info intel_ivybridge_m_info = {
215	GEN7_FEATURES,	217	GEN7_FEATURES,
216	.is_ivybridge = 1,	218	.is_ivybridge = 1,
217	.is_mobile = 1,	219	.is_mobile = 1,
218	};	220	};
219		221
220	static const struct intel_device_info intel_ivybridge_q_info = {	222	static const struct intel_device_info intel_ivybridge_q_info = {
221	GEN7_FEATURES,	223	GEN7_FEATURES,
222	.is_ivybridge = 1,	224	.is_ivybridge = 1,
223	.num_pipes = 0, /* legal, last one wins */	225	.num_pipes = 0, /* legal, last one wins */
224	};	226	};
225		227
226	#define VLV_FEATURES \	228	#define VLV_FEATURES \
227	.gen = 7, .num_pipes = 2, \	229	.gen = 7, .num_pipes = 2, \
228	.need_gfx_hws = 1, .has_hotplug = 1, \	230	.need_gfx_hws = 1, .has_hotplug = 1, \
229	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING, \	231	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING, \
230	.display_mmio_offset = VLV_DISPLAY_BASE, \	232	.display_mmio_offset = VLV_DISPLAY_BASE, \
231	GEN_DEFAULT_PIPEOFFSETS, \	233	GEN_DEFAULT_PIPEOFFSETS, \
232	CURSOR_OFFSETS	234	CURSOR_OFFSETS
233		235
234	static const struct intel_device_info intel_valleyview_m_info = {	236	static const struct intel_device_info intel_valleyview_m_info = {
235	VLV_FEATURES,	237	VLV_FEATURES,
236	.is_valleyview = 1,	238	.is_valleyview = 1,
237	.is_mobile = 1,	239	.is_mobile = 1,
238	};	240	};
239		241
240	static const struct intel_device_info intel_valleyview_d_info = {	242	static const struct intel_device_info intel_valleyview_d_info = {
241	VLV_FEATURES,	243	VLV_FEATURES,
242	.is_valleyview = 1,	244	.is_valleyview = 1,
243	};	245	};
244		246
245	#define HSW_FEATURES \	247	#define HSW_FEATURES \
246	GEN7_FEATURES, \	248	GEN7_FEATURES, \
247	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING, \	249	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING, \
248	.has_ddi = 1, \	250	.has_ddi = 1, \
249	.has_fpga_dbg = 1	251	.has_fpga_dbg = 1
250		252
251	static const struct intel_device_info intel_haswell_d_info = {	253	static const struct intel_device_info intel_haswell_d_info = {
252	HSW_FEATURES,	254	HSW_FEATURES,
253	.is_haswell = 1,	255	.is_haswell = 1,
254	};	256	};
255		257
256	static const struct intel_device_info intel_haswell_m_info = {	258	static const struct intel_device_info intel_haswell_m_info = {
257	HSW_FEATURES,	259	HSW_FEATURES,
258	.is_haswell = 1,	260	.is_haswell = 1,
259	.is_mobile = 1,	261	.is_mobile = 1,
260	};	262	};
261		263
262	static const struct intel_device_info intel_broadwell_d_info = {	264	static const struct intel_device_info intel_broadwell_d_info = {
263	HSW_FEATURES,	265	HSW_FEATURES,
264	.gen = 8,	266	.gen = 8,
265	};	267	};
266		268
267	static const struct intel_device_info intel_broadwell_m_info = {	269	static const struct intel_device_info intel_broadwell_m_info = {
268	HSW_FEATURES,	270	HSW_FEATURES,
269	.gen = 8, .is_mobile = 1,	271	.gen = 8, .is_mobile = 1,
270	};	272	};
271		273
272	static const struct intel_device_info intel_broadwell_gt3d_info = {	274	static const struct intel_device_info intel_broadwell_gt3d_info = {
273	HSW_FEATURES,	275	HSW_FEATURES,
274	.gen = 8,	276	.gen = 8,
275	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,	277	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
276	};	278	};
277		279
278	static const struct intel_device_info intel_broadwell_gt3m_info = {	280	static const struct intel_device_info intel_broadwell_gt3m_info = {
279	HSW_FEATURES,	281	HSW_FEATURES,
280	.gen = 8, .is_mobile = 1,	282	.gen = 8, .is_mobile = 1,
281	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,	283	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
282	};	284	};
283		285
284	static const struct intel_device_info intel_cherryview_info = {	286	static const struct intel_device_info intel_cherryview_info = {
285	.gen = 8, .num_pipes = 3,	287	.gen = 8, .num_pipes = 3,
286	.need_gfx_hws = 1, .has_hotplug = 1,	288	.need_gfx_hws = 1, .has_hotplug = 1,
287	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING,	289	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING,
288	.is_cherryview = 1,	290	.is_cherryview = 1,
289	.display_mmio_offset = VLV_DISPLAY_BASE,	291	.display_mmio_offset = VLV_DISPLAY_BASE,
290	GEN_CHV_PIPEOFFSETS,	292	GEN_CHV_PIPEOFFSETS,
291	CURSOR_OFFSETS,	293	CURSOR_OFFSETS,
292	};	294	};
293		295
294	static const struct intel_device_info intel_skylake_info = {	296	static const struct intel_device_info intel_skylake_info = {
295	HSW_FEATURES,	297	HSW_FEATURES,
296	.is_skylake = 1,	298	.is_skylake = 1,
297	.gen = 9,	299	.gen = 9,
298	};	300	};
299		301
300	static const struct intel_device_info intel_skylake_gt3_info = {	302	static const struct intel_device_info intel_skylake_gt3_info = {
301	HSW_FEATURES,	303	HSW_FEATURES,
302	.is_skylake = 1,	304	.is_skylake = 1,
303	.gen = 9,	305	.gen = 9,
304	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,	306	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
305	};	307	};
306		308
307	static const struct intel_device_info intel_broxton_info = {	309	static const struct intel_device_info intel_broxton_info = {
308	.is_preliminary = 1,	310	.is_preliminary = 1,
309	.is_broxton = 1,	311	.is_broxton = 1,
310	.gen = 9,	312	.gen = 9,
311	.need_gfx_hws = 1, .has_hotplug = 1,	313	.need_gfx_hws = 1, .has_hotplug = 1,
312	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING,	314	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING,
313	.num_pipes = 3,	315	.num_pipes = 3,
314	.has_ddi = 1,	316	.has_ddi = 1,
315	.has_fpga_dbg = 1,	317	.has_fpga_dbg = 1,
316	.has_fbc = 1,	318	.has_fbc = 1,
317	GEN_DEFAULT_PIPEOFFSETS,	319	GEN_DEFAULT_PIPEOFFSETS,
318	IVB_CURSOR_OFFSETS,	320	IVB_CURSOR_OFFSETS,
319	};	321	};
320		322
321	static const struct intel_device_info intel_kabylake_info = {	323	static const struct intel_device_info intel_kabylake_info = {
322	HSW_FEATURES,	324	HSW_FEATURES,
323	.is_preliminary = 1,	325	.is_preliminary = 1,
324	.is_kabylake = 1,	326	.is_kabylake = 1,
325	.gen = 9,	327	.gen = 9,
326	};	328	};
327		329
328	static const struct intel_device_info intel_kabylake_gt3_info = {	330	static const struct intel_device_info intel_kabylake_gt3_info = {
329	HSW_FEATURES,	331	HSW_FEATURES,
330	.is_preliminary = 1,	332	.is_preliminary = 1,
331	.is_kabylake = 1,	333	.is_kabylake = 1,
332	.gen = 9,	334	.gen = 9,
333	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,	335	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
334	};	336	};
335		337
336	/*	338	/*
337	* Make sure any device matches here are from most specific to most	339	* Make sure any device matches here are from most specific to most
338	* general. For example, since the Quanta match is based on the subsystem	340	* general. For example, since the Quanta match is based on the subsystem
339	* and subvendor IDs, we need it to come before the more general IVB	341	* and subvendor IDs, we need it to come before the more general IVB
340	* PCI ID matches, otherwise we'll use the wrong info struct above.	342	* PCI ID matches, otherwise we'll use the wrong info struct above.
341	*/	343	*/
342	static const struct pci_device_id pciidlist[] = {	344	static const struct pci_device_id pciidlist[] = {
343	INTEL_I915G_IDS(&intel_i915g_info),	345	INTEL_I915G_IDS(&intel_i915g_info),
344	INTEL_I915GM_IDS(&intel_i915gm_info),	346	INTEL_I915GM_IDS(&intel_i915gm_info),
345	INTEL_I945G_IDS(&intel_i945g_info),	347	INTEL_I945G_IDS(&intel_i945g_info),
346	INTEL_I945GM_IDS(&intel_i945gm_info),	348	INTEL_I945GM_IDS(&intel_i945gm_info),
347	INTEL_I965G_IDS(&intel_i965g_info),	349	INTEL_I965G_IDS(&intel_i965g_info),
348	INTEL_G33_IDS(&intel_g33_info),	350	INTEL_G33_IDS(&intel_g33_info),
349	INTEL_I965GM_IDS(&intel_i965gm_info),	351	INTEL_I965GM_IDS(&intel_i965gm_info),
350	INTEL_GM45_IDS(&intel_gm45_info),	352	INTEL_GM45_IDS(&intel_gm45_info),
351	INTEL_G45_IDS(&intel_g45_info),	353	INTEL_G45_IDS(&intel_g45_info),
352	INTEL_PINEVIEW_IDS(&intel_pineview_info),	354	INTEL_PINEVIEW_IDS(&intel_pineview_info),
353	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),	355	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
354	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),	356	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
355	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),	357	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
356	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),	358	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
357	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */	359	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
358	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),	360	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
359	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),	361	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
360	INTEL_HSW_D_IDS(&intel_haswell_d_info),	362	INTEL_HSW_D_IDS(&intel_haswell_d_info),
361	INTEL_HSW_M_IDS(&intel_haswell_m_info),	363	INTEL_HSW_M_IDS(&intel_haswell_m_info),
362	INTEL_VLV_M_IDS(&intel_valleyview_m_info),	364	INTEL_VLV_M_IDS(&intel_valleyview_m_info),
363	INTEL_VLV_D_IDS(&intel_valleyview_d_info),	365	INTEL_VLV_D_IDS(&intel_valleyview_d_info),
364	INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),	366	INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
365	INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),	367	INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
366	INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),	368	INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
367	INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),	369	INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
368	INTEL_CHV_IDS(&intel_cherryview_info),	370	INTEL_CHV_IDS(&intel_cherryview_info),
369	INTEL_SKL_GT1_IDS(&intel_skylake_info),	371	INTEL_SKL_GT1_IDS(&intel_skylake_info),
370	INTEL_SKL_GT2_IDS(&intel_skylake_info),	372	INTEL_SKL_GT2_IDS(&intel_skylake_info),
371	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),	373	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
372	INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),	374	INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
373	INTEL_BXT_IDS(&intel_broxton_info),	375	INTEL_BXT_IDS(&intel_broxton_info),
374	INTEL_KBL_GT1_IDS(&intel_kabylake_info),	376	INTEL_KBL_GT1_IDS(&intel_kabylake_info),
375	INTEL_KBL_GT2_IDS(&intel_kabylake_info),	377	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
376	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),	378	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
377	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),	379	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
378	{0, 0, 0}	380	{0, 0, 0}
379	};	381	};
380		382
381		383
382		384
383	static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)	385	static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
384	{	386	{
385	enum intel_pch ret = PCH_NOP;	387	enum intel_pch ret = PCH_NOP;
386		388
387	/*	389	/*
388	* In a virtualized passthrough environment we can be in a	390	* In a virtualized passthrough environment we can be in a
389	* setup where the ISA bridge is not able to be passed through.	391	* setup where the ISA bridge is not able to be passed through.
390	* In this case, a south bridge can be emulated and we have to	392	* In this case, a south bridge can be emulated and we have to
391	* make an educated guess as to which PCH is really there.	393	* make an educated guess as to which PCH is really there.
392	*/	394	*/
393		395
394	if (IS_GEN5(dev)) {	396	if (IS_GEN5(dev)) {
395	ret = PCH_IBX;	397	ret = PCH_IBX;
396	DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");	398	DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
397	} else if (IS_GEN6(dev) \|\| IS_IVYBRIDGE(dev)) {	399	} else if (IS_GEN6(dev) \|\| IS_IVYBRIDGE(dev)) {
398	ret = PCH_CPT;	400	ret = PCH_CPT;
399	DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");	401	DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
400	} else if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) {	402	} else if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) {
401	ret = PCH_LPT;	403	ret = PCH_LPT;
402	DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");	404	DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
403	} else if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev)) {	405	} else if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev)) {
404	ret = PCH_SPT;	406	ret = PCH_SPT;
405	DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");	407	DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
406	}	408	}
407		409
408	return ret;	410	return ret;
409	}	411	}
410		412
411	void intel_detect_pch(struct drm_device *dev)	413	void intel_detect_pch(struct drm_device *dev)
412	{	414	{
413	struct drm_i915_private *dev_priv = dev->dev_private;	415	struct drm_i915_private *dev_priv = dev->dev_private;
414	struct pci_dev *pch = NULL;	416	struct pci_dev *pch = NULL;
415		417
416	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting	418	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
417	* (which really amounts to a PCH but no South Display).	419	* (which really amounts to a PCH but no South Display).
418	*/	420	*/
419	if (INTEL_INFO(dev)->num_pipes == 0) {	421	if (INTEL_INFO(dev)->num_pipes == 0) {
420	dev_priv->pch_type = PCH_NOP;	422	dev_priv->pch_type = PCH_NOP;
421	return;	423	return;
422	}	424	}
423		425
424	/*	426	/*
425	* The reason to probe ISA bridge instead of Dev31:Fun0 is to	427	* The reason to probe ISA bridge instead of Dev31:Fun0 is to
426	* make graphics device passthrough work easy for VMM, that only	428	* make graphics device passthrough work easy for VMM, that only
427	* need to expose ISA bridge to let driver know the real hardware	429	* need to expose ISA bridge to let driver know the real hardware
428	* underneath. This is a requirement from virtualization team.	430	* underneath. This is a requirement from virtualization team.
429	*	431	*
430	* In some virtualized environments (e.g. XEN), there is irrelevant	432	* In some virtualized environments (e.g. XEN), there is irrelevant
431	* ISA bridge in the system. To work reliably, we should scan trhough	433	* ISA bridge in the system. To work reliably, we should scan trhough
432	* all the ISA bridge devices and check for the first match, instead	434	* all the ISA bridge devices and check for the first match, instead
433	* of only checking the first one.	435	* of only checking the first one.
434	*/	436	*/
435	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {	437	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
436	if (pch->vendor == PCI_VENDOR_ID_INTEL) {	438	if (pch->vendor == PCI_VENDOR_ID_INTEL) {
437	unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;	439	unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
438	dev_priv->pch_id = id;	440	dev_priv->pch_id = id;
439		441
440	if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {	442	if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
441	dev_priv->pch_type = PCH_IBX;	443	dev_priv->pch_type = PCH_IBX;
442	DRM_DEBUG_KMS("Found Ibex Peak PCH\n");	444	DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
443	WARN_ON(!IS_GEN5(dev));	445	WARN_ON(!IS_GEN5(dev));
444	} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {	446	} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
445	dev_priv->pch_type = PCH_CPT;	447	dev_priv->pch_type = PCH_CPT;
446	DRM_DEBUG_KMS("Found CougarPoint PCH\n");	448	DRM_DEBUG_KMS("Found CougarPoint PCH\n");
447	WARN_ON(!(IS_GEN6(dev) \|\| IS_IVYBRIDGE(dev)));	449	WARN_ON(!(IS_GEN6(dev) \|\| IS_IVYBRIDGE(dev)));
448	} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {	450	} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
449	/* PantherPoint is CPT compatible */	451	/* PantherPoint is CPT compatible */
450	dev_priv->pch_type = PCH_CPT;	452	dev_priv->pch_type = PCH_CPT;
451	DRM_DEBUG_KMS("Found PantherPoint PCH\n");	453	DRM_DEBUG_KMS("Found PantherPoint PCH\n");
452	WARN_ON(!(IS_GEN6(dev) \|\| IS_IVYBRIDGE(dev)));	454	WARN_ON(!(IS_GEN6(dev) \|\| IS_IVYBRIDGE(dev)));
453	} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {	455	} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
454	dev_priv->pch_type = PCH_LPT;	456	dev_priv->pch_type = PCH_LPT;
455	DRM_DEBUG_KMS("Found LynxPoint PCH\n");	457	DRM_DEBUG_KMS("Found LynxPoint PCH\n");
456	WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));	458	WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
457	WARN_ON(IS_HSW_ULT(dev) \|\| IS_BDW_ULT(dev));	459	WARN_ON(IS_HSW_ULT(dev) \|\| IS_BDW_ULT(dev));
458	} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {	460	} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
459	dev_priv->pch_type = PCH_LPT;	461	dev_priv->pch_type = PCH_LPT;
460	DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");	462	DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
461	WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));	463	WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
462	WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));	464	WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
463	} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {	465	} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
464	dev_priv->pch_type = PCH_SPT;	466	dev_priv->pch_type = PCH_SPT;
465	DRM_DEBUG_KMS("Found SunrisePoint PCH\n");	467	DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
466	WARN_ON(!IS_SKYLAKE(dev) &&	468	WARN_ON(!IS_SKYLAKE(dev) &&
467	!IS_KABYLAKE(dev));	469	!IS_KABYLAKE(dev));
468	} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {	470	} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
469	dev_priv->pch_type = PCH_SPT;	471	dev_priv->pch_type = PCH_SPT;
470	DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");	472	DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
471	WARN_ON(!IS_SKYLAKE(dev) &&	473	WARN_ON(!IS_SKYLAKE(dev) &&
472	!IS_KABYLAKE(dev));	474	!IS_KABYLAKE(dev));
473	} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) \|\|	475	} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) \|\|
474	((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&	476	((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
475	pch->subsystem_vendor == 0x1af4 &&	477	pch->subsystem_vendor == 0x1af4 &&
476	pch->subsystem_device == 0x1100)) {	478	pch->subsystem_device == 0x1100)) {
477	dev_priv->pch_type = intel_virt_detect_pch(dev);	479	dev_priv->pch_type = intel_virt_detect_pch(dev);
478	} else	480	} else
479	continue;	481	continue;
480		482
481	break;	483	break;
482	}	484	}
483	}	485	}
484	if (!pch)	486	if (!pch)
485	DRM_DEBUG_KMS("No PCH found.\n");	487	DRM_DEBUG_KMS("No PCH found.\n");
486		488
487	// pci_dev_put(pch);	489	// pci_dev_put(pch);
488	}	490	}
489		491
490	bool i915_semaphore_is_enabled(struct drm_device *dev)	492	bool i915_semaphore_is_enabled(struct drm_device *dev)
491	{	493	{
492	if (INTEL_INFO(dev)->gen < 6)	494	if (INTEL_INFO(dev)->gen < 6)
493	return false;	495	return false;
494		496
495	if (i915.semaphores >= 0)	497	if (i915.semaphores >= 0)
496	return i915.semaphores;	498	return i915.semaphores;
497		499
498	/* TODO: make semaphores and Execlists play nicely together */	500	/* TODO: make semaphores and Execlists play nicely together */

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_drv.c @ 7173 – Rev 6937 → 7144