Rev 6937 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 6937 | Rev 7144 | ||
|---|---|---|---|
| Line 35... | Line 35... | ||
| 35 | #include "i915_trace.h" |
35 | #include "i915_trace.h" |
| 36 | #include "intel_drv.h" |
36 | #include "intel_drv.h" |
| Line 37... | Line 37... | ||
| 37 | 37 | ||
| 38 | #include |
38 | #include |
| - | 39 | #include |
|
| - | 40 | #include |
|
| 39 | #include |
41 | #include |
| Line 40... | Line 42... | ||
| 40 | #include |
42 | #include |
| Line 41... | Line 43... | ||
| 41 | 43 | ||
| Line 570... | Line 572... | ||
| 570 | 572 | ||
| Line 571... | Line 573... | ||
| 571 | intel_guc_suspend(dev); |
573 | intel_guc_suspend(dev); |
| Line 572... | Line -... | ||
| 572 | - | ||
| 573 | intel_suspend_gt_powersave(dev); |
- | |
| 574 | - | ||
| 575 | /* |
- | |
| 576 | * Disable CRTCs directly since we want to preserve sw state |
- | |
| 577 | * for _thaw. Also, power gate the CRTC power wells. |
574 | |
| 578 | */ |
- | |
| Line 579... | Line 575... | ||
| 579 | drm_modeset_lock_all(dev); |
575 | intel_suspend_gt_powersave(dev); |
| Line 580... | Line 576... | ||
| 580 | intel_display_suspend(dev); |
576 | |
| 581 | drm_modeset_unlock_all(dev); |
577 | intel_display_suspend(dev); |
| Line 731... | Line 727... | ||
| 731 | spin_lock_irq(&dev_priv->irq_lock); |
727 | spin_lock_irq(&dev_priv->irq_lock); |
| 732 | if (dev_priv->display.hpd_irq_setup) |
728 | if (dev_priv->display.hpd_irq_setup) |
| 733 | dev_priv->display.hpd_irq_setup(dev); |
729 | dev_priv->display.hpd_irq_setup(dev); |
| 734 | spin_unlock_irq(&dev_priv->irq_lock); |
730 | spin_unlock_irq(&dev_priv->irq_lock); |
| Line 735... | Line -... | ||
| 735 | - | ||
| 736 | drm_modeset_lock_all(dev); |
- | |
| 737 | intel_display_resume(dev); |
- | |
| 738 | drm_modeset_unlock_all(dev); |
- | |
| 739 | 731 | ||
| Line -... | Line 732... | ||
| - | 732 | intel_dp_mst_resume(dev); |
|
| - | 733 | ||
| 740 | intel_dp_mst_resume(dev); |
734 | intel_display_resume(dev); |
| 741 | 735 | ||
| 742 | /* |
736 | /* |
| 743 | * ... but also need to make sure that hotplug processing |
737 | * ... but also need to make sure that hotplug processing |
| 744 | * doesn't cause havoc. Like in the driver load code we don't |
738 | * doesn't cause havoc. Like in the driver load code we don't |
| Line 856... | Line 850... | ||
| 856 | if (ret) |
850 | if (ret) |
| 857 | return ret; |
851 | return ret; |
| Line 858... | Line 852... | ||
| 858 | 852 | ||
| 859 | return i915_drm_resume(dev); |
853 | return i915_drm_resume(dev); |
| - | 854 | } |
|
| Line 860... | Line 855... | ||
| 860 | } |
855 | #endif |
| 861 | 856 | ||
| 862 | /** |
857 | /** |
| 863 | * i915_reset - reset chip after a hang |
858 | * i915_reset - reset chip after a hang |
| Line 908... | Line 903... | ||
| 908 | DRM_ERROR("Failed to reset chip: %i\n", ret); |
903 | DRM_ERROR("Failed to reset chip: %i\n", ret); |
| 909 | mutex_unlock(&dev->struct_mutex); |
904 | mutex_unlock(&dev->struct_mutex); |
| 910 | return ret; |
905 | return ret; |
| 911 | } |
906 | } |
| Line 912... | Line 907... | ||
| 912 | 907 | ||
| Line 913... | Line 908... | ||
| 913 | intel_overlay_reset(dev_priv); |
908 | // intel_overlay_reset(dev_priv); |
| Line 914... | Line 909... | ||
| 914 | 909 | ||
| 915 | /* Ok, now get things going again... */ |
910 | /* Ok, now get things going again... */ |
| Line 950... | Line 945... | ||
| 950 | intel_enable_gt_powersave(dev); |
945 | intel_enable_gt_powersave(dev); |
| Line 951... | Line 946... | ||
| 951 | 946 | ||
| 952 | return 0; |
947 | return 0; |
| Line -... | Line 948... | ||
| - | 948 | } |
|
| 953 | } |
949 | |
| 954 | 950 | #if 0 |
|
| 955 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
951 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 956 | { |
952 | { |
| Line 1079... | Line 1075... | ||
| 1079 | * TODO: when DC5 support is added enable DC5 here if the CSR FW |
1075 | * TODO: when DC5 support is added enable DC5 here if the CSR FW |
| 1080 | * is available. |
1076 | * is available. |
| 1081 | */ |
1077 | */ |
| 1082 | broxton_init_cdclk(dev); |
1078 | broxton_init_cdclk(dev); |
| 1083 | broxton_ddi_phy_init(dev); |
1079 | broxton_ddi_phy_init(dev); |
| 1084 | intel_prepare_ddi(dev); |
- | |
| Line 1085... | Line 1080... | ||
| 1085 | 1080 | ||
| 1086 | return 0; |
1081 | return 0; |
| Line 1087... | Line 1082... | ||
| 1087 | } |
1082 | } |
| Line 1339... | Line 1334... | ||
| 1339 | #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) |
1334 | #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) |
| 1340 | if (COND) |
1335 | if (COND) |
| 1341 | return 0; |
1336 | return 0; |
| Line 1342... | Line 1337... | ||
| 1342 | 1337 | ||
| 1343 | DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", |
1338 | DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", |
| 1344 | wait_for_on ? "on" : "off", |
1339 | onoff(wait_for_on), |
| Line 1345... | Line 1340... | ||
| 1345 | I915_READ(VLV_GTLC_PW_STATUS)); |
1340 | I915_READ(VLV_GTLC_PW_STATUS)); |
| 1346 | 1341 | ||
| 1347 | /* |
1342 | /* |
| 1348 | * RC6 transitioning can be delayed up to 2 msec (see |
1343 | * RC6 transitioning can be delayed up to 2 msec (see |
| 1349 | * valleyview_enable_rps), use 3 msec for safety. |
1344 | * valleyview_enable_rps), use 3 msec for safety. |
| 1350 | */ |
1345 | */ |
| 1351 | err = wait_for(COND, 3); |
1346 | err = wait_for(COND, 3); |
| 1352 | if (err) |
1347 | if (err) |
| Line 1353... | Line 1348... | ||
| 1353 | DRM_ERROR("timeout waiting for GT wells to go %s\n", |
1348 | DRM_ERROR("timeout waiting for GT wells to go %s\n", |
| 1354 | wait_for_on ? "on" : "off"); |
1349 | onoff(wait_for_on)); |
| 1355 | 1350 | ||
| Line 1356... | Line 1351... | ||
| 1356 | return err; |
1351 | return err; |
| 1357 | #undef COND |
1352 | #undef COND |
| 1358 | } |
1353 | } |
| 1359 | 1354 | ||
| Line 1360... | Line 1355... | ||
| 1360 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) |
1355 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) |
| 1361 | { |
1356 | { |
| 1362 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) |
1357 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) |
| Line 1363... | Line 1358... | ||
| 1363 | return; |
1358 | return; |
| 1364 | 1359 | ||
| Line 1504... | Line 1499... | ||
| 1504 | 1499 | ||
| Line 1505... | Line 1500... | ||
| 1505 | intel_uncore_forcewake_reset(dev, false); |
1500 | intel_uncore_forcewake_reset(dev, false); |
| 1506 | 1501 | ||
| - | 1502 | enable_rpm_wakeref_asserts(dev_priv); |
|
| - | 1503 | WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count)); |
|
| - | 1504 | ||
| - | 1505 | if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv)) |
|
| 1507 | enable_rpm_wakeref_asserts(dev_priv); |
1506 | DRM_ERROR("Unclaimed access detected prior to suspending\n"); |
| Line 1508... | Line 1507... | ||
| 1508 | WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count)); |
1507 | |
| 1509 | dev_priv->pm.suspended = true; |
1508 | dev_priv->pm.suspended = true; |
| 1510 | 1509 | ||
| Line 1552... | Line 1551... | ||
| 1552 | WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count)); |
1551 | WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count)); |
| 1553 | disable_rpm_wakeref_asserts(dev_priv); |
1552 | disable_rpm_wakeref_asserts(dev_priv); |
| Line 1554... | Line 1553... | ||
| 1554 | 1553 | ||
| 1555 | intel_opregion_notify_adapter(dev, PCI_D0); |
1554 | intel_opregion_notify_adapter(dev, PCI_D0); |
| - | 1555 | dev_priv->pm.suspended = false; |
|
| - | 1556 | if (intel_uncore_unclaimed_mmio(dev_priv)) |
|
| Line 1556... | Line 1557... | ||
| 1556 | dev_priv->pm.suspended = false; |
1557 | DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n"); |
| Line 1557... | Line 1558... | ||
| 1557 | 1558 | ||
| 1558 | intel_guc_resume(dev); |
1559 | intel_guc_resume(dev); |