WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_drv.c

 #include "i915_trace.h"
 #include "intel_drv.h"
 #include
-#include
-#include
-#include
-#include
 #include
 #include
+#include
+int init_display_kms(struct drm_device *dev);
-#include
+extern int intel_agp_enabled;
 static struct drm_driver driver;
 	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
 #define IVB_CURSOR_OFFSETS \
-	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
-int init_display_kms(struct drm_device *dev);
-extern int intel_agp_enabled;
+	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
 #define PCI_VENDOR_ID_INTEL        0x8086
 #define GEN7_FEATURES  \
 	.gen = 7, .num_pipes = 3, \
 	.need_gfx_hws = 1, .has_hotplug = 1, \
 	.has_fbc = 1, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
-	.has_llc = 1
+	.has_llc = 1, \
+	GEN_DEFAULT_PIPEOFFSETS, \
+	IVB_CURSOR_OFFSETS
 static const struct intel_device_info intel_ivybridge_d_info = {
 	GEN7_FEATURES,
-	.is_ivybridge = 1,
-	GEN_DEFAULT_PIPEOFFSETS,
-	IVB_CURSOR_OFFSETS,
+	.is_ivybridge = 1,
 };
 static const struct intel_device_info intel_ivybridge_m_info = {
 	GEN7_FEATURES,
-	.is_ivybridge = 1,
-	.is_mobile = 1,
-	GEN_DEFAULT_PIPEOFFSETS,
+	.is_ivybridge = 1,
-	IVB_CURSOR_OFFSETS,
+	.is_mobile = 1,
 };
 static const struct intel_device_info intel_ivybridge_q_info = {
-	GEN7_FEATURES,
-	.is_ivybridge = 1,
-	.num_pipes = 0, /* legal, last one wins */
+	GEN7_FEATURES,
+	.is_ivybridge = 1,
+	.num_pipes = 0, /* legal, last one wins */
+};
+#define VLV_FEATURES  \
+	.gen = 7, .num_pipes = 2, \
+	.need_gfx_hws = 1, .has_hotplug = 1, \
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
-	GEN_DEFAULT_PIPEOFFSETS,
+	.display_mmio_offset = VLV_DISPLAY_BASE, \
-	IVB_CURSOR_OFFSETS,
+	GEN_DEFAULT_PIPEOFFSETS, \
-};
-static const struct intel_device_info intel_valleyview_m_info = {
+	CURSOR_OFFSETS
-	GEN7_FEATURES,
-	.is_mobile = 1,
-	.num_pipes = 2,
-	.is_valleyview = 1,
-	.display_mmio_offset = VLV_DISPLAY_BASE,
-	.has_fbc = 0, /* legal, last one wins */
+static const struct intel_device_info intel_valleyview_m_info = {
-	.has_llc = 0, /* legal, last one wins */
+	VLV_FEATURES,
-	GEN_DEFAULT_PIPEOFFSETS,
+	.is_valleyview = 1,
-	CURSOR_OFFSETS,
-};
+	.is_mobile = 1,
-static const struct intel_device_info intel_valleyview_d_info = {
-	GEN7_FEATURES,
-	.num_pipes = 2,
-	.is_valleyview = 1,
-	.display_mmio_offset = VLV_DISPLAY_BASE,
+};
+static const struct intel_device_info intel_valleyview_d_info = {
+	VLV_FEATURES,
+	.is_valleyview = 1,
+};
-	.has_fbc = 0, /* legal, last one wins */
+#define HSW_FEATURES  \
-	.has_llc = 0, /* legal, last one wins */
+	GEN7_FEATURES, \
-	GEN_DEFAULT_PIPEOFFSETS,
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
-	CURSOR_OFFSETS,
-};
-static const struct intel_device_info intel_haswell_d_info = {
-	GEN7_FEATURES,
-	.is_haswell = 1,
+	.has_ddi = 1, \
-	.has_ddi = 1,
+	.has_fpga_dbg = 1
-	.has_fpga_dbg = 1,
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+static const struct intel_device_info intel_haswell_d_info = {
-	GEN_DEFAULT_PIPEOFFSETS,
+	HSW_FEATURES,
-	IVB_CURSOR_OFFSETS,
-};
-static const struct intel_device_info intel_haswell_m_info = {
-	GEN7_FEATURES,
 	.is_haswell = 1,
-	.is_mobile = 1,
+};
-	.has_ddi = 1,
-	.has_fpga_dbg = 1,
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
-	GEN_DEFAULT_PIPEOFFSETS,
-	IVB_CURSOR_OFFSETS,
-};
+static const struct intel_device_info intel_haswell_m_info = {
-static const struct intel_device_info intel_broadwell_d_info = {
-	.gen = 8, .num_pipes = 3,
-	.need_gfx_hws = 1, .has_hotplug = 1,
+	HSW_FEATURES,
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+	.is_haswell = 1,
-	.has_llc = 1,
-	.has_ddi = 1,
-	.has_fpga_dbg = 1,
-	.has_fbc = 1,
+	.is_mobile = 1,
-	GEN_DEFAULT_PIPEOFFSETS,
-	IVB_CURSOR_OFFSETS,
+};
-};
-static const struct intel_device_info intel_broadwell_m_info = {
 	.gen = 8, .is_mobile = 1, .num_pipes = 3,
-	.need_gfx_hws = 1, .has_hotplug = 1,
+static const struct intel_device_info intel_broadwell_d_info = {
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+	HSW_FEATURES,
-	.has_llc = 1,
+	.gen = 8,
-	.has_ddi = 1,
+};
-	.has_fpga_dbg = 1,
-	.has_fbc = 1,
-	GEN_DEFAULT_PIPEOFFSETS,
-	IVB_CURSOR_OFFSETS,
-};
 static const struct intel_device_info intel_broadwell_gt3d_info = {
-	.gen = 8, .num_pipes = 3,
+static const struct intel_device_info intel_broadwell_m_info = {
-	.need_gfx_hws = 1, .has_hotplug = 1,
+	HSW_FEATURES,
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+	.gen = 8, .is_mobile = 1,
-	.has_llc = 1,
+};
-	.has_ddi = 1,
-	.has_fpga_dbg = 1,
-	.has_fbc = 1,
-	GEN_DEFAULT_PIPEOFFSETS,
-	IVB_CURSOR_OFFSETS,
-};
-static const struct intel_device_info intel_broadwell_gt3m_info = {
+static const struct intel_device_info intel_broadwell_gt3d_info = {
-	.gen = 8, .is_mobile = 1, .num_pipes = 3,
+	HSW_FEATURES,
-	.need_gfx_hws = 1, .has_hotplug = 1,
+	.gen = 8,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
-	.has_llc = 1,
+};
 	.has_ddi = 1,
-	.has_fpga_dbg = 1,
+static const struct intel_device_info intel_broadwell_gt3m_info = {
-	.has_fbc = 1,
+	HSW_FEATURES,
-	GEN_DEFAULT_PIPEOFFSETS,
+	.gen = 8, .is_mobile = 1,
-	IVB_CURSOR_OFFSETS,
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+};
 };
-static const struct intel_device_info intel_cherryview_info = {
-	.gen = 8, .num_pipes = 3,
-	.need_gfx_hws = 1, .has_hotplug = 1,
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
-	.is_valleyview = 1,
-	.display_mmio_offset = VLV_DISPLAY_BASE,
+static const struct intel_device_info intel_cherryview_info = {
-	GEN_CHV_PIPEOFFSETS,
-	CURSOR_OFFSETS,
-};
+	.gen = 8, .num_pipes = 3,
 	.need_gfx_hws = 1, .has_hotplug = 1,
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
-static const struct intel_device_info intel_skylake_info = {
+	.is_cherryview = 1,
-	.is_skylake = 1,
+	.display_mmio_offset = VLV_DISPLAY_BASE,
-	.gen = 9, .num_pipes = 3,
-	.need_gfx_hws = 1, .has_hotplug = 1,
+	GEN_CHV_PIPEOFFSETS,
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
-	.has_llc = 1,
-	.has_ddi = 1,
-	.has_fpga_dbg = 1,
-	.has_fbc = 1,
-	GEN_DEFAULT_PIPEOFFSETS,
-	IVB_CURSOR_OFFSETS,
+	CURSOR_OFFSETS,
 };
+static const struct intel_device_info intel_skylake_info = {
-static const struct intel_device_info intel_skylake_gt3_info = {
+	HSW_FEATURES,
 	.is_skylake = 1,
-	.gen = 9, .num_pipes = 3,
+	.gen = 9,
-	.need_gfx_hws = 1, .has_hotplug = 1,
+};
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 	.has_fbc = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 };
+static const struct intel_device_info intel_kabylake_info = {
+	HSW_FEATURES,
+	.is_preliminary = 1,
+	.is_kabylake = 1,
+	.gen = 9,
+};
+static const struct intel_device_info intel_kabylake_gt3_info = {
+	HSW_FEATURES,
+	.is_preliminary = 1,
+	.is_kabylake = 1,
+	.gen = 9,
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+};
 /*
  * Make sure any device matches here are from most specific to most
  * general.  For example, since the Quanta match is based on the subsystem
  * and subvendor IDs, we need it to come before the more general IVB
  * PCI ID matches, otherwise we'll use the wrong info struct above.
  */
-#define INTEL_PCI_IDS \
+static const struct pci_device_id pciidlist[] = {
-	INTEL_I915G_IDS(&intel_i915g_info),	\
+	INTEL_I915G_IDS(&intel_i915g_info),
-	INTEL_I915GM_IDS(&intel_i915gm_info),	\
+	INTEL_I915GM_IDS(&intel_i915gm_info),
-	INTEL_I945G_IDS(&intel_i945g_info),	\
+	INTEL_I945G_IDS(&intel_i945g_info),
-	INTEL_I945GM_IDS(&intel_i945gm_info),	\
+	INTEL_I945GM_IDS(&intel_i945gm_info),
-	INTEL_I965G_IDS(&intel_i965g_info),	\
+	INTEL_I965G_IDS(&intel_i965g_info),
-	INTEL_G33_IDS(&intel_g33_info),		\
+	INTEL_G33_IDS(&intel_g33_info),
-	INTEL_I965GM_IDS(&intel_i965gm_info),	\
+	INTEL_I965GM_IDS(&intel_i965gm_info),
-	INTEL_GM45_IDS(&intel_gm45_info), 	\
+	INTEL_GM45_IDS(&intel_gm45_info),
-	INTEL_G45_IDS(&intel_g45_info), 	\
+	INTEL_G45_IDS(&intel_g45_info),
-	INTEL_PINEVIEW_IDS(&intel_pineview_info),	\
+	INTEL_PINEVIEW_IDS(&intel_pineview_info),
-	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),	\
+	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
-	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),	\
+	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
-	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),	\
+	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
-	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),	\
+	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
-	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
+	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
-	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),	\
+	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
-	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),	\
+	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
-	INTEL_HSW_D_IDS(&intel_haswell_d_info), \
+	INTEL_HSW_D_IDS(&intel_haswell_d_info),
-	INTEL_HSW_M_IDS(&intel_haswell_m_info), \
+	INTEL_HSW_M_IDS(&intel_haswell_m_info),
-	INTEL_VLV_M_IDS(&intel_valleyview_m_info),	\
+	INTEL_VLV_M_IDS(&intel_valleyview_m_info),
-	INTEL_VLV_D_IDS(&intel_valleyview_d_info),	\
+	INTEL_VLV_D_IDS(&intel_valleyview_d_info),
-	INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),	\
+	INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
-	INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),	\
+	INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
-	INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),	\
+	INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
-	INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
+	INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
-	INTEL_CHV_IDS(&intel_cherryview_info),	\
+	INTEL_CHV_IDS(&intel_cherryview_info),
-	INTEL_SKL_GT1_IDS(&intel_skylake_info),	\
+	INTEL_SKL_GT1_IDS(&intel_skylake_info),
-	INTEL_SKL_GT2_IDS(&intel_skylake_info),	\
+	INTEL_SKL_GT2_IDS(&intel_skylake_info),
+	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
-	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),	\
+	INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
-	INTEL_BXT_IDS(&intel_broxton_info)
+	INTEL_BXT_IDS(&intel_broxton_info),
-static const struct pci_device_id pciidlist[] = {		/* aka */
+	INTEL_KBL_GT1_IDS(&intel_kabylake_info),
+	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
+	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
-	INTEL_PCI_IDS,
+	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 	{0, 0, 0}
-};
-#define INTEL_PCH_DEVICE_ID_MASK        0xff00
-#define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
-#define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
+};
 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 #define INTEL_PCH_LPT_DEVICE_ID_TYPE	0x8c00
 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
+{
 		ret = PCH_CPT;
 		DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 		ret = PCH_LPT;
 		DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
-	} else if (IS_SKYLAKE(dev)) {
+	} else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 		ret = PCH_SPT;
 		DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
+	}
 				WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 				WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 			} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_SPT;
 				DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
-				WARN_ON(!IS_SKYLAKE(dev));
+				WARN_ON(!IS_SKYLAKE(dev) &&
+					!IS_KABYLAKE(dev));
 			} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_SPT;
 				DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
-				WARN_ON(!IS_SKYLAKE(dev));
+				WARN_ON(!IS_SKYLAKE(dev) &&
+					!IS_KABYLAKE(dev));
 			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 				    pch->subsystem_vendor == 0x1af4 &&
 				    pch->subsystem_device == 0x1100)) {
 				dev_priv->pch_type = intel_virt_detect_pch(dev);
 	return true;
+}
-#if 0
-void i915_firmware_load_error_print(const char *fw_path, int err)
-{
-	DRM_ERROR("failed to load firmware %s (%d)\n", fw_path, err);
-	/*
-	 * If the reason is not known assume -ENOENT since that's the most
-	 * usual failure mode.
-	 */
-	if (!err)
-		err = -ENOENT;
-	if (!(IS_BUILTIN(CONFIG_DRM_I915) && err == -ENOENT))
-		return;
-	DRM_ERROR(
-	  "The driver is built-in, so to load the firmware you need to\n"
-	  "include it either in the kernel (see CONFIG_EXTRA_FIRMWARE) or\n"
 	  "in your initrd/initramfs image.\n");
 #if 0
 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
+{
 	struct drm_device *dev = dev_priv->dev;
-	struct drm_encoder *encoder;
-	drm_modeset_lock_all(dev);
+	struct intel_encoder *encoder;
-	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
-		struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 	drm_modeset_lock_all(dev);
-		if (intel_encoder->suspend)
+	for_each_intel_encoder(dev, encoder)
-			intel_encoder->suspend(intel_encoder);
+		if (encoder->suspend)
 			encoder->suspend(encoder);
 	drm_modeset_unlock_all(dev);
-}
+}
+static int intel_suspend_complete(struct drm_i915_private *dev_priv);
+static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
+			      bool rpm_resume);
+static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
+static bool suspend_to_idle(struct drm_i915_private *dev_priv)
+{
-static int intel_suspend_complete(struct drm_i915_private *dev_priv);
+#if IS_ENABLED(CONFIG_ACPI_SLEEP)
-static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
+	if (acpi_target_system_state() < ACPI_STATE_S3)
-			      bool rpm_resume);
+		return true;
-static int skl_resume_prepare(struct drm_i915_private *dev_priv);
+#endif
 	/* ignore lid events during suspend */
 	mutex_lock(&dev_priv->modeset_restore_lock);
 	dev_priv->modeset_restore = MODESET_SUSPENDED;
 	mutex_unlock(&dev_priv->modeset_restore_lock);
+	disable_rpm_wakeref_asserts(dev_priv);
 	/* We do a lot of poking in a lot of registers, make sure they work
 	 * properly. */
 	intel_display_set_init_power(dev_priv, true);
 	error = i915_gem_suspend(dev);
 	if (error) {
 		dev_err(&dev->pdev->dev,
 			"GEM idle failed, resume might fail\n");
-		return error;
+		goto out;
+	}
 	i915_gem_suspend_gtt_mappings(dev);
-	i915_save_state(dev);
-	opregion_target_state = PCI_D3cold;
-#if IS_ENABLED(CONFIG_ACPI_SLEEP)
-	if (acpi_target_system_state() < ACPI_STATE_S3)
+	i915_save_state(dev);
 		opregion_target_state = PCI_D1;
-#endif
+	opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
 	dev_priv->suspend_count++;
+	intel_display_set_init_power(dev_priv, false);
+	if (HAS_CSR(dev_priv))
+		flush_work(&dev_priv->csr.work);
+out:
-	intel_display_set_init_power(dev_priv, false);
+	enable_rpm_wakeref_asserts(dev_priv);
-	return 0;
+	return error;
+}
 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
+{
+	struct drm_i915_private *dev_priv = drm_dev->dev_private;
+	bool fw_csr;
+	int ret;
+	disable_rpm_wakeref_asserts(dev_priv);
+	fw_csr = suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
+	/*
+	 * In case of firmware assisted context save/restore don't manually
+	 * deinit the power domains. This also means the CSR/DMC firmware will
+	 * stay active, it will power down any HW resources as required and
+	 * also enable deeper system power states that would be blocked if the
-static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
+	 * firmware was inactive.
 	 */
-	struct drm_i915_private *dev_priv = drm_dev->dev_private;
+	if (!fw_csr)
+		intel_power_domains_suspend(dev_priv);
-	int ret;
+	ret = intel_suspend_complete(dev_priv);
-	ret = intel_suspend_complete(dev_priv);
+	if (ret) {
 		DRM_ERROR("Suspend complete failed: %d\n", ret);
-	if (ret) {
+		if (!fw_csr)
 	 * Acer Aspire 1830T
 	 */
 	if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
 		pci_set_power_state(drm_dev->pdev, PCI_D3hot);
+	dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
+out:
+	enable_rpm_wakeref_asserts(dev_priv);
-	return 0;
+	return ret;
+}
 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
 static int i915_drm_resume(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	disable_rpm_wakeref_asserts(dev_priv);
 	mutex_lock(&dev->struct_mutex);
 	i915_gem_restore_gtt_mappings(dev);
 	intel_opregion_notify_adapter(dev, PCI_D0);
+	drm_kms_helper_poll_enable(dev);
-	drm_kms_helper_poll_enable(dev);
+	enable_rpm_wakeref_asserts(dev_priv);
 	return 0;
+}
 static int i915_drm_resume_early(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int ret = 0;
+	int ret;
 	/*
 	 * We have a resume ordering issue with the snd-hda driver also
 	 * requiring our device to be power up. Due to the lack of a
 	 * parent/child relationship we currently solve this with an early
+	 * resume hook.
+	 *
+	 * FIXME: This should be solved with a special hdmi sink device or
+	 * similar so that power domains can be employed.
+	 */
+	/*
+	 * Note that we need to set the power state explicitly, since we
+	 * powered off the device during freeze and the PCI core won't power
+	 * it back up for us during thaw. Powering off the device during
+	 * freeze is not a hard requirement though, and during the
+	 * suspend/resume phases the PCI core makes sure we get here with the
+	 * device powered on. So in case we change our freeze logic and keep
+	 * the device powered we can also remove the following set power state
+	 * call.
+	 */
+	ret = pci_set_power_state(dev->pdev, PCI_D0);
+	if (ret) {
+		DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
+		goto out;
+	}
+	/*
+	 * Note that pci_enable_device() first enables any parent bridge
+	 * device and only then sets the power state for this device. The
+	 * bridge enabling is a nop though, since bridge devices are resumed
+	 * first. The order of enabling power and enabling the device is
+	 * imposed by the PCI core as described above, so here we preserve the
+	 * same order for the freeze/thaw phases.
+	 *
-	 * resume hook.
+	 * TODO: eventually we should remove pci_disable_device() /
-	 *
+	 * pci_enable_enable_device() from suspend/resume. Due to how they
+	 * depend on the device enable refcount we can't anyway depend on them
+	 * disabling/enabling the device.
-	 * FIXME: This should be solved with a special hdmi sink device or
+	 */
+	if (pci_enable_device(dev->pdev)) {
+		ret = -EIO;
-	 * similar so that power domains can be employed.
+		goto out;
 	 */
 	if (pci_enable_device(dev->pdev))
-		return -EIO;
+	pci_set_master(dev->pdev);
-	pci_set_master(dev->pdev);
+	disable_rpm_wakeref_asserts(dev_priv);
-	if (IS_VALLEYVIEW(dev_priv))
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-		ret = vlv_resume_prepare(dev_priv, false);
-	if (ret)
-		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
+		ret = vlv_resume_prepare(dev_priv, false);
-			  ret);
+	if (ret)
 		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
+			  ret);
 	intel_uncore_early_sanitize(dev, true);
+	if (IS_BROXTON(dev))
+		ret = bxt_resume_prepare(dev_priv);
+	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+		hsw_disable_pc8(dev_priv);
-	if (IS_BROXTON(dev))
+	intel_uncore_sanitize(dev);
 		ret = bxt_resume_prepare(dev_priv);
 		DRM_ERROR("Failed to reset chip: %i\n", ret);
 		mutex_unlock(&dev->struct_mutex);
 		return ret;
+	}
+	intel_overlay_reset(dev_priv);
 	/* Ok, now get things going again... */
 	/*
 		return 0;
 	return i915_drm_resume(drm_dev);
-}
-static int skl_suspend_complete(struct drm_i915_private *dev_priv)
-{
-	/* Enabling DC6 is not a hard requirement to enter runtime D3 */
-	skl_uninit_cdclk(dev_priv);
-	return 0;
+}
 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
+{
 	intel_prepare_ddi(dev);
 	return 0;
-}
-static int skl_resume_prepare(struct drm_i915_private *dev_priv)
-{
-	struct drm_device *dev = dev_priv->dev;
-	skl_init_cdclk(dev_priv);
-	intel_csr_load_program(dev);
-	return 0;
+}
 /*
  * Save all Gunit registers that may be lost after a D3 and a subsequent
  * S0i[R123] transition. The list of registers needing a save/restore is
 		 */
 		pm_runtime_mark_last_busy(device);
 		return -EAGAIN;
+	}
+	disable_rpm_wakeref_asserts(dev_priv);
 	/*
 	 * We are safe here against re-faults, since the fault handler takes
 	 * an RPM reference.
 	 */
 	i915_gem_release_all_mmaps(dev_priv);
+	mutex_unlock(&dev->struct_mutex);
-	mutex_unlock(&dev->struct_mutex);
+	cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
 	intel_guc_suspend(dev);
 	intel_suspend_gt_powersave(dev);
 	intel_runtime_pm_disable_interrupts(dev_priv);
+	ret = intel_suspend_complete(dev_priv);
+	if (ret) {
-	ret = intel_suspend_complete(dev_priv);
+		DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
-	if (ret) {
+		intel_runtime_pm_enable_interrupts(dev_priv);
-		DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
 		intel_runtime_pm_enable_interrupts(dev_priv);
+		enable_rpm_wakeref_asserts(dev_priv);
+		return ret;
+	}
 		return ret;
 	intel_uncore_forcewake_reset(dev, false);
 	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
 		return -ENODEV;
+	DRM_DEBUG_KMS("Resuming device\n");
+	WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
-	DRM_DEBUG_KMS("Resuming device\n");
+	disable_rpm_wakeref_asserts(dev_priv);
 	intel_opregion_notify_adapter(dev, PCI_D0);
 	dev_priv->pm.suspended = false;
 	intel_guc_resume(dev);
-	if (IS_GEN6(dev_priv))
-		intel_init_pch_refclk(dev);
 	if (IS_GEN6(dev_priv))
-	if (IS_BROXTON(dev))
+		intel_init_pch_refclk(dev);
-		ret = bxt_resume_prepare(dev_priv);
-	else if (IS_SKYLAKE(dev))
+	if (IS_BROXTON(dev))
-		ret = skl_resume_prepare(dev_priv);
+		ret = bxt_resume_prepare(dev_priv);
 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		hsw_disable_pc8(dev_priv);
 	/*
 	 * On VLV/CHV display interrupts are part of the display
 	 * power well, so hpd is reinitialized from there. For
 	 * everyone else do it here.
 	 */
-	if (!IS_VALLEYVIEW(dev_priv))
+	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
 		intel_hpd_init(dev_priv);
+	intel_enable_gt_powersave(dev);
-	intel_enable_gt_powersave(dev);
+	enable_rpm_wakeref_asserts(dev_priv);
 	if (ret)
 		DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
+{
 	int ret;
 	if (IS_BROXTON(dev_priv))
-		ret = bxt_suspend_complete(dev_priv);
-	else if (IS_SKYLAKE(dev_priv))
-		ret = skl_suspend_complete(dev_priv);
+		ret = bxt_suspend_complete(dev_priv);
 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		ret = hsw_suspend_complete(dev_priv);
-	else if (IS_VALLEYVIEW(dev_priv))
+	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		ret = vlv_suspend_complete(dev_priv);
 	else
 		ret = 0;
     drm_core_init();
     DRM_INFO("device %x:%x\n", device.pci_dev.vendor,
                                 device.pci_dev.device);
-    driver.driver_features |= DRIVER_MODESET;
+    driver.driver_features |= DRIVER_MODESET+DRIVER_ATOMIC;

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_drv.c – Rev 6660 → 6937