WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_drv.c


/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
 */
/*
 *
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */
 
//#include 
#include 
#include 
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"
 
#include 
#include 
#include 
#include 
 
#include 
 
#include 
 
#define __read_mostly
 
int init_display_kms(struct drm_device *dev);
 
static int i915_modeset __read_mostly = 1;
module_param_named(modeset, i915_modeset, int, 0400);
MODULE_PARM_DESC(modeset,
		"Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
		"1=on, -1=force vga console preference [default])");
 
unsigned int i915_fbpercrtc __always_unused = 0;
module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
 
int i915_panel_ignore_lid __read_mostly         =  1;
module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
MODULE_PARM_DESC(panel_ignore_lid,
		"Override lid status (0=autodetect, 1=autodetect disabled [default], "
		"-1=force lid closed, -2=force lid open)");
 
unsigned int i915_powersave __read_mostly = 1;
module_param_named(powersave, i915_powersave, int, 0600);
MODULE_PARM_DESC(powersave,
		"Enable powersavings, fbc, downclocking, etc. (default: true)");
 
int i915_semaphores __read_mostly = -1;
module_param_named(semaphores, i915_semaphores, int, 0400);
MODULE_PARM_DESC(semaphores,
		"Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
 
int i915_enable_rc6 __read_mostly = -1;
module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
MODULE_PARM_DESC(i915_enable_rc6,
		"Enable power-saving render C-state 6. "
		"Different stages can be selected via bitmask values "
		"(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
		"For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
		"default: -1 (use per-chip default)");
 
int i915_enable_fbc __read_mostly = -1;
module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
MODULE_PARM_DESC(i915_enable_fbc,
		"Enable frame buffer compression for power savings "
		"(default: -1 (use per-chip default))");
 
unsigned int i915_lvds_downclock  __read_mostly =  0;
module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
MODULE_PARM_DESC(lvds_downclock,
		"Use panel (LVDS/eDP) downclocking for power savings "
		"(default: false)");
 
int i915_lvds_channel_mode __read_mostly;
module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
MODULE_PARM_DESC(lvds_channel_mode,
		 "Specify LVDS channel mode "
		 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
 
int i915_panel_use_ssc __read_mostly = -1;
module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
MODULE_PARM_DESC(lvds_use_ssc,
		"Use Spread Spectrum Clock with panels [LVDS/eDP] "
		"(default: auto from VBT)");
 
int i915_vbt_sdvo_panel_type __read_mostly      = -1;
module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
MODULE_PARM_DESC(vbt_sdvo_panel_type,
		"Override/Ignore selection of SDVO panel mode in the VBT "
		"(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 
static bool i915_try_reset __read_mostly = true;
module_param_named(reset, i915_try_reset, bool, 0600);
MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 
bool i915_enable_hangcheck __read_mostly = false;
module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
MODULE_PARM_DESC(enable_hangcheck,
		"Periodically check GPU activity for detecting hangs. "
		"WARNING: Disabling this can cause system wide hangs. "
		"(default: true)");
 
int i915_enable_ppgtt __read_mostly = -1;
module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0400);
MODULE_PARM_DESC(i915_enable_ppgtt,
		"Enable PPGTT (default: true)");
 
int i915_enable_psr __read_mostly = 0;
module_param_named(enable_psr, i915_enable_psr, int, 0600);
MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
 
unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT);
module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
MODULE_PARM_DESC(preliminary_hw_support,
		"Enable preliminary hardware support.");
 
int i915_disable_power_well __read_mostly = 1;
module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
MODULE_PARM_DESC(disable_power_well,
		 "Disable the power well when possible (default: true)");
 
int i915_enable_ips __read_mostly = 1;
module_param_named(enable_ips, i915_enable_ips, int, 0600);
MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
 
bool i915_fastboot __read_mostly = 0;
module_param_named(fastboot, i915_fastboot, bool, 0600);
MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "
		 "(default: false)");
 
int i915_enable_pc8 __read_mostly = 0;
module_param_named(enable_pc8, i915_enable_pc8, int, 0600);
MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)");
 
int i915_pc8_timeout __read_mostly = 5000;
module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600);
MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)");
 
bool i915_prefault_disable __read_mostly;
module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);
MODULE_PARM_DESC(prefault_disable,
		"Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
 
static struct drm_driver driver;
extern int intel_agp_enabled;
 
#define PCI_VENDOR_ID_INTEL        0x8086
 
 
static const struct intel_device_info intel_i915g_info = {
	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.ring_mask = RENDER_RING,
};
static const struct intel_device_info intel_i915gm_info = {
	.gen = 3, .is_mobile = 1, .num_pipes = 2,
	.cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.supports_tv = 1,
	.has_fbc = 1,
	.ring_mask = RENDER_RING,
};
static const struct intel_device_info intel_i945g_info = {
	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.ring_mask = RENDER_RING,
};
static const struct intel_device_info intel_i945gm_info = {
	.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
	.has_hotplug = 1, .cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.supports_tv = 1,
	.has_fbc = 1,
	.ring_mask = RENDER_RING,
};
 
static const struct intel_device_info intel_i965g_info = {
	.gen = 4, .is_broadwater = 1, .num_pipes = 2,
	.has_hotplug = 1,
	.has_overlay = 1,
	.ring_mask = RENDER_RING,
};
 
static const struct intel_device_info intel_i965gm_info = {
	.gen = 4, .is_crestline = 1, .num_pipes = 2,
	.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
	.has_overlay = 1,
	.supports_tv = 1,
	.ring_mask = RENDER_RING,
};
 
static const struct intel_device_info intel_g33_info = {
	.gen = 3, .is_g33 = 1, .num_pipes = 2,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.has_overlay = 1,
	.ring_mask = RENDER_RING,
};
 
static const struct intel_device_info intel_g45_info = {
	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
	.has_pipe_cxsr = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING,
};
 
static const struct intel_device_info intel_gm45_info = {
	.gen = 4, .is_g4x = 1, .num_pipes = 2,
	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
	.has_pipe_cxsr = 1, .has_hotplug = 1,
	.supports_tv = 1,
	.ring_mask = RENDER_RING | BSD_RING,
};
 
static const struct intel_device_info intel_pineview_info = {
	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.has_overlay = 1,
};
 
static const struct intel_device_info intel_ironlake_d_info = {
	.gen = 5, .num_pipes = 2,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING,
};
 
static const struct intel_device_info intel_ironlake_m_info = {
	.gen = 5, .is_mobile = 1, .num_pipes = 2,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.has_fbc = 1,
	.ring_mask = RENDER_RING | BSD_RING,
};
 
static const struct intel_device_info intel_sandybridge_d_info = {
	.gen = 6, .num_pipes = 2,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.has_fbc = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
	.has_llc = 1,
 
};
 
static const struct intel_device_info intel_sandybridge_m_info = {
	.gen = 6, .is_mobile = 1, .num_pipes = 2,
	.need_gfx_hws = 1, .has_hotplug = 1,
    .has_fbc      = 1,
 
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
	.has_llc = 1,
 
};
 
#define GEN7_FEATURES  \
	.gen = 7, .num_pipes = 3, \
	.need_gfx_hws = 1, .has_hotplug = 1, \
	.has_fbc = 1, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
	.has_llc = 1
 
 
static const struct intel_device_info intel_ivybridge_d_info = {
	GEN7_FEATURES,
	.is_ivybridge = 1,
};
 
static const struct intel_device_info intel_ivybridge_m_info = {
	GEN7_FEATURES,
	.is_ivybridge = 1,
	.is_mobile = 1,
 
};
 
static const struct intel_device_info intel_ivybridge_q_info = {
	GEN7_FEATURES,
	.is_ivybridge = 1,
	.num_pipes = 0, /* legal, last one wins */
};
 
static const struct intel_device_info intel_valleyview_m_info = {
	GEN7_FEATURES,
	.is_mobile = 1,
	.num_pipes = 2,
	.is_valleyview = 1,
	.display_mmio_offset = VLV_DISPLAY_BASE,
	.has_fbc = 0, /* legal, last one wins */
	.has_llc = 0, /* legal, last one wins */
};
 
static const struct intel_device_info intel_valleyview_d_info = {
	GEN7_FEATURES,
	.num_pipes = 2,
	.is_valleyview = 1,
	.display_mmio_offset = VLV_DISPLAY_BASE,
	.has_fbc = 0, /* legal, last one wins */
	.has_llc = 0, /* legal, last one wins */
};
 
static const struct intel_device_info intel_haswell_d_info = {
	GEN7_FEATURES,
	.is_haswell = 1,
	.has_ddi = 1,
	.has_fpga_dbg = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
};
 
static const struct intel_device_info intel_haswell_m_info = {
	GEN7_FEATURES,
	.is_haswell = 1,
	.is_mobile = 1,
	.has_ddi = 1,
	.has_fpga_dbg = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
};
 
static const struct intel_device_info intel_broadwell_d_info = {
	.gen = 8, .num_pipes = 3,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.has_llc = 1,
	.has_ddi = 1,
};
 
static const struct intel_device_info intel_broadwell_m_info = {
	.gen = 8, .is_mobile = 1, .num_pipes = 3,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.has_llc = 1,
	.has_ddi = 1,
};
 
/*
 * Make sure any device matches here are from most specific to most
 * general.  For example, since the Quanta match is based on the subsystem
 * and subvendor IDs, we need it to come before the more general IVB
 * PCI ID matches, otherwise we'll use the wrong info struct above.
 */
#define INTEL_PCI_IDS \
	INTEL_I915G_IDS(&intel_i915g_info),	\
	INTEL_I915GM_IDS(&intel_i915gm_info),	\
	INTEL_I945G_IDS(&intel_i945g_info),	\
	INTEL_I945GM_IDS(&intel_i945gm_info),	\
	INTEL_I965G_IDS(&intel_i965g_info),	\
	INTEL_G33_IDS(&intel_g33_info),		\
	INTEL_I965GM_IDS(&intel_i965gm_info),	\
	INTEL_GM45_IDS(&intel_gm45_info), 	\
	INTEL_G45_IDS(&intel_g45_info), 	\
	INTEL_PINEVIEW_IDS(&intel_pineview_info),	\
	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),	\
	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),	\
	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),	\
	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),	\
	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),	\
	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),	\
	INTEL_HSW_D_IDS(&intel_haswell_d_info), \
	INTEL_HSW_M_IDS(&intel_haswell_m_info), \
	INTEL_VLV_M_IDS(&intel_valleyview_m_info),	\
	INTEL_VLV_D_IDS(&intel_valleyview_d_info),	\
	INTEL_BDW_M_IDS(&intel_broadwell_m_info),	\
	INTEL_BDW_D_IDS(&intel_broadwell_d_info)
 
static const struct pci_device_id pciidlist[] = {       /* aka */
	INTEL_PCI_IDS,
    {0, 0, 0}
};
 
#define INTEL_PCH_DEVICE_ID_MASK        0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE	0x8c00
 
void intel_detect_pch(struct drm_device *dev)
{
    struct drm_i915_private *dev_priv = dev->dev_private;
    struct pci_dev *pch;
 
	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
	 * (which really amounts to a PCH but no South Display).
	 */
	if (INTEL_INFO(dev)->num_pipes == 0) {
		dev_priv->pch_type = PCH_NOP;
		return;
	}
 
    /*
     * The reason to probe ISA bridge instead of Dev31:Fun0 is to
     * make graphics device passthrough work easy for VMM, that only
     * need to expose ISA bridge to let driver know the real hardware
     * underneath. This is a requirement from virtualization team.
	 *
	 * In some virtualized environments (e.g. XEN), there is irrelevant
	 * ISA bridge in the system. To work reliably, we should scan trhough
	 * all the ISA bridge devices and check for the first match, instead
	 * of only checking the first one.
     */
    pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
	while (pch) {
		struct pci_dev *curr = pch;
        if (pch->vendor == PCI_VENDOR_ID_INTEL) {
			unsigned short id;
            id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
			dev_priv->pch_id = id;
 
            if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
                dev_priv->pch_type = PCH_IBX;
                DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
				WARN_ON(!IS_GEN5(dev));
            } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
                dev_priv->pch_type = PCH_CPT;
                DRM_DEBUG_KMS("Found CougarPoint PCH\n");
				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
            } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
                /* PantherPoint is CPT compatible */
                dev_priv->pch_type = PCH_CPT;
				DRM_DEBUG_KMS("Found PantherPoint PCH\n");
				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
				WARN_ON(!IS_HASWELL(dev));
				WARN_ON(IS_ULT(dev));
			} else if (IS_BROADWELL(dev)) {
				dev_priv->pch_type = PCH_LPT;
				dev_priv->pch_id =
					INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
				DRM_DEBUG_KMS("This is Broadwell, assuming "
					      "LynxPoint LP PCH\n");
			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
				WARN_ON(!IS_HASWELL(dev));
				WARN_ON(!IS_ULT(dev));
			} else {
				goto check_next;
            }
			break;
        }
check_next:
		pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr);
//       pci_dev_put(curr);
    }
	if (!pch)
		DRM_DEBUG_KMS("No PCH found?\n");
}
 
bool i915_semaphore_is_enabled(struct drm_device *dev)
{
	if (INTEL_INFO(dev)->gen < 6)
		return false;
 
	/* Until we get further testing... */
	if (IS_GEN8(dev)) {
		WARN_ON(!i915_preliminary_hw_support);
		return false;
	}
 
	if (i915_semaphores >= 0)
		return i915_semaphores;
 
#ifdef CONFIG_INTEL_IOMMU
	/* Enable semaphores on SNB when IO remapping is off */
	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
		return false;
#endif
 
	return true;
}
 
#if 0
static int i915_drm_freeze(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
 
	intel_runtime_pm_get(dev_priv);
 
	/* ignore lid events during suspend */
	mutex_lock(&dev_priv->modeset_restore_lock);
	dev_priv->modeset_restore = MODESET_SUSPENDED;
	mutex_unlock(&dev_priv->modeset_restore_lock);
 
	/* We do a lot of poking in a lot of registers, make sure they work
	 * properly. */
	hsw_disable_package_c8(dev_priv);
	intel_display_set_init_power(dev, true);
 
	drm_kms_helper_poll_disable(dev);
 
	pci_save_state(dev->pdev);
 
	/* If KMS is active, we do the leavevt stuff here */
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		int error;
 
 
 
		error = i915_gem_suspend(dev);
		if (error) {
			dev_err(&dev->pdev->dev,
				"GEM idle failed, resume might fail\n");
			return error;
		}
 
		cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 
		drm_irq_uninstall(dev);
		dev_priv->enable_hotplug_processing = false;
		/*
		 * Disable CRTCs directly since we want to preserve sw state
		 * for _thaw.
		 */
		mutex_lock(&dev->mode_config.mutex);
		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
			dev_priv->display.crtc_disable(crtc);
		mutex_unlock(&dev->mode_config.mutex);
 
		intel_modeset_suspend_hw(dev);
	}
 
	i915_gem_suspend_gtt_mappings(dev);
 
	i915_save_state(dev);
 
	intel_opregion_fini(dev);
 
	console_lock();
	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
	console_unlock();
 
	return 0;
}
 
int i915_suspend(struct drm_device *dev, pm_message_t state)
{
	int error;
 
	if (!dev || !dev->dev_private) {
		DRM_ERROR("dev: %p\n", dev);
		DRM_ERROR("DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}
 
	if (state.event == PM_EVENT_PRETHAW)
		return 0;
 
 
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
 
	error = i915_drm_freeze(dev);
	if (error)
		return error;
 
	if (state.event == PM_EVENT_SUSPEND) {
		/* Shut down the device */
		pci_disable_device(dev->pdev);
		pci_set_power_state(dev->pdev, PCI_D3hot);
	}
 
	return 0;
}
 
void intel_console_resume(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private,
			     console_resume_work);
	struct drm_device *dev = dev_priv->dev;
 
	console_lock();
	intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
	console_unlock();
}
 
static void intel_resume_hotplug(struct drm_device *dev)
{
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *encoder;
 
	mutex_lock(&mode_config->mutex);
	DRM_DEBUG_KMS("running encoder hotplug functions\n");
 
	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
		if (encoder->hot_plug)
			encoder->hot_plug(encoder);
 
	mutex_unlock(&mode_config->mutex);
 
	/* Just fire off a uevent and let userspace tell us what to do */
	drm_helper_hpd_irq_event(dev);
}
 
static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int error = 0;
 
	intel_uncore_early_sanitize(dev);
 
	intel_uncore_sanitize(dev);
 
	if (drm_core_check_feature(dev, DRIVER_MODESET) &&
	    restore_gtt_mappings) {
		mutex_lock(&dev->struct_mutex);
		i915_gem_restore_gtt_mappings(dev);
		mutex_unlock(&dev->struct_mutex);
	}
 
	intel_power_domains_init_hw(dev);
 
	i915_restore_state(dev);
	intel_opregion_setup(dev);
 
	/* KMS EnterVT equivalent */
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		intel_init_pch_refclk(dev);
 
		mutex_lock(&dev->struct_mutex);
 
		error = i915_gem_init_hw(dev);
		mutex_unlock(&dev->struct_mutex);
 
		/* We need working interrupts for modeset enabling ... */
		drm_irq_install(dev);
 
		intel_modeset_init_hw(dev);
 
		drm_modeset_lock_all(dev);
		drm_mode_config_reset(dev);
		intel_modeset_setup_hw_state(dev, true);
		drm_modeset_unlock_all(dev);
 
		/*
		 * ... but also need to make sure that hotplug processing
		 * doesn't cause havoc. Like in the driver load code we don't
		 * bother with the tiny race here where we might loose hotplug
		 * notifications.
		 * */
		intel_hpd_init(dev);
		dev_priv->enable_hotplug_processing = true;
		/* Config may have changed between suspend and resume */
		intel_resume_hotplug(dev);
	}
 
	intel_opregion_init(dev);
 
	/*
	 * The console lock can be pretty contented on resume due
	 * to all the printk activity.  Try to keep it out of the hot
	 * path of resume if possible.
	 */
	if (console_trylock()) {
		intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
		console_unlock();
	} else {
		schedule_work(&dev_priv->console_resume_work);
	}
 
	/* Undo what we did at i915_drm_freeze so the refcount goes back to the
	 * expected level. */
	hsw_enable_package_c8(dev_priv);
 
	mutex_lock(&dev_priv->modeset_restore_lock);
	dev_priv->modeset_restore = MODESET_DONE;
	mutex_unlock(&dev_priv->modeset_restore_lock);
 
	intel_runtime_pm_put(dev_priv);
	return error;
}
 
static int i915_drm_thaw(struct drm_device *dev)
{
 
 
 
 
	if (drm_core_check_feature(dev, DRIVER_MODESET))
 
 
 
 
		i915_check_and_clear_faults(dev);
 
 
 
	return __i915_drm_thaw(dev, true);
}
 
int i915_resume(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;
 
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
 
	if (pci_enable_device(dev->pdev))
		return -EIO;
 
	pci_set_master(dev->pdev);
 
 
 
	/*
	 * Platforms with opregion should have sane BIOS, older ones (gen3 and
	 * earlier) need to restore the GTT mappings since the BIOS might clear
	 * all our scratch PTEs.
 
	 */
 
 
 
 
 
 
	ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
	if (ret)
		return ret;
 
	drm_kms_helper_poll_enable(dev);
	return 0;
}
 
/**
 * i915_reset - reset chip after a hang
 * @dev: drm device to reset
 *
 * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 * reset or otherwise an error code.
 *
 * Procedure is fairly simple:
 *   - reset the chip using the reset reg
 *   - re-init context state
 *   - re-init hardware status page
 *   - re-init ring buffer
 *   - re-init interrupt state
 *   - re-init display
 */
int i915_reset(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	bool simulated;
	int ret;
 
	if (!i915_try_reset)
		return 0;
 
	mutex_lock(&dev->struct_mutex);
 
	i915_gem_reset(dev);
 
	simulated = dev_priv->gpu_error.stop_rings != 0;
 
 
 
 
 
		ret = intel_gpu_reset(dev);
 
		/* Also reset the gpu hangman. */
		if (simulated) {
			DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
			dev_priv->gpu_error.stop_rings = 0;
			if (ret == -ENODEV) {
			DRM_INFO("Reset not implemented, but ignoring "
					  "error for simulated gpu hangs\n");
				ret = 0;
			}
 
 
	}
 
	if (ret) {
		DRM_ERROR("Failed to reset chip: %i\n", ret);
		mutex_unlock(&dev->struct_mutex);
		return ret;
	}
 
	/* Ok, now get things going again... */
 
	/*
	 * Everything depends on having the GTT running, so we need to start
	 * there.  Fortunately we don't need to do this unless we reset the
	 * chip at a PCI level.
	 *
	 * Next we need to restore the context, but we don't use those
	 * yet either...
	 *
	 * Ring buffer needs to be re-initialized in the KMS case, or if X
	 * was running at the time of the reset (i.e. we weren't VT
	 * switched away).
	 */
	if (drm_core_check_feature(dev, DRIVER_MODESET) ||
			!dev_priv->ums.mm_suspended) {
 
 
 
		dev_priv->ums.mm_suspended = 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
		ret = i915_gem_init_hw(dev);
		mutex_unlock(&dev->struct_mutex);
		if (ret) {
			DRM_ERROR("Failed hw init on reset %d\n", ret);
			return ret;
		}
 
		drm_irq_uninstall(dev);
		drm_irq_install(dev);
		intel_hpd_init(dev);
	} else {
		mutex_unlock(&dev->struct_mutex);
	}
 
	return 0;
}
 
static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	struct intel_device_info *intel_info =
		(struct intel_device_info *) ent->driver_data;
 
	if (IS_PRELIMINARY_HW(intel_info) && !i915_preliminary_hw_support) {
		DRM_INFO("This hardware requires preliminary hardware support.\n"
			 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
		return -ENODEV;
	}
 
	/* Only bind to function 0 of the device. Early generations
	 * used function 1 as a placeholder for multi-head. This causes
	 * us confusion instead, especially on the systems where both
	 * functions have the same PCI-ID!
	 */
	if (PCI_FUNC(pdev->devfn))
		return -ENODEV;
 
	/* We've managed to ship a kms-enabled ddx that shipped with an XvMC
	 * implementation for gen3 (and only gen3) that used legacy drm maps
	 * (gasp!) to share buffers between X and the client. Hence we need to
	 * keep around the fake agp stuff for gen3, even when kms is enabled. */
	if (intel_info->gen != 3) {
		driver.driver_features &=
			~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
	} else if (!intel_agp_enabled) {
		DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
		return -ENODEV;
	}
 
	return drm_get_pci_dev(pdev, ent, &driver);
}
 
static void
i915_pci_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
 
	drm_put_dev(dev);
}
 
static int i915_pm_suspend(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);
	int error;
 
	if (!drm_dev || !drm_dev->dev_private) {
		dev_err(dev, "DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}
 
	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
 
	error = i915_drm_freeze(drm_dev);
	if (error)
		return error;
 
	pci_disable_device(pdev);
	pci_set_power_state(pdev, PCI_D3hot);
 
	return 0;
}
 
static int i915_pm_resume(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);
 
	return i915_resume(drm_dev);
}
 
static int i915_pm_freeze(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);
 
	if (!drm_dev || !drm_dev->dev_private) {
		dev_err(dev, "DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}
 
	return i915_drm_freeze(drm_dev);
}
 
static int i915_pm_thaw(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);
 
	return i915_drm_thaw(drm_dev);
}
 
static int i915_pm_poweroff(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);
 
	return i915_drm_freeze(drm_dev);
}
 
 
#endif
 
static struct drm_driver driver = {
    /* Don't use MTRRs here; the Xserver or userspace app should
     * deal with them for Intel hardware.
     */
    .driver_features =
	    DRIVER_USE_AGP |
	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
	    DRIVER_RENDER,
    .load = i915_driver_load,
//    .unload = i915_driver_unload,
      .open = i915_driver_open,
//    .lastclose = i915_driver_lastclose,
//    .preclose = i915_driver_preclose,
//    .postclose = i915_driver_postclose,
 
    /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
//    .suspend = i915_suspend,
//    .resume = i915_resume,
 
//    .device_is_agp = i915_driver_device_is_agp,
//    .master_create = i915_master_create,
//    .master_destroy = i915_master_destroy,
#if defined(CONFIG_DEBUG_FS)
	.debugfs_init = i915_debugfs_init,
	.debugfs_cleanup = i915_debugfs_cleanup,
#endif
 
    .gem_free_object = i915_gem_free_object,
 
//    .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
//    .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
//    .gem_prime_export = i915_gem_prime_export,
//    .gem_prime_import = i915_gem_prime_import,
 
//    .dumb_create = i915_gem_dumb_create,
//    .dumb_map_offset = i915_gem_mmap_gtt,
//    .dumb_destroy = i915_gem_dumb_destroy,
//    .ioctls = i915_ioctls,
//    .fops = &i915_driver_fops,
//    .name = DRIVER_NAME,
//    .desc = DRIVER_DESC,
//    .date = DRIVER_DATE,
//    .major = DRIVER_MAJOR,
//    .minor = DRIVER_MINOR,
//    .patchlevel = DRIVER_PATCHLEVEL,
};
 
 
 
 
int i915_init(void)
{
    static pci_dev_t device;
    const struct pci_device_id  *ent;
    int  err;
 
    ent = find_pci_device(&device, pciidlist);
    if( unlikely(ent == NULL) )
    {
        dbgprintf("device not found\n");
        return -ENODEV;
    };
 
    drm_core_init();
 
    DRM_INFO("device %x:%x\n", device.pci_dev.vendor,
                                device.pci_dev.device);
 
    driver.driver_features |= DRIVER_MODESET;
 
    err = drm_get_pci_dev(&device.pci_dev, ent, &driver);
 
    return err;
}

Rev 4398	Rev 4560
1	/* i915_drv.c -- i830,i845,i855,i865,i915 driver -- linux-c --	1	/* i915_drv.c -- i830,i845,i855,i865,i915 driver -- linux-c --
2	*/	2	*/
3	/*	3	/*
4	*	4	*
5	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.	5	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6	* All Rights Reserved.	6	* All Rights Reserved.
7	*	7	*
8	* Permission is hereby granted, free of charge, to any person obtaining a	8	* Permission is hereby granted, free of charge, to any person obtaining a
9	* copy of this software and associated documentation files (the	9	* copy of this software and associated documentation files (the
10	* "Software"), to deal in the Software without restriction, including	10	* "Software"), to deal in the Software without restriction, including
11	* without limitation the rights to use, copy, modify, merge, publish,	11	* without limitation the rights to use, copy, modify, merge, publish,
12	* distribute, sub license, and/or sell copies of the Software, and to	12	* distribute, sub license, and/or sell copies of the Software, and to
13	* permit persons to whom the Software is furnished to do so, subject to	13	* permit persons to whom the Software is furnished to do so, subject to
14	* the following conditions:	14	* the following conditions:
15	*	15	*
16	* The above copyright notice and this permission notice (including the	16	* The above copyright notice and this permission notice (including the
17	* next paragraph) shall be included in all copies or substantial portions	17	* next paragraph) shall be included in all copies or substantial portions
18	* of the Software.	18	* of the Software.
19	*	19	*
20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS	20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF	21	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.	22	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR	23	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,	24	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE	25	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.	26	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27	*	27	*
28	*/	28	*/
29		29
30	//#include	30	//#include
31	#include	31	#include
32	#include	32	#include
33	#include "i915_drv.h"	33	#include "i915_drv.h"
34	#include "i915_trace.h"	34	#include "i915_trace.h"
35	#include "intel_drv.h"	35	#include "intel_drv.h"
36		36
37	#include	37	#include
38	#include	38	#include
39	#include	39	#include
40	#include	40	#include
41		41
42	#include	42	#include
43		43
44	#include	44	#include
45		45
46	#define __read_mostly	46	#define __read_mostly
47		47
48	int init_display_kms(struct drm_device *dev);	48	int init_display_kms(struct drm_device *dev);
49		49
50	static int i915_modeset __read_mostly = 1;	50	static int i915_modeset __read_mostly = 1;
51	module_param_named(modeset, i915_modeset, int, 0400);	51	module_param_named(modeset, i915_modeset, int, 0400);
52	MODULE_PARM_DESC(modeset,	52	MODULE_PARM_DESC(modeset,
53	"Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "	53	"Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
54	"1=on, -1=force vga console preference [default])");	54	"1=on, -1=force vga console preference [default])");
55		55
56	unsigned int i915_fbpercrtc __always_unused = 0;	56	unsigned int i915_fbpercrtc __always_unused = 0;
57	module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);	57	module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
58		58
59	int i915_panel_ignore_lid __read_mostly = 1;	59	int i915_panel_ignore_lid __read_mostly = 1;
60	module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);	60	module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
61	MODULE_PARM_DESC(panel_ignore_lid,	61	MODULE_PARM_DESC(panel_ignore_lid,
62	"Override lid status (0=autodetect, 1=autodetect disabled [default], "	62	"Override lid status (0=autodetect, 1=autodetect disabled [default], "
63	"-1=force lid closed, -2=force lid open)");	63	"-1=force lid closed, -2=force lid open)");
64		64
65	unsigned int i915_powersave __read_mostly = 0;	65	unsigned int i915_powersave __read_mostly = 1;
66	module_param_named(powersave, i915_powersave, int, 0600);	66	module_param_named(powersave, i915_powersave, int, 0600);
67	MODULE_PARM_DESC(powersave,	67	MODULE_PARM_DESC(powersave,
68	"Enable powersavings, fbc, downclocking, etc. (default: true)");	68	"Enable powersavings, fbc, downclocking, etc. (default: true)");
69		69
70	int i915_semaphores __read_mostly = -1;	70	int i915_semaphores __read_mostly = -1;
71	module_param_named(semaphores, i915_semaphores, int, 0600);	71	module_param_named(semaphores, i915_semaphores, int, 0400);
72	MODULE_PARM_DESC(semaphores,	72	MODULE_PARM_DESC(semaphores,
73	"Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");	73	"Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
74		74
75	int i915_enable_rc6 __read_mostly = 0;	75	int i915_enable_rc6 __read_mostly = -1;
76	module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);	76	module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
77	MODULE_PARM_DESC(i915_enable_rc6,	77	MODULE_PARM_DESC(i915_enable_rc6,
78	"Enable power-saving render C-state 6. "	78	"Enable power-saving render C-state 6. "
79	"Different stages can be selected via bitmask values "	79	"Different stages can be selected via bitmask values "
80	"(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "	80	"(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
81	"For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "	81	"For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
82	"default: -1 (use per-chip default)");	82	"default: -1 (use per-chip default)");
83		83
84	int i915_enable_fbc __read_mostly = 0;	84	int i915_enable_fbc __read_mostly = -1;
85	module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);	85	module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
86	MODULE_PARM_DESC(i915_enable_fbc,	86	MODULE_PARM_DESC(i915_enable_fbc,
87	"Enable frame buffer compression for power savings "	87	"Enable frame buffer compression for power savings "
88	"(default: -1 (use per-chip default))");	88	"(default: -1 (use per-chip default))");
89		89
90	unsigned int i915_lvds_downclock __read_mostly = 0;	90	unsigned int i915_lvds_downclock __read_mostly = 0;
91	module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);	91	module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
92	MODULE_PARM_DESC(lvds_downclock,	92	MODULE_PARM_DESC(lvds_downclock,
93	"Use panel (LVDS/eDP) downclocking for power savings "	93	"Use panel (LVDS/eDP) downclocking for power savings "
94	"(default: false)");	94	"(default: false)");
95		95
96	int i915_lvds_channel_mode __read_mostly;	96	int i915_lvds_channel_mode __read_mostly;
97	module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);	97	module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
98	MODULE_PARM_DESC(lvds_channel_mode,	98	MODULE_PARM_DESC(lvds_channel_mode,
99	"Specify LVDS channel mode "	99	"Specify LVDS channel mode "
100	"(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");	100	"(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
101		101
102	int i915_panel_use_ssc __read_mostly = -1;	102	int i915_panel_use_ssc __read_mostly = -1;
103	module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);	103	module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
104	MODULE_PARM_DESC(lvds_use_ssc,	104	MODULE_PARM_DESC(lvds_use_ssc,
105	"Use Spread Spectrum Clock with panels [LVDS/eDP] "	105	"Use Spread Spectrum Clock with panels [LVDS/eDP] "
106	"(default: auto from VBT)");	106	"(default: auto from VBT)");
107		107
108	int i915_vbt_sdvo_panel_type __read_mostly = -1;	108	int i915_vbt_sdvo_panel_type __read_mostly = -1;
109	module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);	109	module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
110	MODULE_PARM_DESC(vbt_sdvo_panel_type,	110	MODULE_PARM_DESC(vbt_sdvo_panel_type,
111	"Override/Ignore selection of SDVO panel mode in the VBT "	111	"Override/Ignore selection of SDVO panel mode in the VBT "
112	"(-2=ignore, -1=auto [default], index in VBT BIOS table)");	112	"(-2=ignore, -1=auto [default], index in VBT BIOS table)");
113		113
114	static bool i915_try_reset __read_mostly = true;	114	static bool i915_try_reset __read_mostly = true;
115	module_param_named(reset, i915_try_reset, bool, 0600);	115	module_param_named(reset, i915_try_reset, bool, 0600);
116	MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");	116	MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
117		117
118	bool i915_enable_hangcheck __read_mostly = false;	118	bool i915_enable_hangcheck __read_mostly = false;
119	module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);	119	module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
120	MODULE_PARM_DESC(enable_hangcheck,	120	MODULE_PARM_DESC(enable_hangcheck,
121	"Periodically check GPU activity for detecting hangs. "	121	"Periodically check GPU activity for detecting hangs. "
122	"WARNING: Disabling this can cause system wide hangs. "	122	"WARNING: Disabling this can cause system wide hangs. "
123	"(default: true)");	123	"(default: true)");
124		124
125	int i915_enable_ppgtt __read_mostly = 0;	125	int i915_enable_ppgtt __read_mostly = -1;
126	module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);	126	module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0400);
127	MODULE_PARM_DESC(i915_enable_ppgtt,	127	MODULE_PARM_DESC(i915_enable_ppgtt,
128	"Enable PPGTT (default: true)");	128	"Enable PPGTT (default: true)");
129		129
130	int i915_enable_psr __read_mostly = 0;	130	int i915_enable_psr __read_mostly = 0;
131	module_param_named(enable_psr, i915_enable_psr, int, 0600);	131	module_param_named(enable_psr, i915_enable_psr, int, 0600);
132	MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");	132	MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
133		133
134	unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT);	134	unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT);
135	module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);	135	module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
136	MODULE_PARM_DESC(preliminary_hw_support,	136	MODULE_PARM_DESC(preliminary_hw_support,
137	"Enable preliminary hardware support.");	137	"Enable preliminary hardware support.");
138		138
139	int i915_disable_power_well __read_mostly = 1;	139	int i915_disable_power_well __read_mostly = 1;
140	module_param_named(disable_power_well, i915_disable_power_well, int, 0600);	140	module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
141	MODULE_PARM_DESC(disable_power_well,	141	MODULE_PARM_DESC(disable_power_well,
142	"Disable the power well when possible (default: true)");	142	"Disable the power well when possible (default: true)");
143		143
144	int i915_enable_ips __read_mostly = 1;	144	int i915_enable_ips __read_mostly = 1;
145	module_param_named(enable_ips, i915_enable_ips, int, 0600);	145	module_param_named(enable_ips, i915_enable_ips, int, 0600);
146	MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");	146	MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
147		147
148	bool i915_fastboot __read_mostly = 0;	148	bool i915_fastboot __read_mostly = 0;
149	module_param_named(fastboot, i915_fastboot, bool, 0600);	149	module_param_named(fastboot, i915_fastboot, bool, 0600);
150	MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "	150	MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "
151	"(default: false)");	151	"(default: false)");
152		152
153	int i915_enable_pc8 __read_mostly = 0;	153	int i915_enable_pc8 __read_mostly = 0;
154	module_param_named(enable_pc8, i915_enable_pc8, int, 0600);	154	module_param_named(enable_pc8, i915_enable_pc8, int, 0600);
155	MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)");	155	MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)");
156		156
157	int i915_pc8_timeout __read_mostly = 5000;	157	int i915_pc8_timeout __read_mostly = 5000;
158	module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600);	158	module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600);
159	MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)");	159	MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)");
160		160
161	bool i915_prefault_disable __read_mostly;	161	bool i915_prefault_disable __read_mostly;
162	module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);	162	module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);
163	MODULE_PARM_DESC(prefault_disable,	163	MODULE_PARM_DESC(prefault_disable,
164	"Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");	164	"Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
165		165
166	static struct drm_driver driver;	166	static struct drm_driver driver;
167	extern int intel_agp_enabled;	167	extern int intel_agp_enabled;
168		168
169	#define PCI_VENDOR_ID_INTEL 0x8086	169	#define PCI_VENDOR_ID_INTEL 0x8086
170		170
171		171
172	static const struct intel_device_info intel_i915g_info = {	172	static const struct intel_device_info intel_i915g_info = {
173	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,	173	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
174	.has_overlay = 1, .overlay_needs_physical = 1,	174	.has_overlay = 1, .overlay_needs_physical = 1,
-		175	.ring_mask = RENDER_RING,
175	};	176	};
176	static const struct intel_device_info intel_i915gm_info = {	177	static const struct intel_device_info intel_i915gm_info = {
177	.gen = 3, .is_mobile = 1, .num_pipes = 2,	178	.gen = 3, .is_mobile = 1, .num_pipes = 2,
178	.cursor_needs_physical = 1,	179	.cursor_needs_physical = 1,
179	.has_overlay = 1, .overlay_needs_physical = 1,	180	.has_overlay = 1, .overlay_needs_physical = 1,
180	.supports_tv = 1,	181	.supports_tv = 1,
-		182	.has_fbc = 1,
-		183	.ring_mask = RENDER_RING,
181	};	184	};
182	static const struct intel_device_info intel_i945g_info = {	185	static const struct intel_device_info intel_i945g_info = {
183	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,	186	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
184	.has_overlay = 1, .overlay_needs_physical = 1,	187	.has_overlay = 1, .overlay_needs_physical = 1,
-		188	.ring_mask = RENDER_RING,
185	};	189	};
186	static const struct intel_device_info intel_i945gm_info = {	190	static const struct intel_device_info intel_i945gm_info = {
187	.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,	191	.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
188	.has_hotplug = 1, .cursor_needs_physical = 1,	192	.has_hotplug = 1, .cursor_needs_physical = 1,
189	.has_overlay = 1, .overlay_needs_physical = 1,	193	.has_overlay = 1, .overlay_needs_physical = 1,
190	.supports_tv = 1,	194	.supports_tv = 1,
-		195	.has_fbc = 1,
-		196	.ring_mask = RENDER_RING,
191	};	197	};
192		198
193	static const struct intel_device_info intel_i965g_info = {	199	static const struct intel_device_info intel_i965g_info = {
194	.gen = 4, .is_broadwater = 1, .num_pipes = 2,	200	.gen = 4, .is_broadwater = 1, .num_pipes = 2,
195	.has_hotplug = 1,	201	.has_hotplug = 1,
196	.has_overlay = 1,	202	.has_overlay = 1,
-		203	.ring_mask = RENDER_RING,
197	};	204	};
198		205
199	static const struct intel_device_info intel_i965gm_info = {	206	static const struct intel_device_info intel_i965gm_info = {
200	.gen = 4, .is_crestline = 1, .num_pipes = 2,	207	.gen = 4, .is_crestline = 1, .num_pipes = 2,
201	.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,	208	.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
202	.has_overlay = 1,	209	.has_overlay = 1,
203	.supports_tv = 1,	210	.supports_tv = 1,
-		211	.ring_mask = RENDER_RING,
204	};	212	};
205		213
206	static const struct intel_device_info intel_g33_info = {	214	static const struct intel_device_info intel_g33_info = {
207	.gen = 3, .is_g33 = 1, .num_pipes = 2,	215	.gen = 3, .is_g33 = 1, .num_pipes = 2,
208	.need_gfx_hws = 1, .has_hotplug = 1,	216	.need_gfx_hws = 1, .has_hotplug = 1,
209	.has_overlay = 1,	217	.has_overlay = 1,
-		218	.ring_mask = RENDER_RING,
210	};	219	};
211		220
212	static const struct intel_device_info intel_g45_info = {	221	static const struct intel_device_info intel_g45_info = {
213	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,	222	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
214	.has_pipe_cxsr = 1, .has_hotplug = 1,	223	.has_pipe_cxsr = 1, .has_hotplug = 1,
215	.has_bsd_ring = 1,	224	.ring_mask = RENDER_RING \| BSD_RING,
216	};	225	};
217		226
218	static const struct intel_device_info intel_gm45_info = {	227	static const struct intel_device_info intel_gm45_info = {
219	.gen = 4, .is_g4x = 1, .num_pipes = 2,	228	.gen = 4, .is_g4x = 1, .num_pipes = 2,
220	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,	229	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
221	.has_pipe_cxsr = 1, .has_hotplug = 1,	230	.has_pipe_cxsr = 1, .has_hotplug = 1,
222	.supports_tv = 1,	231	.supports_tv = 1,
223	.has_bsd_ring = 1,	232	.ring_mask = RENDER_RING \| BSD_RING,
224	};	233	};
225		234
226	static const struct intel_device_info intel_pineview_info = {	235	static const struct intel_device_info intel_pineview_info = {
227	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,	236	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
228	.need_gfx_hws = 1, .has_hotplug = 1,	237	.need_gfx_hws = 1, .has_hotplug = 1,
229	.has_overlay = 1,	238	.has_overlay = 1,
230	};	239	};
231		240
232	static const struct intel_device_info intel_ironlake_d_info = {	241	static const struct intel_device_info intel_ironlake_d_info = {
233	.gen = 5, .num_pipes = 2,	242	.gen = 5, .num_pipes = 2,
234	.need_gfx_hws = 1, .has_hotplug = 1,	243	.need_gfx_hws = 1, .has_hotplug = 1,
235	.has_bsd_ring = 1,	244	.ring_mask = RENDER_RING \| BSD_RING,
236	};	245	};
237		246
238	static const struct intel_device_info intel_ironlake_m_info = {	247	static const struct intel_device_info intel_ironlake_m_info = {
239	.gen = 5, .is_mobile = 1, .num_pipes = 2,	248	.gen = 5, .is_mobile = 1, .num_pipes = 2,
240	.need_gfx_hws = 1, .has_hotplug = 1,	249	.need_gfx_hws = 1, .has_hotplug = 1,
241	.has_fbc = 1,	250	.has_fbc = 1,
242	.has_bsd_ring = 1,	251	.ring_mask = RENDER_RING \| BSD_RING,
243	};	252	};
244		253
245	static const struct intel_device_info intel_sandybridge_d_info = {	254	static const struct intel_device_info intel_sandybridge_d_info = {
246	.gen = 6, .num_pipes = 2,	255	.gen = 6, .num_pipes = 2,
247	.need_gfx_hws = 1, .has_hotplug = 1,	256	.need_gfx_hws = 1, .has_hotplug = 1,
248	.has_bsd_ring = 1,	257	.has_fbc = 1,
249	.has_blt_ring = 1,	258	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING,
250	.has_llc = 1,	259	.has_llc = 1,
251	.has_force_wake = 1,	-
252	};	260	};
253		261
254	static const struct intel_device_info intel_sandybridge_m_info = {	262	static const struct intel_device_info intel_sandybridge_m_info = {
255	.gen = 6, .is_mobile = 1, .num_pipes = 2,	263	.gen = 6, .is_mobile = 1, .num_pipes = 2,
256	.need_gfx_hws = 1, .has_hotplug = 1,	264	.need_gfx_hws = 1, .has_hotplug = 1,
257	.has_fbc = 1,	265	.has_fbc = 1,
258	.has_bsd_ring = 1,	-
259	.has_blt_ring = 1,	266	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING,
260	.has_llc = 1,	267	.has_llc = 1,
261	.has_force_wake = 1,	-
262	};	268	};
263		269
264	#define GEN7_FEATURES \	270	#define GEN7_FEATURES \
265	.gen = 7, .num_pipes = 3, \	271	.gen = 7, .num_pipes = 3, \
266	.need_gfx_hws = 1, .has_hotplug = 1, \	272	.need_gfx_hws = 1, .has_hotplug = 1, \
267	.has_bsd_ring = 1, \	273	.has_fbc = 1, \
268	.has_blt_ring = 1, \	274	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING, \
269	.has_llc = 1, \	275	.has_llc = 1
270	.has_force_wake = 1	-
271		276
272	static const struct intel_device_info intel_ivybridge_d_info = {	277	static const struct intel_device_info intel_ivybridge_d_info = {
273	GEN7_FEATURES,	278	GEN7_FEATURES,
274	.is_ivybridge = 1,	279	.is_ivybridge = 1,
275	};	280	};
276		281
277	static const struct intel_device_info intel_ivybridge_m_info = {	282	static const struct intel_device_info intel_ivybridge_m_info = {
278	GEN7_FEATURES,	283	GEN7_FEATURES,
279	.is_ivybridge = 1,	284	.is_ivybridge = 1,
280	.is_mobile = 1,	285	.is_mobile = 1,
281	.has_fbc = 1,	-
282	};	286	};
283		287
284	static const struct intel_device_info intel_ivybridge_q_info = {	288	static const struct intel_device_info intel_ivybridge_q_info = {
285	GEN7_FEATURES,	289	GEN7_FEATURES,
286	.is_ivybridge = 1,	290	.is_ivybridge = 1,
287	.num_pipes = 0, /* legal, last one wins */	291	.num_pipes = 0, /* legal, last one wins */
288	};	292	};
289		293
290	static const struct intel_device_info intel_valleyview_m_info = {	294	static const struct intel_device_info intel_valleyview_m_info = {
291	GEN7_FEATURES,	295	GEN7_FEATURES,
292	.is_mobile = 1,	296	.is_mobile = 1,
293	.num_pipes = 2,	297	.num_pipes = 2,
294	.is_valleyview = 1,	298	.is_valleyview = 1,
295	.display_mmio_offset = VLV_DISPLAY_BASE,	299	.display_mmio_offset = VLV_DISPLAY_BASE,
-		300	.has_fbc = 0, /* legal, last one wins */
296	.has_llc = 0, /* legal, last one wins */	301	.has_llc = 0, /* legal, last one wins */
297	};	302	};
298		303
299	static const struct intel_device_info intel_valleyview_d_info = {	304	static const struct intel_device_info intel_valleyview_d_info = {
300	GEN7_FEATURES,	305	GEN7_FEATURES,
301	.num_pipes = 2,	306	.num_pipes = 2,
302	.is_valleyview = 1,	307	.is_valleyview = 1,
303	.display_mmio_offset = VLV_DISPLAY_BASE,	308	.display_mmio_offset = VLV_DISPLAY_BASE,
-		309	.has_fbc = 0, /* legal, last one wins */
304	.has_llc = 0, /* legal, last one wins */	310	.has_llc = 0, /* legal, last one wins */
305	};	311	};
306		312
307	static const struct intel_device_info intel_haswell_d_info = {	313	static const struct intel_device_info intel_haswell_d_info = {
308	GEN7_FEATURES,	314	GEN7_FEATURES,
309	.is_haswell = 1,	315	.is_haswell = 1,
310	.has_ddi = 1,	316	.has_ddi = 1,
311	.has_fpga_dbg = 1,	317	.has_fpga_dbg = 1,
312	.has_vebox_ring = 1,	318	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING,
313	};	319	};
314		320
315	static const struct intel_device_info intel_haswell_m_info = {	321	static const struct intel_device_info intel_haswell_m_info = {
316	GEN7_FEATURES,	322	GEN7_FEATURES,
317	.is_haswell = 1,	323	.is_haswell = 1,
318	.is_mobile = 1,	324	.is_mobile = 1,
319	.has_ddi = 1,	325	.has_ddi = 1,
320	.has_fpga_dbg = 1,	326	.has_fpga_dbg = 1,
-		327	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING,
-		328	};
-		329
-		330	static const struct intel_device_info intel_broadwell_d_info = {
-		331	.gen = 8, .num_pipes = 3,
-		332	.need_gfx_hws = 1, .has_hotplug = 1,
-		333	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING,
321	.has_fbc = 1,	334	.has_llc = 1,
-		335	.has_ddi = 1,
-		336	};
-		337
-		338	static const struct intel_device_info intel_broadwell_m_info = {
-		339	.gen = 8, .is_mobile = 1, .num_pipes = 3,
-		340	.need_gfx_hws = 1, .has_hotplug = 1,
-		341	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING,
-		342	.has_llc = 1,
322	.has_vebox_ring = 1,	343	.has_ddi = 1,
323	};	344	};
324		345
325	/*	346	/*
326	* Make sure any device matches here are from most specific to most	347	* Make sure any device matches here are from most specific to most
327	* general. For example, since the Quanta match is based on the subsystem	348	* general. For example, since the Quanta match is based on the subsystem
328	* and subvendor IDs, we need it to come before the more general IVB	349	* and subvendor IDs, we need it to come before the more general IVB
329	* PCI ID matches, otherwise we'll use the wrong info struct above.	350	* PCI ID matches, otherwise we'll use the wrong info struct above.
330	*/	351	*/
331	#define INTEL_PCI_IDS \	352	#define INTEL_PCI_IDS \
332	INTEL_I915G_IDS(&intel_i915g_info), \	353	INTEL_I915G_IDS(&intel_i915g_info), \
333	INTEL_I915GM_IDS(&intel_i915gm_info), \	354	INTEL_I915GM_IDS(&intel_i915gm_info), \
334	INTEL_I945G_IDS(&intel_i945g_info), \	355	INTEL_I945G_IDS(&intel_i945g_info), \
335	INTEL_I945GM_IDS(&intel_i945gm_info), \	356	INTEL_I945GM_IDS(&intel_i945gm_info), \
336	INTEL_I965G_IDS(&intel_i965g_info), \	357	INTEL_I965G_IDS(&intel_i965g_info), \
337	INTEL_G33_IDS(&intel_g33_info), \	358	INTEL_G33_IDS(&intel_g33_info), \
338	INTEL_I965GM_IDS(&intel_i965gm_info), \	359	INTEL_I965GM_IDS(&intel_i965gm_info), \
339	INTEL_GM45_IDS(&intel_gm45_info), \	360	INTEL_GM45_IDS(&intel_gm45_info), \
340	INTEL_G45_IDS(&intel_g45_info), \	361	INTEL_G45_IDS(&intel_g45_info), \
341	INTEL_PINEVIEW_IDS(&intel_pineview_info), \	362	INTEL_PINEVIEW_IDS(&intel_pineview_info), \
342	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \	363	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
343	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \	364	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
344	INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \	365	INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
345	INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \	366	INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
346	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \	367	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
347	INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \	368	INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
348	INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \	369	INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
349	INTEL_HSW_D_IDS(&intel_haswell_d_info), \	370	INTEL_HSW_D_IDS(&intel_haswell_d_info), \
350	INTEL_HSW_M_IDS(&intel_haswell_m_info), \	371	INTEL_HSW_M_IDS(&intel_haswell_m_info), \
351	INTEL_VLV_M_IDS(&intel_valleyview_m_info), \	372	INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
352	INTEL_VLV_D_IDS(&intel_valleyview_d_info)	373	INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
-		374	INTEL_BDW_M_IDS(&intel_broadwell_m_info), \
-		375	INTEL_BDW_D_IDS(&intel_broadwell_d_info)
353		376
354	static const struct pci_device_id pciidlist[] = { /* aka */	377	static const struct pci_device_id pciidlist[] = { /* aka */
355	INTEL_PCI_IDS,	378	INTEL_PCI_IDS,
356	{0, 0, 0}	379	{0, 0, 0}
357	};	380	};
358		381
359	#define INTEL_PCH_DEVICE_ID_MASK 0xff00	382	#define INTEL_PCH_DEVICE_ID_MASK 0xff00
360	#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00	383	#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
361	#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00	384	#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
362	#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00	385	#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
363	#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00	386	#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
364		387
365	void intel_detect_pch(struct drm_device *dev)	388	void intel_detect_pch(struct drm_device *dev)
366	{	389	{
367	struct drm_i915_private *dev_priv = dev->dev_private;	390	struct drm_i915_private *dev_priv = dev->dev_private;
368	struct pci_dev *pch;	391	struct pci_dev *pch;
369		392
370	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting	393	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
371	* (which really amounts to a PCH but no South Display).	394	* (which really amounts to a PCH but no South Display).
372	*/	395	*/
373	if (INTEL_INFO(dev)->num_pipes == 0) {	396	if (INTEL_INFO(dev)->num_pipes == 0) {
374	dev_priv->pch_type = PCH_NOP;	397	dev_priv->pch_type = PCH_NOP;
375	return;	398	return;
376	}	399	}
377		400
378	/*	401	/*
379	* The reason to probe ISA bridge instead of Dev31:Fun0 is to	402	* The reason to probe ISA bridge instead of Dev31:Fun0 is to
380	* make graphics device passthrough work easy for VMM, that only	403	* make graphics device passthrough work easy for VMM, that only
381	* need to expose ISA bridge to let driver know the real hardware	404	* need to expose ISA bridge to let driver know the real hardware
382	* underneath. This is a requirement from virtualization team.	405	* underneath. This is a requirement from virtualization team.
383	*	406	*
384	* In some virtualized environments (e.g. XEN), there is irrelevant	407	* In some virtualized environments (e.g. XEN), there is irrelevant
385	* ISA bridge in the system. To work reliably, we should scan trhough	408	* ISA bridge in the system. To work reliably, we should scan trhough
386	* all the ISA bridge devices and check for the first match, instead	409	* all the ISA bridge devices and check for the first match, instead
387	* of only checking the first one.	410	* of only checking the first one.
388	*/	411	*/
389	pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);	412	pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
390	while (pch) {	413	while (pch) {
391	struct pci_dev *curr = pch;	414	struct pci_dev *curr = pch;
392	if (pch->vendor == PCI_VENDOR_ID_INTEL) {	415	if (pch->vendor == PCI_VENDOR_ID_INTEL) {
393	unsigned short id;	416	unsigned short id;
394	id = pch->device & INTEL_PCH_DEVICE_ID_MASK;	417	id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
395	dev_priv->pch_id = id;	418	dev_priv->pch_id = id;
396		419
397	if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {	420	if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
398	dev_priv->pch_type = PCH_IBX;	421	dev_priv->pch_type = PCH_IBX;
399	DRM_DEBUG_KMS("Found Ibex Peak PCH\n");	422	DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
400	WARN_ON(!IS_GEN5(dev));	423	WARN_ON(!IS_GEN5(dev));
401	} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {	424	} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
402	dev_priv->pch_type = PCH_CPT;	425	dev_priv->pch_type = PCH_CPT;
403	DRM_DEBUG_KMS("Found CougarPoint PCH\n");	426	DRM_DEBUG_KMS("Found CougarPoint PCH\n");
404	WARN_ON(!(IS_GEN6(dev) \|\| IS_IVYBRIDGE(dev)));	427	WARN_ON(!(IS_GEN6(dev) \|\| IS_IVYBRIDGE(dev)));
405	} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {	428	} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
406	/* PantherPoint is CPT compatible */	429	/* PantherPoint is CPT compatible */
407	dev_priv->pch_type = PCH_CPT;	430	dev_priv->pch_type = PCH_CPT;
408	DRM_DEBUG_KMS("Found PatherPoint PCH\n");	431	DRM_DEBUG_KMS("Found PantherPoint PCH\n");
409	WARN_ON(!(IS_GEN6(dev) \|\| IS_IVYBRIDGE(dev)));	432	WARN_ON(!(IS_GEN6(dev) \|\| IS_IVYBRIDGE(dev)));
410	} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {	433	} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
411	dev_priv->pch_type = PCH_LPT;	434	dev_priv->pch_type = PCH_LPT;
412	DRM_DEBUG_KMS("Found LynxPoint PCH\n");	435	DRM_DEBUG_KMS("Found LynxPoint PCH\n");
413	WARN_ON(!IS_HASWELL(dev));	436	WARN_ON(!IS_HASWELL(dev));
414	WARN_ON(IS_ULT(dev));	437	WARN_ON(IS_ULT(dev));
-		438	} else if (IS_BROADWELL(dev)) {
-		439	dev_priv->pch_type = PCH_LPT;
-		440	dev_priv->pch_id =
-		441	INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
-		442	DRM_DEBUG_KMS("This is Broadwell, assuming "
-		443	"LynxPoint LP PCH\n");
415	} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {	444	} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
416	dev_priv->pch_type = PCH_LPT;	445	dev_priv->pch_type = PCH_LPT;
417	DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");	446	DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
418	WARN_ON(!IS_HASWELL(dev));	447	WARN_ON(!IS_HASWELL(dev));
419	WARN_ON(!IS_ULT(dev));	448	WARN_ON(!IS_ULT(dev));
420	} else {	449	} else {
421	goto check_next;	450	goto check_next;
422	}	451	}
423	break;	452	break;
424	}	453	}
425	check_next:	454	check_next:
426	pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr);	455	pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr);
427	// pci_dev_put(curr);	456	// pci_dev_put(curr);
428	}	457	}
429	if (!pch)	458	if (!pch)
430	DRM_DEBUG_KMS("No PCH found?\n");	459	DRM_DEBUG_KMS("No PCH found?\n");
431	}	460	}
432		461
433	bool i915_semaphore_is_enabled(struct drm_device *dev)	462	bool i915_semaphore_is_enabled(struct drm_device *dev)
434	{	463	{
435	if (INTEL_INFO(dev)->gen < 6)	464	if (INTEL_INFO(dev)->gen < 6)
436	return 0;	465	return false;
-		466
-		467	/* Until we get further testing... */
-		468	if (IS_GEN8(dev)) {
-		469	WARN_ON(!i915_preliminary_hw_support);
-		470	return false;
-		471	}
437		472
438	if (i915_semaphores >= 0)	473	if (i915_semaphores >= 0)
439	return i915_semaphores;	474	return i915_semaphores;
440		475
441	#ifdef CONFIG_INTEL_IOMMU	476	#ifdef CONFIG_INTEL_IOMMU
442	/* Enable semaphores on SNB when IO remapping is off */	477	/* Enable semaphores on SNB when IO remapping is off */
443	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)	478	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
444	return false;	479	return false;
445	#endif	480	#endif
446		481
447	return 1;	482	return true;
448	}	483	}
449		484
450	#if 0	485	#if 0
451	static int i915_drm_freeze(struct drm_device *dev)	486	static int i915_drm_freeze(struct drm_device *dev)
452	{	487	{
453	struct drm_i915_private *dev_priv = dev->dev_private;	488	struct drm_i915_private *dev_priv = dev->dev_private;
454	struct drm_crtc *crtc;	489	struct drm_crtc *crtc;
-		490
-		491	intel_runtime_pm_get(dev_priv);
455		492
456	/* ignore lid events during suspend */	493	/* ignore lid events during suspend */
457	mutex_lock(&dev_priv->modeset_restore_lock);	494	mutex_lock(&dev_priv->modeset_restore_lock);
458	dev_priv->modeset_restore = MODESET_SUSPENDED;	495	dev_priv->modeset_restore = MODESET_SUSPENDED;

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_drv.c – Rev 4398 → 4560