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Rev 3482 | Rev 3746 | ||
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Line 55... | Line 55... | ||
55 | module_param_named(modeset, i915_modeset, int, 0400); |
55 | module_param_named(modeset, i915_modeset, int, 0400); |
56 | MODULE_PARM_DESC(modeset, |
56 | MODULE_PARM_DESC(modeset, |
57 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " |
57 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " |
58 | "1=on, -1=force vga console preference [default])"); |
58 | "1=on, -1=force vga console preference [default])"); |
Line -... | Line 59... | ||
- | 59 | ||
- | 60 | unsigned int i915_fbpercrtc __always_unused = 0; |
|
Line 59... | Line 61... | ||
59 | 61 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
|
60 | 62 | ||
61 | int i915_panel_ignore_lid __read_mostly = 1; |
63 | int i915_panel_ignore_lid __read_mostly = 1; |
62 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
64 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
Line 122... | Line 124... | ||
122 | MODULE_PARM_DESC(enable_hangcheck, |
124 | MODULE_PARM_DESC(enable_hangcheck, |
123 | "Periodically check GPU activity for detecting hangs. " |
125 | "Periodically check GPU activity for detecting hangs. " |
124 | "WARNING: Disabling this can cause system wide hangs. " |
126 | "WARNING: Disabling this can cause system wide hangs. " |
125 | "(default: true)"); |
127 | "(default: true)"); |
Line 126... | Line 128... | ||
126 | 128 | ||
127 | int i915_enable_ppgtt __read_mostly = false; |
129 | int i915_enable_ppgtt __read_mostly = 0; |
128 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); |
130 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); |
129 | MODULE_PARM_DESC(i915_enable_ppgtt, |
131 | MODULE_PARM_DESC(i915_enable_ppgtt, |
Line 130... | Line 132... | ||
130 | "Enable PPGTT (default: true)"); |
132 | "Enable PPGTT (default: true)"); |
131 | 133 | ||
132 | unsigned int i915_preliminary_hw_support __read_mostly = true; |
134 | unsigned int i915_preliminary_hw_support __read_mostly = true; |
133 | module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600); |
135 | module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600); |
134 | MODULE_PARM_DESC(preliminary_hw_support, |
- | |
135 | "Enable preliminary hardware support. " |
- | |
Line 136... | Line 136... | ||
136 | "Enable Haswell and ValleyView Support. " |
136 | MODULE_PARM_DESC(preliminary_hw_support, |
137 | "(default: false)"); |
137 | "Enable preliminary hardware support. (default: false)"); |
138 | 138 | ||
139 | int i915_disable_power_well __read_mostly = 0; |
139 | int i915_disable_power_well __read_mostly = 0; |
Line 150... | Line 150... | ||
150 | .device = id, \ |
150 | .device = id, \ |
151 | .subvendor = PCI_ANY_ID, \ |
151 | .subvendor = PCI_ANY_ID, \ |
152 | .subdevice = PCI_ANY_ID, \ |
152 | .subdevice = PCI_ANY_ID, \ |
153 | .driver_data = (unsigned long) info } |
153 | .driver_data = (unsigned long) info } |
Line -... | Line 154... | ||
- | 154 | ||
- | 155 | #define INTEL_QUANTA_VGA_DEVICE(info) { \ |
|
- | 156 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ |
|
- | 157 | .class_mask = 0xff0000, \ |
|
- | 158 | .vendor = 0x8086, \ |
|
- | 159 | .device = 0x16a, \ |
|
- | 160 | .subvendor = 0x152d, \ |
|
- | 161 | .subdevice = 0x8990, \ |
|
Line 154... | Line 162... | ||
154 | 162 | .driver_data = (unsigned long) info } |
|
155 | 163 | ||
156 | static const struct intel_device_info intel_i915g_info = { |
164 | static const struct intel_device_info intel_i915g_info = { |
157 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
165 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
158 | .has_overlay = 1, .overlay_needs_physical = 1, |
166 | .has_overlay = 1, .overlay_needs_physical = 1, |
159 | }; |
167 | }; |
160 | static const struct intel_device_info intel_i915gm_info = { |
168 | static const struct intel_device_info intel_i915gm_info = { |
161 | .gen = 3, .is_mobile = 1, |
169 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
162 | .cursor_needs_physical = 1, |
170 | .cursor_needs_physical = 1, |
163 | .has_overlay = 1, .overlay_needs_physical = 1, |
171 | .has_overlay = 1, .overlay_needs_physical = 1, |
164 | .supports_tv = 1, |
172 | .supports_tv = 1, |
165 | }; |
173 | }; |
166 | static const struct intel_device_info intel_i945g_info = { |
174 | static const struct intel_device_info intel_i945g_info = { |
167 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
175 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
168 | .has_overlay = 1, .overlay_needs_physical = 1, |
176 | .has_overlay = 1, .overlay_needs_physical = 1, |
169 | }; |
177 | }; |
170 | static const struct intel_device_info intel_i945gm_info = { |
178 | static const struct intel_device_info intel_i945gm_info = { |
171 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
179 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
172 | .has_hotplug = 1, .cursor_needs_physical = 1, |
180 | .has_hotplug = 1, .cursor_needs_physical = 1, |
173 | .has_overlay = 1, .overlay_needs_physical = 1, |
181 | .has_overlay = 1, .overlay_needs_physical = 1, |
Line 174... | Line 182... | ||
174 | .supports_tv = 1, |
182 | .supports_tv = 1, |
175 | }; |
183 | }; |
176 | 184 | ||
177 | static const struct intel_device_info intel_i965g_info = { |
185 | static const struct intel_device_info intel_i965g_info = { |
178 | .gen = 4, .is_broadwater = 1, |
186 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
Line 179... | Line 187... | ||
179 | .has_hotplug = 1, |
187 | .has_hotplug = 1, |
180 | .has_overlay = 1, |
188 | .has_overlay = 1, |
181 | }; |
189 | }; |
182 | 190 | ||
183 | static const struct intel_device_info intel_i965gm_info = { |
191 | static const struct intel_device_info intel_i965gm_info = { |
184 | .gen = 4, .is_crestline = 1, |
192 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
Line 185... | Line 193... | ||
185 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
193 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
186 | .has_overlay = 1, |
194 | .has_overlay = 1, |
187 | .supports_tv = 1, |
195 | .supports_tv = 1, |
188 | }; |
196 | }; |
189 | 197 | ||
Line 190... | Line 198... | ||
190 | static const struct intel_device_info intel_g33_info = { |
198 | static const struct intel_device_info intel_g33_info = { |
191 | .gen = 3, .is_g33 = 1, |
199 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
192 | .need_gfx_hws = 1, .has_hotplug = 1, |
200 | .need_gfx_hws = 1, .has_hotplug = 1, |
193 | .has_overlay = 1, |
201 | .has_overlay = 1, |
194 | }; |
202 | }; |
Line 195... | Line 203... | ||
195 | 203 | ||
196 | static const struct intel_device_info intel_g45_info = { |
204 | static const struct intel_device_info intel_g45_info = { |
197 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
205 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
198 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
206 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
199 | .has_bsd_ring = 1, |
207 | .has_bsd_ring = 1, |
200 | }; |
208 | }; |
201 | 209 | ||
Line 202... | Line 210... | ||
202 | static const struct intel_device_info intel_gm45_info = { |
210 | static const struct intel_device_info intel_gm45_info = { |
203 | .gen = 4, .is_g4x = 1, |
211 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
204 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
212 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
205 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
213 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
206 | .supports_tv = 1, |
214 | .supports_tv = 1, |
Line 207... | Line 215... | ||
207 | .has_bsd_ring = 1, |
215 | .has_bsd_ring = 1, |
208 | }; |
216 | }; |
209 | 217 | ||
210 | static const struct intel_device_info intel_pineview_info = { |
218 | static const struct intel_device_info intel_pineview_info = { |
211 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
219 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
Line 212... | Line 220... | ||
212 | .need_gfx_hws = 1, .has_hotplug = 1, |
220 | .need_gfx_hws = 1, .has_hotplug = 1, |
213 | .has_overlay = 1, |
221 | .has_overlay = 1, |
214 | }; |
222 | }; |
215 | 223 | ||
216 | static const struct intel_device_info intel_ironlake_d_info = { |
224 | static const struct intel_device_info intel_ironlake_d_info = { |
217 | .gen = 5, |
225 | .gen = 5, .num_pipes = 2, |
Line 218... | Line 226... | ||
218 | .need_gfx_hws = 1, .has_hotplug = 1, |
226 | .need_gfx_hws = 1, .has_hotplug = 1, |
219 | .has_bsd_ring = 1, |
227 | .has_bsd_ring = 1, |
220 | }; |
228 | }; |
221 | 229 | ||
222 | static const struct intel_device_info intel_ironlake_m_info = { |
230 | static const struct intel_device_info intel_ironlake_m_info = { |
223 | .gen = 5, .is_mobile = 1, |
231 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
224 | .need_gfx_hws = 1, .has_hotplug = 1, |
232 | .need_gfx_hws = 1, .has_hotplug = 1, |
225 | .has_fbc = 1, |
233 | .has_fbc = 1, |
Line 226... | Line 234... | ||
226 | .has_bsd_ring = 1, |
234 | .has_bsd_ring = 1, |
227 | }; |
235 | }; |
228 | 236 | ||
229 | static const struct intel_device_info intel_sandybridge_d_info = { |
237 | static const struct intel_device_info intel_sandybridge_d_info = { |
230 | .gen = 6, |
238 | .gen = 6, .num_pipes = 2, |
231 | .need_gfx_hws = 1, .has_hotplug = 1, |
239 | .need_gfx_hws = 1, .has_hotplug = 1, |
232 | .has_bsd_ring = 1, |
240 | .has_bsd_ring = 1, |
233 | .has_blt_ring = 1, |
241 | .has_blt_ring = 1, |
234 | .has_llc = 1, |
242 | .has_llc = 1, |
Line -... | Line 243... | ||
- | 243 | .has_force_wake = 1, |
|
- | 244 | }; |
|
- | 245 | ||
- | 246 | static const struct intel_device_info intel_sandybridge_m_info = { |
|
- | 247 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
|
- | 248 | .need_gfx_hws = 1, .has_hotplug = 1, |
|
- | 249 | .has_fbc = 1, |
|
- | 250 | .has_bsd_ring = 1, |
|
235 | .has_force_wake = 1, |
251 | .has_blt_ring = 1, |
236 | }; |
- | |
237 | - | ||
238 | static const struct intel_device_info intel_sandybridge_m_info = { |
252 | .has_llc = 1, |
239 | .gen = 6, .is_mobile = 1, |
253 | .has_force_wake = 1, |
240 | .need_gfx_hws = 1, .has_hotplug = 1, |
- | |
241 | .has_fbc = 1, |
- | |
242 | .has_bsd_ring = 1, |
254 | }; |
Line 243... | Line 255... | ||
243 | .has_blt_ring = 1, |
255 | |
- | 256 | #define GEN7_FEATURES \ |
|
244 | .has_llc = 1, |
257 | .gen = 7, .num_pipes = 3, \ |
245 | .has_force_wake = 1, |
258 | .need_gfx_hws = 1, .has_hotplug = 1, \ |
- | 259 | .has_bsd_ring = 1, \ |
|
- | 260 | .has_blt_ring = 1, \ |
|
246 | }; |
261 | .has_llc = 1, \ |
247 | 262 | .has_force_wake = 1 |
|
248 | static const struct intel_device_info intel_ivybridge_d_info = { |
263 | |
249 | .is_ivybridge = 1, .gen = 7, |
- | |
250 | .need_gfx_hws = 1, .has_hotplug = 1, |
264 | static const struct intel_device_info intel_ivybridge_d_info = { |
251 | .has_bsd_ring = 1, |
265 | GEN7_FEATURES, |
Line 252... | Line 266... | ||
252 | .has_blt_ring = 1, |
266 | .is_ivybridge = 1, |
253 | .has_llc = 1, |
- | |
254 | .has_force_wake = 1, |
- | |
255 | }; |
267 | }; |
256 | 268 | ||
257 | static const struct intel_device_info intel_ivybridge_m_info = { |
269 | static const struct intel_device_info intel_ivybridge_m_info = { |
258 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, |
270 | GEN7_FEATURES, |
259 | .need_gfx_hws = 1, .has_hotplug = 1, |
271 | .is_ivybridge = 1, |
- | 272 | .is_mobile = 1, |
|
260 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ |
273 | }; |
Line 261... | Line 274... | ||
261 | .has_bsd_ring = 1, |
274 | |
262 | .has_blt_ring = 1, |
- | |
263 | .has_llc = 1, |
- | |
264 | .has_force_wake = 1, |
275 | static const struct intel_device_info intel_ivybridge_q_info = { |
265 | }; |
276 | GEN7_FEATURES, |
266 | - | ||
267 | static const struct intel_device_info intel_valleyview_m_info = { |
277 | .is_ivybridge = 1, |
268 | .gen = 7, .is_mobile = 1, |
278 | .num_pipes = 0, /* legal, last one wins */ |
- | 279 | }; |
|
269 | .need_gfx_hws = 1, .has_hotplug = 1, |
280 | |
Line 270... | Line 281... | ||
270 | .has_fbc = 0, |
281 | static const struct intel_device_info intel_valleyview_m_info = { |
271 | .has_bsd_ring = 1, |
- | |
272 | .has_blt_ring = 1, |
- | |
273 | .is_valleyview = 1, |
- | |
274 | .display_mmio_offset = VLV_DISPLAY_BASE, |
282 | GEN7_FEATURES, |
275 | }; |
283 | .is_mobile = 1, |
276 | - | ||
277 | static const struct intel_device_info intel_valleyview_d_info = { |
284 | .num_pipes = 2, |
Line 278... | Line 285... | ||
278 | .gen = 7, |
285 | .is_valleyview = 1, |
279 | .need_gfx_hws = 1, .has_hotplug = 1, |
- | |
280 | .has_fbc = 0, |
- | |
281 | .has_bsd_ring = 1, |
- | |
282 | .has_blt_ring = 1, |
286 | .display_mmio_offset = VLV_DISPLAY_BASE, |
283 | .is_valleyview = 1, |
287 | .has_llc = 0, /* legal, last one wins */ |
284 | .display_mmio_offset = VLV_DISPLAY_BASE, |
288 | }; |
285 | }; |
289 | |
Line 286... | Line 290... | ||
286 | 290 | static const struct intel_device_info intel_valleyview_d_info = { |
|
287 | static const struct intel_device_info intel_haswell_d_info = { |
291 | GEN7_FEATURES, |
288 | .is_haswell = 1, .gen = 7, |
292 | .num_pipes = 2, |
Line 339... | Line 343... | ||
339 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
343 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
340 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ |
344 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ |
341 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ |
345 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ |
342 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ |
346 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ |
343 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ |
347 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ |
- | 348 | INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */ |
|
344 | INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ |
349 | INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ |
345 | INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */ |
350 | INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */ |
346 | INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */ |
351 | INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */ |
347 | INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */ |
352 | INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */ |
348 | INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */ |
353 | INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */ |
349 | INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */ |
354 | INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */ |
350 | INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */ |
355 | INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */ |
351 | INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ |
356 | INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ |
352 | INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ |
357 | INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ |
353 | INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */ |
358 | INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */ |
- | 359 | INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */ |
|
- | 360 | INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */ |
|
- | 361 | INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */ |
|
- | 362 | INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */ |
|
- | 363 | INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */ |
|
- | 364 | INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */ |
|
354 | INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */ |
365 | INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */ |
355 | INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */ |
366 | INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */ |
356 | INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */ |
367 | INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */ |
357 | INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */ |
368 | INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */ |
358 | INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */ |
369 | INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */ |
359 | INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */ |
370 | INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */ |
360 | INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */ |
371 | INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */ |
361 | INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */ |
372 | INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */ |
362 | INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */ |
373 | INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */ |
- | 374 | INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */ |
|
- | 375 | INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */ |
|
- | 376 | INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */ |
|
- | 377 | INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */ |
|
- | 378 | INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */ |
|
- | 379 | INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */ |
|
363 | INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */ |
380 | INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */ |
364 | INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */ |
381 | INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */ |
365 | INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */ |
382 | INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */ |
366 | INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */ |
383 | INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */ |
367 | INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */ |
384 | INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */ |
368 | INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */ |
385 | INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */ |
369 | INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */ |
386 | INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */ |
370 | INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */ |
387 | INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */ |
371 | INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */ |
388 | INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */ |
- | 389 | INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */ |
|
- | 390 | INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */ |
|
- | 391 | INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */ |
|
- | 392 | INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */ |
|
- | 393 | INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */ |
|
- | 394 | INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */ |
|
372 | INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */ |
395 | INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */ |
373 | INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */ |
396 | INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */ |
374 | INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */ |
397 | INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */ |
375 | INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */ |
398 | INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */ |
376 | INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */ |
399 | INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */ |
377 | INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */ |
400 | INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */ |
378 | INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */ |
401 | INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */ |
379 | INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */ |
402 | INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */ |
380 | INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */ |
403 | INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */ |
- | 404 | INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */ |
|
- | 405 | INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */ |
|
- | 406 | INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */ |
|
- | 407 | INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */ |
|
- | 408 | INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */ |
|
- | 409 | INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */ |
|
381 | INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info), |
410 | INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info), |
- | 411 | INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info), |
|
- | 412 | INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info), |
|
- | 413 | INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info), |
|
382 | INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info), |
414 | INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info), |
383 | INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info), |
415 | INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info), |
384 | {0, 0, 0} |
416 | {0, 0, 0} |
385 | }; |
417 | }; |
Line 393... | Line 425... | ||
393 | void intel_detect_pch(struct drm_device *dev) |
425 | void intel_detect_pch(struct drm_device *dev) |
394 | { |
426 | { |
395 | struct drm_i915_private *dev_priv = dev->dev_private; |
427 | struct drm_i915_private *dev_priv = dev->dev_private; |
396 | struct pci_dev *pch; |
428 | struct pci_dev *pch; |
Line -... | Line 429... | ||
- | 429 | ||
- | 430 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
|
- | 431 | * (which really amounts to a PCH but no South Display). |
|
- | 432 | */ |
|
- | 433 | if (INTEL_INFO(dev)->num_pipes == 0) { |
|
- | 434 | dev_priv->pch_type = PCH_NOP; |
|
- | 435 | dev_priv->num_pch_pll = 0; |
|
- | 436 | return; |
|
- | 437 | } |
|
397 | 438 | ||
398 | /* |
439 | /* |
399 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to |
440 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to |
400 | * make graphics device passthrough work easy for VMM, that only |
441 | * make graphics device passthrough work easy for VMM, that only |
401 | * need to expose ISA bridge to let driver know the real hardware |
442 | * need to expose ISA bridge to let driver know the real hardware |
Line 427... | Line 468... | ||
427 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
468 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
428 | dev_priv->pch_type = PCH_LPT; |
469 | dev_priv->pch_type = PCH_LPT; |
429 | dev_priv->num_pch_pll = 0; |
470 | dev_priv->num_pch_pll = 0; |
430 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); |
471 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); |
431 | WARN_ON(!IS_HASWELL(dev)); |
472 | WARN_ON(!IS_HASWELL(dev)); |
- | 473 | WARN_ON(IS_ULT(dev)); |
|
432 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
474 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
433 | dev_priv->pch_type = PCH_LPT; |
475 | dev_priv->pch_type = PCH_LPT; |
434 | dev_priv->num_pch_pll = 0; |
476 | dev_priv->num_pch_pll = 0; |
435 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); |
477 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); |
436 | WARN_ON(!IS_HASWELL(dev)); |
478 | WARN_ON(!IS_HASWELL(dev)); |
- | 479 | WARN_ON(!IS_ULT(dev)); |
|
437 | } |
480 | } |
438 | BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS); |
481 | BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS); |
439 | } |
482 | } |
440 | } |
483 | } |
441 | } |
484 | } |
Line 724... | Line 767... | ||
724 | } |
767 | } |
Line 725... | Line 768... | ||
725 | 768 | ||
726 | return true; |
769 | return true; |
Line -... | Line 770... | ||
- | 770 | } |
|
- | 771 | ||
- | 772 | /* We give fast paths for the really cool registers */ |
|
- | 773 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
|
- | 774 | ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ |
|
727 | } |
775 | ((reg) < 0x40000) && \ |
728 | 776 | ((reg) != FORCEWAKE)) |
|
729 | static void |
777 | static void |
730 | ilk_dummy_write(struct drm_i915_private *dev_priv) |
778 | ilk_dummy_write(struct drm_i915_private *dev_priv) |
731 | { |
779 | { |
732 | /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the |
780 | /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the |
733 | * chip from rc6 before touching it for real. MI_MODE is masked, hence |
781 | * chip from rc6 before touching it for real. MI_MODE is masked, hence |
734 | * harmless to write 0 into. */ |
782 | * harmless to write 0 into. */ |
Line -... | Line 783... | ||
- | 783 | I915_WRITE_NOTRACE(MI_MODE, 0); |
|
- | 784 | } |
|
- | 785 | ||
- | 786 | static void |
|
- | 787 | hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) |
|
- | 788 | { |
|
- | 789 | if (IS_HASWELL(dev_priv->dev) && |
|
- | 790 | (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
|
- | 791 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", |
|
- | 792 | reg); |
|
- | 793 | I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
|
- | 794 | } |
|
- | 795 | } |
|
- | 796 | ||
- | 797 | static void |
|
- | 798 | hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) |
|
- | 799 | { |
|
- | 800 | if (IS_HASWELL(dev_priv->dev) && |
|
- | 801 | (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
|
- | 802 | DRM_ERROR("Unclaimed write to %x\n", reg); |
|
- | 803 | I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
|
735 | I915_WRITE_NOTRACE(MI_MODE, 0); |
804 | } |
736 | } |
805 | } |
737 | 806 | ||
738 | #define __i915_read(x, y) \ |
807 | #define __i915_read(x, y) \ |
739 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
808 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
Line 768... | Line 837... | ||
768 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
837 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
769 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
838 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
770 | } \ |
839 | } \ |
771 | if (IS_GEN5(dev_priv->dev)) \ |
840 | if (IS_GEN5(dev_priv->dev)) \ |
772 | ilk_dummy_write(dev_priv); \ |
841 | ilk_dummy_write(dev_priv); \ |
773 | if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ |
- | |
774 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \ |
842 | hsw_unclaimed_reg_clear(dev_priv, reg); \ |
775 | I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \ |
- | |
776 | } \ |
- | |
777 | write##y(val, dev_priv->regs + reg); \ |
843 | write##y(val, dev_priv->regs + reg); \ |
778 | if (unlikely(__fifo_ret)) { \ |
844 | if (unlikely(__fifo_ret)) { \ |
779 | gen6_gt_check_fifodbg(dev_priv); \ |
845 | gen6_gt_check_fifodbg(dev_priv); \ |
780 | } \ |
846 | } \ |
781 | if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ |
- | |
782 | DRM_ERROR("Unclaimed write to %x\n", reg); \ |
847 | hsw_unclaimed_reg_check(dev_priv, reg); \ |
783 | writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); \ |
- | |
784 | } \ |
- | |
785 | } |
848 | } |
786 | __i915_write(8, b) |
849 | __i915_write(8, b) |
787 | __i915_write(16, w) |
850 | __i915_write(16, w) |
788 | __i915_write(32, l) |
851 | __i915_write(32, l) |
789 | __i915_write(64, q) |
852 | __i915_write(64, q) |