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Line 51... Line 51...
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int i915_panel_ignore_lid __read_mostly         =  0;
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int i915_panel_ignore_lid __read_mostly         =  0;
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unsigned int i915_powersave  __read_mostly      =  0;
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unsigned int i915_powersave  __read_mostly      =  0;
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int i915_vbt_sdvo_panel_type __read_mostly      = -1;
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int i915_vbt_sdvo_panel_type __read_mostly      = -1;
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#define PCI_VENDOR_ID_INTEL        0x8086
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#define PCI_VENDOR_ID_INTEL        0x8086
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#define INTEL_VGA_DEVICE(id, info) {        \
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#define INTEL_VGA_DEVICE(id, info) {        \
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    .class = PCI_CLASS_DISPLAY_VGA << 8,    \
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	.class = PCI_BASE_CLASS_DISPLAY << 16,	\
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    .class_mask = 0xff0000,                 \
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    .class_mask = 0xff0000,                 \
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    .vendor = 0x8086,                       \
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    .vendor = 0x8086,                       \
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    .device = id,                           \
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    .device = id,                           \
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            }
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            }
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        }
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        }
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    }
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    }
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}
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}
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static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
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void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
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{
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{
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    int count;
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    int count;
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    count = 0;
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    count = 0;
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    while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
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    while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
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        udelay(10);
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        udelay(10);
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}
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}
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void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
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{
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	int count;
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	count = 0;
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	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
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		udelay(10);
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	I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
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	POSTING_READ(FORCEWAKE_MT);
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	count = 0;
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	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
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		udelay(10);
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}
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/*
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/*
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 * Generally this is called implicitly by the register read function. However,
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 * Generally this is called implicitly by the register read function. However,
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 * if some sequence requires the GT to not power down then this function should
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 * if some sequence requires the GT to not power down then this function should
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 * be called at the beginning of the sequence followed by a call to
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 * be called at the beginning of the sequence followed by a call to
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 * gen6_gt_force_wake_put() at the end of the sequence.
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 * gen6_gt_force_wake_put() at the end of the sequence.
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 */
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 */
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void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
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void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
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{
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{
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//    WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
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	unsigned long irqflags;
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    /* Forcewake is atomic in case we get in here without the lock */
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	spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
-
 
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	if (dev_priv->forcewake_count++ == 0)
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    if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)
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		dev_priv->display.force_wake_get(dev_priv);
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        __gen6_gt_force_wake_get(dev_priv);
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	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
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}
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}
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static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
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void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
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{
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{
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    I915_WRITE_NOTRACE(FORCEWAKE, 0);
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    POSTING_READ(FORCEWAKE);
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}
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void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
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{
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    I915_WRITE_NOTRACE(FORCEWAKE, 0);
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	I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
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    POSTING_READ(FORCEWAKE);
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	POSTING_READ(FORCEWAKE_MT);
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}
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}
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/*
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/*
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 * see gen6_gt_force_wake_get()
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 * see gen6_gt_force_wake_get()
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 */
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 */
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void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
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void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
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{
-
 
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	unsigned long irqflags;
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{
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//    WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
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	spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
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	if (--dev_priv->forcewake_count == 0)
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    if (atomic_dec_and_test(&dev_priv->forcewake_count))
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		dev_priv->display.force_wake_put(dev_priv);
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    return ret;
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    return ret;
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}
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#define __i915_read(x, y) \
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u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
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	u##x val = 0; \
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	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
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		unsigned long irqflags; \
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		spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
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		if (dev_priv->forcewake_count == 0) \
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			dev_priv->display.force_wake_get(dev_priv); \
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		val = read##y(dev_priv->regs + reg); \
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		if (dev_priv->forcewake_count == 0) \
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			dev_priv->display.force_wake_put(dev_priv); \
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		spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
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	} else { \
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		val = read##y(dev_priv->regs + reg); \
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	} \
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	return val; \
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}
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__i915_read(8, b)
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__i915_read(16, w)
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__i915_read(32, l)
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__i915_read(64, q)
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#undef __i915_read
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#define __i915_write(x, y) \
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void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
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	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
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		__gen6_gt_wait_for_fifo(dev_priv); \
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	} \
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	write##y(val, dev_priv->regs + reg); \
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}
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__i915_write(8, b)
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__i915_write(16, w)