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Rev 6088 Rev 6937
Line 405... Line 405...
405 
 *
 405 
 *
406 
 * Registers with non-zero mask are only allowed to be written using
 406 
 * Registers with non-zero mask are only allowed to be written using
407 
 * LRI.
 407 
 * LRI.
408 
 */
 408 
 */
409 
struct drm_i915_reg_descriptor {
 409 
struct drm_i915_reg_descriptor {
410 
	u32 addr;
 410 
	i915_reg_t addr;
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	u32 mask;
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	u32 mask;
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	u32 value;
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	u32 value;
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};
 413 
};
Line 414... Line 414...
414 
 
 414 
 
415 
/* Convenience macro for adding 32-bit registers. */
 415 
/* Convenience macro for adding 32-bit registers. */
416 
#define REG32(address, ...)                             \
 416 
#define REG32(_reg, ...) \
Line 417... Line 417...
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	{ .addr = address, __VA_ARGS__ }
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	{ .addr = (_reg), __VA_ARGS__ }
418 
 
 418 
 
419 
/*
 419 
/*
420 
 * Convenience macro for adding 64-bit registers.
 420 
 * Convenience macro for adding 64-bit registers.
421 
 *
 421 
 *
422 
 * Some registers that userspace accesses are 64 bits. The register
 422 
 * Some registers that userspace accesses are 64 bits. The register
423 
 * access commands only allow 32-bit accesses. Hence, we have to include
 423 
 * access commands only allow 32-bit accesses. Hence, we have to include
- 
 
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 * entries for both halves of the 64-bit registers.
- 
 
 425 
 */
- 
 
 426 
#define REG64(_reg) \
- 
 
 427 
	{ .addr = _reg }, \
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 * entries for both halves of the 64-bit registers.
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	{ .addr = _reg ## _UDW }
- 
 
 429 
 
425 
 */
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#define REG64_IDX(_reg, idx) \
Line 426... Line 431...
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#define REG64(addr)                                     \
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	{ .addr = _reg(idx) }, \
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	REG32(addr), REG32(addr + sizeof(u32))
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	{ .addr = _reg ## _UDW(idx) }
428 
 
 433 
 
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static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
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static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
Line 449... Line 454...
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	REG32(GEN7_3DPRIM_START_INSTANCE),
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	REG32(GEN7_3DPRIM_START_INSTANCE),
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	REG32(GEN7_3DPRIM_BASE_VERTEX),
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	REG32(GEN7_3DPRIM_BASE_VERTEX),
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	REG32(GEN7_GPGPU_DISPATCHDIMX),
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	REG32(GEN7_GPGPU_DISPATCHDIMX),
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	REG32(GEN7_GPGPU_DISPATCHDIMY),
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	REG32(GEN7_GPGPU_DISPATCHDIMY),
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	REG32(GEN7_GPGPU_DISPATCHDIMZ),
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	REG32(GEN7_GPGPU_DISPATCHDIMZ),
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	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
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	REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0),
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	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
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	REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1),
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	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
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	REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2),
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	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)),
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	REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3),
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	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)),
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	REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0),
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	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)),
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	REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1),
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	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)),
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	REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2),
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	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)),
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	REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3),
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	REG32(GEN7_SO_WRITE_OFFSET(0)),
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	REG32(GEN7_SO_WRITE_OFFSET(0)),
463 
	REG32(GEN7_SO_WRITE_OFFSET(1)),
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	REG32(GEN7_SO_WRITE_OFFSET(1)),
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	REG32(GEN7_SO_WRITE_OFFSET(2)),
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	REG32(GEN7_SO_WRITE_OFFSET(2)),
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	REG32(GEN7_SO_WRITE_OFFSET(3)),
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	REG32(GEN7_SO_WRITE_OFFSET(3)),
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	REG32(GEN7_L3SQCREG1),
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	REG32(GEN7_L3SQCREG1),
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590 
	int i;
 595 
	int i;
591 
	u32 previous = 0;
 596 
	u32 previous = 0;
592 
	bool ret = true;
 597 
	bool ret = true;
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593 
 
 598 
 
594 
	for (i = 0; i < reg_count; i++) {
 599 
	for (i = 0; i < reg_count; i++) {
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		u32 curr = reg_table[i].addr;
 600 
		u32 curr = i915_mmio_reg_offset(reg_table[i].addr);
596 
 
 601 
 
597 
		if (curr < previous) {
 602 
		if (curr < previous) {
598 
			DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n",
 603 
			DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n",
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845 
{
 850 
{
846 
	if (table) {
 851 
	if (table) {
847 
		int i;
 852 
		int i;
Line 848... Line 853...
848 
 
 853 
 
849 
		for (i = 0; i < count; i++) {
 854 
		for (i = 0; i < count; i++) {
850 
			if (table[i].addr == addr)
 855 
			if (i915_mmio_reg_offset(table[i].addr) == addr)
851 
				return &table[i];
 856 
				return &table[i];
852 
		}
 857 
		}
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853 
	}
 858 
	}
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1021 
			 * snooping on the perf data from another process. To do
 1026 
			 * snooping on the perf data from another process. To do
1022 
			 * that, we need to check the value that will be written
 1027 
			 * that, we need to check the value that will be written
1023 
			 * to the register. Hence, limit OACONTROL writes to
 1028 
			 * to the register. Hence, limit OACONTROL writes to
1024 
			 * only MI_LOAD_REGISTER_IMM commands.
 1029 
			 * only MI_LOAD_REGISTER_IMM commands.
1025 
			 */
 1030 
			 */
1026 
			if (reg_addr == OACONTROL) {
 1031 
			if (reg_addr == i915_mmio_reg_offset(OACONTROL)) {
1027 
				if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
 1032 
				if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
1028 
					DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
 1033 
					DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
1029 
					return false;
 1034 
					return false;
1030 
				}
 1035 
				}