WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_cmd_parser.c

 	CMD(  MI_REPORT_HEAD,                   SMI,    F,  1,      S  ),
 	CMD(  MI_SUSPEND_FLUSH,                 SMI,    F,  1,      S  ),
 	CMD(  MI_SEMAPHORE_MBOX,                SMI,   !F,  0xFF,   R  ),
 	CMD(  MI_STORE_DWORD_INDEX,             SMI,   !F,  0xFF,   R  ),
 	CMD(  MI_LOAD_REGISTER_IMM(1),          SMI,   !F,  0xFF,   W,
-	      .reg = { .offset = 1, .mask = 0x007FFFFC }               ),
+	      .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 }    ),
-	CMD(  MI_STORE_REGISTER_MEM(1),         SMI,   !F,  0xFF,   W | B,
+	CMD(  MI_STORE_REGISTER_MEM,            SMI,    F,  3,     W | B,
 	      .reg = { .offset = 1, .mask = 0x007FFFFC },
 	      .bits = {{
 			.offset = 0,
 			.mask = MI_GLOBAL_GTT,
 			.expected = 0,
 	      }},						       ),
-	CMD(  MI_LOAD_REGISTER_MEM,             SMI,   !F,  0xFF,   W | B,
+	CMD(  MI_LOAD_REGISTER_MEM,             SMI,    F,  3,     W | B,
 	      .reg = { .offset = 1, .mask = 0x007FFFFC },
 	      .bits = {{
 			.offset = 0,
 			.mask = MI_GLOBAL_GTT,
 			.expected = 0,
 static const struct drm_i915_cmd_descriptor render_cmds[] = {
 	CMD(  MI_FLUSH,                         SMI,    F,  1,      S  ),
 	CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 	CMD(  MI_PREDICATE,                     SMI,    F,  1,      S  ),
 	CMD(  MI_TOPOLOGY_FILTER,               SMI,    F,  1,      S  ),
+	CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 	CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
 	CMD(  MI_SET_CONTEXT,                   SMI,   !F,  0xFF,   R  ),
 	CMD(  MI_URB_CLEAR,                     SMI,   !F,  0xFF,   S  ),
 	CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3F,   B,
 	      .bits = {{
 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
 	CMD(  MI_SET_PREDICATE,                 SMI,    F,  1,      S  ),
 	CMD(  MI_RS_CONTROL,                    SMI,    F,  1,      S  ),
+	CMD(  MI_URB_ATOMIC_ALLOC,              SMI,    F,  1,      S  ),
-	CMD(  MI_URB_ATOMIC_ALLOC,              SMI,    F,  1,      S  ),
+	CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 	CMD(  MI_RS_CONTEXT,                    SMI,    F,  1,      S  ),
 	CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   M  ),
 	CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
 	CMD(  MI_LOAD_REGISTER_REG,             SMI,   !F,  0xFF,   R  ),
 	CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS,  S3D,   !F,  0x1FF,  S  ),
 };
 static const struct drm_i915_cmd_descriptor video_cmds[] = {
+	CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
-	CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
+	CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 	CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
 	      .bits = {{
 			.offset = 0,
 			.mask = MI_GLOBAL_GTT,
 	CMD(  MFX_WAIT,                         SMFX,   F,  1,      S  ),
 };
 static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
+	CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
-	CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
+	CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 	CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
 	      .bits = {{
 			.offset = 0,
 			.mask = MI_GLOBAL_GTT,
 	{ hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
 };
 /*
+ * Register whitelists, sorted by increasing register offset.
+ */
+/*
+ * An individual whitelist entry granting access to register addr.  If
+ * mask is non-zero the argument of immediate register writes will be
+ * AND-ed with mask, and the command will be rejected if the result
+ * doesn't match value.
+ *
+ * Registers with non-zero mask are only allowed to be written using
+ * LRI.
+ */
+struct drm_i915_reg_descriptor {
+	u32 addr;
+	u32 mask;
+	u32 value;
+};
+/* Convenience macro for adding 32-bit registers. */
+#define REG32(address, ...)                             \
+	{ .addr = address, __VA_ARGS__ }
+/*
- * Register whitelists, sorted by increasing register offset.
+ * Convenience macro for adding 64-bit registers.
+ *
  * Some registers that userspace accesses are 64 bits. The register
  * access commands only allow 32-bit accesses. Hence, we have to include
  * entries for both halves of the 64-bit registers.
+ */
+#define REG64(addr)                                     \
- */
+	REG32(addr), REG32(addr + sizeof(u32))
-/* Convenience macro for adding 64-bit registers */
-#define REG64(addr) (addr), (addr + sizeof(u32))
 static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
-static const u32 gen7_render_regs[] = {
+	REG64(GPGPU_THREADS_DISPATCHED),
 	REG64(HS_INVOCATION_COUNT),
 	REG64(DS_INVOCATION_COUNT),
 	REG64(IA_VERTICES_COUNT),
 	REG64(GS_PRIMITIVES_COUNT),
 	REG64(CL_INVOCATION_COUNT),
 	REG64(CL_PRIMITIVES_COUNT),
 	REG64(PS_INVOCATION_COUNT),
 	REG64(PS_DEPTH_COUNT),
-	OACONTROL, /* Only allowed for LRI and SRM. See below. */
+	REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */
 	REG64(MI_PREDICATE_SRC0),
 	REG64(MI_PREDICATE_SRC1),
-	GEN7_3DPRIM_END_OFFSET,
+	REG32(GEN7_3DPRIM_END_OFFSET),
-	GEN7_3DPRIM_START_VERTEX,
+	REG32(GEN7_3DPRIM_START_VERTEX),
-	GEN7_3DPRIM_VERTEX_COUNT,
+	REG32(GEN7_3DPRIM_VERTEX_COUNT),
-	GEN7_3DPRIM_INSTANCE_COUNT,
+	REG32(GEN7_3DPRIM_INSTANCE_COUNT),
-	GEN7_3DPRIM_START_INSTANCE,
+	REG32(GEN7_3DPRIM_START_INSTANCE),
-	GEN7_3DPRIM_BASE_VERTEX,
+	REG32(GEN7_3DPRIM_BASE_VERTEX),
+	REG32(GEN7_GPGPU_DISPATCHDIMX),
+	REG32(GEN7_GPGPU_DISPATCHDIMY),
+	REG32(GEN7_GPGPU_DISPATCHDIMZ),
 	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
 	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
 	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
 	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)),
 	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)),
 	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)),
 	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)),
 	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)),
-	GEN7_SO_WRITE_OFFSET(0),
+	REG32(GEN7_SO_WRITE_OFFSET(0)),
-	GEN7_SO_WRITE_OFFSET(1),
+	REG32(GEN7_SO_WRITE_OFFSET(1)),
-	GEN7_SO_WRITE_OFFSET(2),
+	REG32(GEN7_SO_WRITE_OFFSET(2)),
-	GEN7_SO_WRITE_OFFSET(3),
+	REG32(GEN7_SO_WRITE_OFFSET(3)),
-	GEN7_L3SQCREG1,
+	REG32(GEN7_L3SQCREG1),
-	GEN7_L3CNTLREG2,
+	REG32(GEN7_L3CNTLREG2),
-	GEN7_L3CNTLREG3,
+	REG32(GEN7_L3CNTLREG3),
+	REG32(HSW_SCRATCH1,
+	      .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
+	      .value = 0),
+	REG32(HSW_ROW_CHICKEN3,
+	      .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |
+                        HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
+	      .value = 0),
 };
-static const u32 gen7_blt_regs[] = {
+static const struct drm_i915_reg_descriptor gen7_blt_regs[] = {
-	BCS_SWCTRL,
+	REG32(BCS_SWCTRL),
 };
-static const u32 ivb_master_regs[] = {
+static const struct drm_i915_reg_descriptor ivb_master_regs[] = {
-	FORCEWAKE_MT,
+	REG32(FORCEWAKE_MT),
-	DERRMR,
+	REG32(DERRMR),
-	GEN7_PIPE_DE_LOAD_SL(PIPE_A),
+	REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)),
-	GEN7_PIPE_DE_LOAD_SL(PIPE_B),
+	REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)),
-	GEN7_PIPE_DE_LOAD_SL(PIPE_C),
+	REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)),
 };
-static const u32 hsw_master_regs[] = {
+static const struct drm_i915_reg_descriptor hsw_master_regs[] = {
-	FORCEWAKE_MT,
+	REG32(FORCEWAKE_MT),
-	DERRMR,
+	REG32(DERRMR),
 };
+#undef REG64
-#undef REG64
+#undef REG32
 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
+{
 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
+{
 	u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 	u32 subclient =
 		(cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
+	u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT;
 	if (client == INSTR_MI_CLIENT)
 		return 0x3F;
 	else if (client == INSTR_RC_CLIENT) {
+		if (subclient == INSTR_MEDIA_SUBCLIENT) {
-		if (subclient == INSTR_MEDIA_SUBCLIENT)
+			if (op == 6)
-			return 0xFFF;
+				return 0xFFFF;
+			else
+				return 0xFFF;
-		else
+		} else
 			return 0xFF;
+	}
 		u32 previous = 0;
 		int j;
 		for (j = 0; j < table->count; j++) {
 			const struct drm_i915_cmd_descriptor *desc =
-				&table->table[i];
+				&table->table[j];
 			u32 curr = desc->cmd.value & desc->cmd.mask;
 			if (curr < previous) {
+	}
 	return ret;
 }
+static bool check_sorted(int ring_id,
 			 const struct drm_i915_reg_descriptor *reg_table,
-static bool check_sorted(int ring_id, const u32 *reg_table, int reg_count)
+			 int reg_count)
+{
 	int i;
 	u32 previous = 0;
 	bool ret = true;
 	for (i = 0; i < reg_count; i++) {
-		u32 curr = reg_table[i];
+		u32 curr = reg_table[i].addr;
+	}
 	BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_table_count));
 	BUG_ON(!validate_regs_sorted(ring));
 	WARN_ON(!hash_empty(ring->cmd_hash));
 	if (hash_empty(ring->cmd_hash)) {
 	ret = init_hash_table(ring, cmd_tables, cmd_table_count);
 	if (ret) {
 		DRM_ERROR("CMD: cmd_parser_init failed!\n");
 		fini_hash_table(ring);
-		return ret;
 		return ret;
+	}
 	default_desc->length.mask = mask;
 	return default_desc;
 }
+static const struct drm_i915_reg_descriptor *
 find_reg(const struct drm_i915_reg_descriptor *table,
-static bool valid_reg(const u32 *table, int count, u32 addr)
+	 int count, u32 addr)
+{
-	if (table && count != 0) {
+	if (table) {
 		int i;
 		for (i = 0; i < count; i++) {
-			if (table[i] == addr)
+			if (table[i].addr == addr)
-				return true;
+				return &table[i];
+		}
 	}
 	return NULL;
 	return false;
 static u32 *vmap_batch(struct drm_i915_gem_object *obj,
+		       unsigned start, unsigned len)
+{
+	int i;
-static u32 *vmap_batch(struct drm_i915_gem_object *obj)
+	void *addr = NULL;
 	struct sg_page_iter sg_iter;
-	int i;
+	int first_page = start >> PAGE_SHIFT;
-	void *addr = NULL;
+	int last_page = (len + start + 4095) >> PAGE_SHIFT;
-	struct sg_page_iter sg_iter;
+	int npages = last_page - first_page;
 	struct page **pages;
     pages = kmalloc(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
 	if (pages == NULL) {
+		DRM_DEBUG_DRIVER("Failed to get space for pages\n");
-		DRM_DEBUG_DRIVER("Failed to get space for pages\n");
+		goto finish;
 		goto finish;
-	}
 	i = 0;
-	i = 0;
+	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, first_page) {
-	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
+		pages[i++] = sg_page_iter_page(&sg_iter);
-		pages[i] = sg_page_iter_page(&sg_iter);
+		if (i == npages)
-		i++;
+			break;
+	}
-//   addr = vmap(pages, i, 0, PAGE_KERNEL);
+	addr = vmap(pages, i, 0, PAGE_KERNEL);
 	if (addr == NULL) {
+		DRM_DEBUG_DRIVER("Failed to vmap pages\n");
+		goto finish;
+	}
+finish:
+	if (pages)
+		drm_free_large(pages);
+	return (u32*)addr;
+}
+/* Returns a vmap'd pointer to dest_obj, which the caller must unmap */
+static u32 *copy_batch(struct drm_i915_gem_object *dest_obj,
+		       struct drm_i915_gem_object *src_obj,
+		       u32 batch_start_offset,
+		       u32 batch_len)
+{
+	int needs_clflush = 0;
+	void *src_base, *src;
+	void *dst = NULL;
+	int ret;
+	if (batch_len > dest_obj->base.size ||
+	    batch_len + batch_start_offset > src_obj->base.size)
+		return ERR_PTR(-E2BIG);
+	if (WARN_ON(dest_obj->pages_pin_count == 0))
+		return ERR_PTR(-ENODEV);
+	ret = i915_gem_obj_prepare_shmem_read(src_obj, &needs_clflush);
+	if (ret) {
+		DRM_DEBUG_DRIVER("CMD: failed to prepare shadow batch\n");
+		return ERR_PTR(ret);
+	}
+	src_base = vmap_batch(src_obj, batch_start_offset, batch_len);
+	if (!src_base) {
+		DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
+		ret = -ENOMEM;
+		goto unpin_src;
+	}
+	ret = i915_gem_object_set_to_cpu_domain(dest_obj, true);
+	if (ret) {
+		DRM_DEBUG_DRIVER("CMD: Failed to set shadow batch to CPU\n");
+		goto unmap_src;
+	}
+	dst = vmap_batch(dest_obj, 0, batch_len);
+	if (!dst) {
+		DRM_DEBUG_DRIVER("CMD: Failed to vmap shadow batch\n");
+		ret = -ENOMEM;
+		goto unmap_src;
+	}
+	src = src_base + offset_in_page(batch_start_offset);
+	if (needs_clflush)
+		drm_clflush_virt_range(src, batch_len);
-		DRM_DEBUG_DRIVER("Failed to vmap pages\n");
+	memcpy(dst, src, batch_len);
 		goto finish;
 unmap_src:
 	vunmap(src_base);
-finish:
+unpin_src:
 	return (i915.enable_cmd_parser == 1);
+}
 static bool check_cmd(const struct intel_engine_cs *ring,
 		      const struct drm_i915_cmd_descriptor *desc,
-		      const u32 *cmd,
+		      const u32 *cmd, u32 length,
 		      const bool is_master,
 		      bool *oacontrol_set)
+{
 	if (desc->flags & CMD_DESC_REJECT) {
 				 *cmd);
 		return false;
+	}
+	if (desc->flags & CMD_DESC_REGISTER) {
+		/*
+		 * Get the distance between individual register offset
+		 * fields if the command can perform more than one
+		 * access at a time.
+		 */
+		const u32 step = desc->reg.step ? desc->reg.step : length;
+		u32 offset;
+		for (offset = desc->reg.offset; offset < length;
-	if (desc->flags & CMD_DESC_REGISTER) {
+		     offset += step) {
+			const u32 reg_addr = cmd[offset] & desc->reg.mask;
+			const struct drm_i915_reg_descriptor *reg =
+				find_reg(ring->reg_table, ring->reg_count,
+					 reg_addr);
+			if (!reg && is_master)
+				reg = find_reg(ring->master_reg_table,
+					       ring->master_reg_count,
+					       reg_addr);
+			if (!reg) {
+				DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
+						 reg_addr, *cmd, ring->id);
+				return false;
 		u32 reg_addr = cmd[desc->reg.offset] & desc->reg.mask;
-		/*
+			/*
-		 * OACONTROL requires some special handling for writes. We
+			 * OACONTROL requires some special handling for
-		 * want to make sure that any batch which enables OA also
+			 * writes. We want to make sure that any batch which
-		 * disables it before the end of the batch. The goal is to
+			 * enables OA also disables it before the end of the
-		 * prevent one process from snooping on the perf data from
+			 * batch. The goal is to prevent one process from
+			 * snooping on the perf data from another process. To do
-		 * another process. To do that, we need to check the value
+			 * that, we need to check the value that will be written
-		 * that will be written to the register. Hence, limit
+			 * to the register. Hence, limit OACONTROL writes to
-		 * OACONTROL writes to only MI_LOAD_REGISTER_IMM commands.
+			 * only MI_LOAD_REGISTER_IMM commands.
-		 */
+			 */
-		if (reg_addr == OACONTROL) {
+			if (reg_addr == OACONTROL) {
-			if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
+				if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
-				DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
+					DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
-				return false;
+					return false;
-			}
+				}
+				if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1))
-			if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1))
+					*oacontrol_set = (cmd[offset + 1] != 0);
-				*oacontrol_set = (cmd[2] != 0);
+			}
-		}
+			/*
+			 * Check the value written to the register against the
-		if (!valid_reg(ring->reg_table,
+			 * allowed mask/value pair given in the whitelist entry.
-			       ring->reg_count, reg_addr)) {
+			 */
-			if (!is_master ||
-			    !valid_reg(ring->master_reg_table,
+			if (reg->mask) {
-				       ring->master_reg_count,
+				if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
+					DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n",
+							 reg_addr);
+					return false;
+				}
-				       reg_addr)) {
+				if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) &&
-				DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
+				    (offset + 2 > length ||
-						 reg_addr,
+				     (cmd[offset + 1] & reg->mask) != reg->value)) {
-						 *cmd,
+					DRM_DEBUG_DRIVER("CMD: Rejected LRI to masked register 0x%08X\n",
-						 ring->id);
+							 reg_addr);
+					return false;
 				return false;
+			}
+		}
 #if 0
 /**
  * i915_parse_cmds() - parse a submitted batch buffer for privilege violations
  * @ring: the ring on which the batch is to execute
  * @batch_obj: the batch buffer in question
+ * @shadow_batch_obj: copy of the batch buffer in question
  * @batch_start_offset: byte offset in the batch at which execution starts
+ * @batch_len: length of the commands in batch_obj
  * @is_master: is the submitting process the drm master?
+ *
  * Parses the specified batch buffer looking for privilege violations as
  * described in the overview.
+ *
  * Return: non-zero if the parser finds violations or otherwise fails; -EACCES
  * if the batch appears legal but should use hardware parsing
  */
 int i915_parse_cmds(struct intel_engine_cs *ring,
 		    struct drm_i915_gem_object *batch_obj,
+		    struct drm_i915_gem_object *shadow_batch_obj,
 		    u32 batch_start_offset,
+		    u32 batch_len,
 		    bool is_master)
+{
-	int ret = 0;
 	u32 *cmd, *batch_base, *batch_end;
 	struct drm_i915_cmd_descriptor default_desc = { 0 };
-	int needs_clflush = 0;
 	bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */
+	int ret = 0;
-	ret = i915_gem_obj_prepare_shmem_read(batch_obj, &needs_clflush);
-	if (ret) {
-		DRM_DEBUG_DRIVER("CMD: failed to prep read\n");
-		return ret;
-	}
+	batch_base = copy_batch(shadow_batch_obj, batch_obj,
-	batch_base = vmap_batch(batch_obj);
+				batch_start_offset, batch_len);
-	if (!batch_base) {
+	if (IS_ERR(batch_base)) {
-		DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
-		i915_gem_object_unpin_pages(batch_obj);
+		DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n");
-		return -ENOMEM;
+		return PTR_ERR(batch_base);
+	}
-	}
+	/*
-	if (needs_clflush)
-		drm_clflush_virt_range((char *)batch_base, batch_obj->base.size);
+	 * We use the batch length as size because the shadow object is as
+	 * large or larger and copy_batch() will write MI_NOPs to the extra
+	 * space. Parsing should be faster in some cases this way.
+	 */
-	cmd = batch_base + (batch_start_offset / sizeof(*cmd));
+	batch_end = batch_base + (batch_len / sizeof(*batch_end));
 	batch_end = cmd + (batch_obj->base.size / sizeof(*batch_end));
 	cmd = batch_base;
 	while (cmd < batch_end) {
 					 batch_end - cmd);
 			ret = -EINVAL;
 			break;
+		}
+		if (!check_cmd(ring, desc, cmd, length, is_master,
-		if (!check_cmd(ring, desc, cmd, is_master, &oacontrol_set)) {
+			       &oacontrol_set)) {
 			ret = -EINVAL;
 			break;
+		}
 	if (cmd >= batch_end) {
 		DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
 		ret = -EINVAL;
+	}
-//   vunmap(batch_base);
-	i915_gem_object_unpin_pages(batch_obj);
+	vunmap(batch_base);
 	return ret;
+	 *
 	 * 1. Initial version. Checks batches and reports violations, but leaves
 	 *    hardware parsing enabled (so does not allow new use cases).
 	 * 2. Allow access to the MI_PREDICATE_SRC0 and
 	 *    MI_PREDICATE_SRC1 registers.
+	 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
+	 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
+	 * 5. GPGPU dispatch compute indirect registers.
 	 */
-	return 2;
+	return 5;
+}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_cmd_parser.c – Rev 5354 → 6084