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Rev 3031 | Rev 5060 | ||
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Line 54... | Line 54... | ||
54 | #define TFP410_CTL_2_RSEN (1<<2) |
54 | #define TFP410_CTL_2_RSEN (1<<2) |
55 | #define TFP410_CTL_2_HTPLG (1<<1) |
55 | #define TFP410_CTL_2_HTPLG (1<<1) |
56 | #define TFP410_CTL_2_MDI (1<<0) |
56 | #define TFP410_CTL_2_MDI (1<<0) |
Line 57... | Line 57... | ||
57 | 57 | ||
58 | #define TFP410_CTL_3 0x0A |
58 | #define TFP410_CTL_3 0x0A |
59 | #define TFP410_CTL_3_DK_MASK (0x7<<5) |
59 | #define TFP410_CTL_3_DK_MASK (0x7<<5) |
60 | #define TFP410_CTL_3_DK (1<<5) |
60 | #define TFP410_CTL_3_DK (1<<5) |
61 | #define TFP410_CTL_3_DKEN (1<<4) |
61 | #define TFP410_CTL_3_DKEN (1<<4) |
62 | #define TFP410_CTL_3_CTL_MASK (0x7<<1) |
62 | #define TFP410_CTL_3_CTL_MASK (0x7<<1) |
Line 116... | Line 116... | ||
116 | out_buf[1] = 0; |
116 | out_buf[1] = 0; |
Line 117... | Line 117... | ||
117 | 117 | ||
118 | if (i2c_transfer(adapter, msgs, 2) == 2) { |
118 | if (i2c_transfer(adapter, msgs, 2) == 2) { |
119 | *ch = in_buf[0]; |
119 | *ch = in_buf[0]; |
120 | return true; |
120 | return true; |
Line 121... | Line 121... | ||
121 | }; |
121 | } |
122 | 122 | ||
123 | if (!tfp->quiet) { |
123 | if (!tfp->quiet) { |
124 | DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n", |
124 | DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n", |
Line 223... | Line 223... | ||
223 | 223 | ||
224 | static void tfp410_mode_set(struct intel_dvo_device *dvo, |
224 | static void tfp410_mode_set(struct intel_dvo_device *dvo, |
225 | struct drm_display_mode *mode, |
225 | struct drm_display_mode *mode, |
226 | struct drm_display_mode *adjusted_mode) |
226 | struct drm_display_mode *adjusted_mode) |
227 | { |
227 | { |
228 | /* As long as the basics are set up, since we don't have clock dependencies |
228 | /* As long as the basics are set up, since we don't have clock dependencies |
229 | * in the mode setup, we can just leave the registers alone and everything |
229 | * in the mode setup, we can just leave the registers alone and everything |
230 | * will work fine. |
230 | * will work fine. |
231 | */ |
231 | */ |
232 | /* don't do much */ |
232 | /* don't do much */ |
233 | return; |
233 | return; |
Line 234... | Line 234... | ||
234 | } |
234 | } |
235 | 235 | ||
236 | /* set the tfp410 power state */ |
236 | /* set the tfp410 power state */ |
Line 265... | Line 265... | ||
265 | static void tfp410_dump_regs(struct intel_dvo_device *dvo) |
265 | static void tfp410_dump_regs(struct intel_dvo_device *dvo) |
266 | { |
266 | { |
267 | uint8_t val, val2; |
267 | uint8_t val, val2; |
Line 268... | Line 268... | ||
268 | 268 | ||
269 | tfp410_readb(dvo, TFP410_REV, &val); |
269 | tfp410_readb(dvo, TFP410_REV, &val); |
270 | DRM_LOG_KMS("TFP410_REV: 0x%02X\n", val); |
270 | DRM_DEBUG_KMS("TFP410_REV: 0x%02X\n", val); |
271 | tfp410_readb(dvo, TFP410_CTL_1, &val); |
271 | tfp410_readb(dvo, TFP410_CTL_1, &val); |
272 | DRM_LOG_KMS("TFP410_CTL1: 0x%02X\n", val); |
272 | DRM_DEBUG_KMS("TFP410_CTL1: 0x%02X\n", val); |
273 | tfp410_readb(dvo, TFP410_CTL_2, &val); |
273 | tfp410_readb(dvo, TFP410_CTL_2, &val); |
274 | DRM_LOG_KMS("TFP410_CTL2: 0x%02X\n", val); |
274 | DRM_DEBUG_KMS("TFP410_CTL2: 0x%02X\n", val); |
275 | tfp410_readb(dvo, TFP410_CTL_3, &val); |
275 | tfp410_readb(dvo, TFP410_CTL_3, &val); |
276 | DRM_LOG_KMS("TFP410_CTL3: 0x%02X\n", val); |
276 | DRM_DEBUG_KMS("TFP410_CTL3: 0x%02X\n", val); |
277 | tfp410_readb(dvo, TFP410_USERCFG, &val); |
277 | tfp410_readb(dvo, TFP410_USERCFG, &val); |
278 | DRM_LOG_KMS("TFP410_USERCFG: 0x%02X\n", val); |
278 | DRM_DEBUG_KMS("TFP410_USERCFG: 0x%02X\n", val); |
279 | tfp410_readb(dvo, TFP410_DE_DLY, &val); |
279 | tfp410_readb(dvo, TFP410_DE_DLY, &val); |
280 | DRM_LOG_KMS("TFP410_DE_DLY: 0x%02X\n", val); |
280 | DRM_DEBUG_KMS("TFP410_DE_DLY: 0x%02X\n", val); |
281 | tfp410_readb(dvo, TFP410_DE_CTL, &val); |
281 | tfp410_readb(dvo, TFP410_DE_CTL, &val); |
282 | DRM_LOG_KMS("TFP410_DE_CTL: 0x%02X\n", val); |
282 | DRM_DEBUG_KMS("TFP410_DE_CTL: 0x%02X\n", val); |
283 | tfp410_readb(dvo, TFP410_DE_TOP, &val); |
283 | tfp410_readb(dvo, TFP410_DE_TOP, &val); |
284 | DRM_LOG_KMS("TFP410_DE_TOP: 0x%02X\n", val); |
284 | DRM_DEBUG_KMS("TFP410_DE_TOP: 0x%02X\n", val); |
285 | tfp410_readb(dvo, TFP410_DE_CNT_LO, &val); |
285 | tfp410_readb(dvo, TFP410_DE_CNT_LO, &val); |
286 | tfp410_readb(dvo, TFP410_DE_CNT_HI, &val2); |
286 | tfp410_readb(dvo, TFP410_DE_CNT_HI, &val2); |
287 | DRM_LOG_KMS("TFP410_DE_CNT: 0x%02X%02X\n", val2, val); |
287 | DRM_DEBUG_KMS("TFP410_DE_CNT: 0x%02X%02X\n", val2, val); |
288 | tfp410_readb(dvo, TFP410_DE_LIN_LO, &val); |
288 | tfp410_readb(dvo, TFP410_DE_LIN_LO, &val); |
289 | tfp410_readb(dvo, TFP410_DE_LIN_HI, &val2); |
289 | tfp410_readb(dvo, TFP410_DE_LIN_HI, &val2); |
290 | DRM_LOG_KMS("TFP410_DE_LIN: 0x%02X%02X\n", val2, val); |
290 | DRM_DEBUG_KMS("TFP410_DE_LIN: 0x%02X%02X\n", val2, val); |
291 | tfp410_readb(dvo, TFP410_H_RES_LO, &val); |
291 | tfp410_readb(dvo, TFP410_H_RES_LO, &val); |
292 | tfp410_readb(dvo, TFP410_H_RES_HI, &val2); |
292 | tfp410_readb(dvo, TFP410_H_RES_HI, &val2); |
293 | DRM_LOG_KMS("TFP410_H_RES: 0x%02X%02X\n", val2, val); |
293 | DRM_DEBUG_KMS("TFP410_H_RES: 0x%02X%02X\n", val2, val); |
294 | tfp410_readb(dvo, TFP410_V_RES_LO, &val); |
294 | tfp410_readb(dvo, TFP410_V_RES_LO, &val); |
295 | tfp410_readb(dvo, TFP410_V_RES_HI, &val2); |
295 | tfp410_readb(dvo, TFP410_V_RES_HI, &val2); |
296 | DRM_LOG_KMS("TFP410_V_RES: 0x%02X%02X\n", val2, val); |
296 | DRM_DEBUG_KMS("TFP410_V_RES: 0x%02X%02X\n", val2, val); |
Line 297... | Line 297... | ||
297 | } |
297 | } |
298 | 298 | ||
299 | static void tfp410_destroy(struct intel_dvo_device *dvo) |
299 | static void tfp410_destroy(struct intel_dvo_device *dvo) |