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Rev 3031 | Rev 5060 | ||
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Line 193... | Line 193... | ||
193 | out_buf[0] = addr; |
193 | out_buf[0] = addr; |
Line 194... | Line 194... | ||
194 | 194 | ||
195 | if (i2c_transfer(adapter, msgs, 3) == 3) { |
195 | if (i2c_transfer(adapter, msgs, 3) == 3) { |
196 | *data = (in_buf[1] << 8) | in_buf[0]; |
196 | *data = (in_buf[1] << 8) | in_buf[0]; |
197 | return true; |
197 | return true; |
Line 198... | Line 198... | ||
198 | }; |
198 | } |
199 | 199 | ||
200 | if (!priv->quiet) { |
200 | if (!priv->quiet) { |
201 | DRM_DEBUG_KMS("Unable to read register 0x%02x from " |
201 | DRM_DEBUG_KMS("Unable to read register 0x%02x from " |
Line 375... | Line 375... | ||
375 | static void ivch_dump_regs(struct intel_dvo_device *dvo) |
375 | static void ivch_dump_regs(struct intel_dvo_device *dvo) |
376 | { |
376 | { |
377 | uint16_t val; |
377 | uint16_t val; |
Line 378... | Line 378... | ||
378 | 378 | ||
379 | ivch_read(dvo, VR00, &val); |
379 | ivch_read(dvo, VR00, &val); |
380 | DRM_LOG_KMS("VR00: 0x%04x\n", val); |
380 | DRM_DEBUG_KMS("VR00: 0x%04x\n", val); |
381 | ivch_read(dvo, VR01, &val); |
381 | ivch_read(dvo, VR01, &val); |
382 | DRM_LOG_KMS("VR01: 0x%04x\n", val); |
382 | DRM_DEBUG_KMS("VR01: 0x%04x\n", val); |
383 | ivch_read(dvo, VR30, &val); |
383 | ivch_read(dvo, VR30, &val); |
384 | DRM_LOG_KMS("VR30: 0x%04x\n", val); |
384 | DRM_DEBUG_KMS("VR30: 0x%04x\n", val); |
385 | ivch_read(dvo, VR40, &val); |
385 | ivch_read(dvo, VR40, &val); |
Line 386... | Line 386... | ||
386 | DRM_LOG_KMS("VR40: 0x%04x\n", val); |
386 | DRM_DEBUG_KMS("VR40: 0x%04x\n", val); |
387 | 387 | ||
388 | /* GPIO registers */ |
388 | /* GPIO registers */ |
389 | ivch_read(dvo, VR80, &val); |
389 | ivch_read(dvo, VR80, &val); |
390 | DRM_LOG_KMS("VR80: 0x%04x\n", val); |
390 | DRM_DEBUG_KMS("VR80: 0x%04x\n", val); |
391 | ivch_read(dvo, VR81, &val); |
391 | ivch_read(dvo, VR81, &val); |
392 | DRM_LOG_KMS("VR81: 0x%04x\n", val); |
392 | DRM_DEBUG_KMS("VR81: 0x%04x\n", val); |
393 | ivch_read(dvo, VR82, &val); |
393 | ivch_read(dvo, VR82, &val); |
394 | DRM_LOG_KMS("VR82: 0x%04x\n", val); |
394 | DRM_DEBUG_KMS("VR82: 0x%04x\n", val); |
395 | ivch_read(dvo, VR83, &val); |
395 | ivch_read(dvo, VR83, &val); |
396 | DRM_LOG_KMS("VR83: 0x%04x\n", val); |
396 | DRM_DEBUG_KMS("VR83: 0x%04x\n", val); |
397 | ivch_read(dvo, VR84, &val); |
397 | ivch_read(dvo, VR84, &val); |
398 | DRM_LOG_KMS("VR84: 0x%04x\n", val); |
398 | DRM_DEBUG_KMS("VR84: 0x%04x\n", val); |
399 | ivch_read(dvo, VR85, &val); |
399 | ivch_read(dvo, VR85, &val); |
400 | DRM_LOG_KMS("VR85: 0x%04x\n", val); |
400 | DRM_DEBUG_KMS("VR85: 0x%04x\n", val); |
401 | ivch_read(dvo, VR86, &val); |
401 | ivch_read(dvo, VR86, &val); |
402 | DRM_LOG_KMS("VR86: 0x%04x\n", val); |
402 | DRM_DEBUG_KMS("VR86: 0x%04x\n", val); |
403 | ivch_read(dvo, VR87, &val); |
403 | ivch_read(dvo, VR87, &val); |
404 | DRM_LOG_KMS("VR87: 0x%04x\n", val); |
404 | DRM_DEBUG_KMS("VR87: 0x%04x\n", val); |
Line 405... | Line 405... | ||
405 | ivch_read(dvo, VR88, &val); |
405 | ivch_read(dvo, VR88, &val); |
406 | DRM_LOG_KMS("VR88: 0x%04x\n", val); |
406 | DRM_DEBUG_KMS("VR88: 0x%04x\n", val); |
407 | 407 | ||
Line 408... | Line 408... | ||
408 | /* Scratch register 0 - AIM Panel type */ |
408 | /* Scratch register 0 - AIM Panel type */ |
409 | ivch_read(dvo, VR8E, &val); |
409 | ivch_read(dvo, VR8E, &val); |
410 | DRM_LOG_KMS("VR8E: 0x%04x\n", val); |
410 | DRM_DEBUG_KMS("VR8E: 0x%04x\n", val); |
411 | 411 | ||
Line 412... | Line 412... | ||
412 | /* Scratch register 1 - Status register */ |
412 | /* Scratch register 1 - Status register */ |
413 | ivch_read(dvo, VR8F, &val); |
413 | ivch_read(dvo, VR8F, &val); |
414 | DRM_LOG_KMS("VR8F: 0x%04x\n", val); |
414 | DRM_DEBUG_KMS("VR8F: 0x%04x\n", val); |