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/* GT PTE cache control fields */

#define GEN6_PTE_UNCACHED	0x00000002

#define HSW_PTE_UNCACHED	0x00000000

#define GEN6_PTE_LLC		0x00000004

#define GEN6_PTE_LLC_MLC	0x00000006

#define GEN6_PTE_GFDT		0x00000008

#define GFX_FLSH_CNTL		0x2170 /* 915+ */

#define SNB_GMCH_CTRL	0x50

#define SNB_GMCH_GMS_STOLEN_MASK	0xF8

#define SNB_GMCH_GMS_STOLEN_32M		(1 << 3)

#define SNB_GMCH_GMS_STOLEN_64M		(2 << 3)

#define SNB_GMCH_GMS_STOLEN_96M		(3 << 3)

#define SNB_GMCH_GMS_STOLEN_128M	(4 << 3)

#define SNB_GMCH_GMS_STOLEN_160M	(5 << 3)

#define SNB_GMCH_GMS_STOLEN_192M	(6 << 3)

#define SNB_GMCH_GMS_STOLEN_224M	(7 << 3)

#define SNB_GMCH_GMS_STOLEN_256M	(8 << 3)

#define SNB_GMCH_GMS_STOLEN_288M	(9 << 3)

#define SNB_GMCH_GMS_STOLEN_320M	(0xa << 3)

#define SNB_GMCH_GMS_STOLEN_352M	(0xb << 3)

#define SNB_GMCH_GMS_STOLEN_384M	(0xc << 3)

#define SNB_GMCH_GMS_STOLEN_416M	(0xd << 3)

#define SNB_GMCH_GMS_STOLEN_448M	(0xe << 3)

#define SNB_GMCH_GMS_STOLEN_480M	(0xf << 3)

#define SNB_GMCH_GMS_STOLEN_512M	(0x10 << 3)

#define SNB_GTT_SIZE_0M			(0 << 8)

#define SNB_GTT_SIZE_1M			(1 << 8)

#define SNB_GTT_SIZE_2M			(2 << 8)

#define SNB_GTT_SIZE_MASK		(3 << 8)

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB		0x0100  /* Desktop */

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG		0x0102

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG		0x0112

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG	0x0122

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB		0x0104  /* Mobile */

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG	0x0106

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG	0x0116

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG	0x0126

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB		0x0108  /* Server */

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG		0x010A

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB		0x0150  /* Desktop */

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG		0x0152

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG		0x0162

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB		0x0154  /* Mobile */

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG		0x0156

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG		0x0166

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB		0x0158  /* Server */

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG		0x015A

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG		0x016A

#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB		0x0F00 /* VLV1 */

#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG		0x0F30

#define PCI_DEVICE_ID_INTEL_HASWELL_HB			0x0400 /* Desktop */

#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG		0x0402

#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG		0x0412

#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG	0x0422

#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB		0x0404 /* Mobile */

#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG		0x0406

#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG		0x0416

#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG	0x0426

#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB		0x0408 /* Server */

#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG		0x040a

#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG		0x041a

#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG	0x042a

#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB		0x0c04

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG	0x0C02

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG	0x0C12

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG	0x0C22

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG	0x0C06

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG	0x0C16

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG	0x0C26

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG	0x0C0A

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG	0x0C1A

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG	0x0C2A

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG	0x0A02

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG	0x0A12

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG	0x0A22

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG	0x0A06

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG	0x0A16

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG	0x0A26

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG	0x0A0A

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG	0x0A1A

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG	0x0A2A

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG	0x0D12

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG	0x0D22

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG	0x0D32

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG	0x0D16

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG	0x0D26

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG	0x0D36

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG	0x0D1A

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG	0x0D2A

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG	0x0D3A