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#include
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#include
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#include
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#include
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extern int x86_clflush_size;
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#if defined(CONFIG_X86)
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/*
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extern int x86_clflush_size;
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 * clflushopt is an unordered instruction which needs fencing with mfence or
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 * sfence to avoid ordering issues.  For drm_clflush_page this fencing happens
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 * in the caller.
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#if 0
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 */
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static void
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static void
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drm_clflush_page(struct page *page)
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drm_clflush_page(struct page *page)
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#endif
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#endif
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void
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void
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drm_clflush_pages(struct page *pages[], unsigned long num_pages)
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drm_clflush_pages(struct page *pages[], unsigned long num_pages)
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{
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    uint8_t *pva;
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{
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    unsigned int i, j;
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#if defined(CONFIG_X86)
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	drm_cache_flush_clflush(pages, num_pages);
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    pva = AllocKernelSpace(4096);
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	return;
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#elif defined(__powerpc__)
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    if(pva != NULL)
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	unsigned long i;
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    {
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	for (i = 0; i < num_pages; i++) {
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        dma_addr_t *src, *dst;
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		struct page *page = pages[i];
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		void *page_virtual;
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        u32 count;
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		if (unlikely(page == NULL))
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        for (i = 0; i < num_pages; i++)
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        {
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			continue;
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            mb();
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            MapPage(pva, page_to_phys(pages[i]), 0x001);
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            for (j = 0; j < PAGE_SIZE; j += x86_clflush_size)
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		page_virtual = kmap_atomic(page);
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		flush_dcache_range((unsigned long)page_virtual,
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				   (unsigned long)page_virtual + PAGE_SIZE);
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                clflush(pva + j);
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		kunmap_atomic(page_virtual);
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	}
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        }
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#else
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        FreeKernelSpace(pva);
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	printk(KERN_ERR "Architecture has no drm_cache.c support\n");
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    }
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	WARN_ON_ONCE(1);
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    mb();
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#endif
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}
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}
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EXPORT_SYMBOL(drm_clflush_pages);
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EXPORT_SYMBOL(drm_clflush_pages);
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void
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void
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drm_clflush_sg(struct sg_table *st)
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{
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    struct sg_page_iter sg_iter;
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    struct page *page;
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    uint8_t *pva;
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drm_clflush_sg(struct sg_table *st)
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    unsigned int i;
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{
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    pva = AllocKernelSpace(4096);
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#if defined(CONFIG_X86)
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	if (cpu_has_clflush) {
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    if( pva != NULL)
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		struct sg_page_iter sg_iter;
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    {
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		mb();
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        mb();
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		for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
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        for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
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			drm_clflush_page(sg_page_iter_page(&sg_iter));
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        {
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		mb();
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            page = sg_page_iter_page(&sg_iter);
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		return;
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            MapPage(pva,page_to_phys(page), 0x001);
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	}
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            for (i = 0; i < PAGE_SIZE; i += x86_clflush_size)
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                clflush(pva + i);
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	if (wbinvd_on_all_cpus())
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        };
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		printk(KERN_ERR "Timed out waiting for cache flush.\n");
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        FreeKernelSpace(pva);
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#else
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    };
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	printk(KERN_ERR "Architecture has no drm_cache.c support\n");
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    mb();
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	WARN_ON_ONCE(1);
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}
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#endif
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EXPORT_SYMBOL(drm_clflush_sg);
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}
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EXPORT_SYMBOL(drm_clflush_sg);
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#if 0
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void
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void
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drm_clflush_virt_range(void *addr, unsigned long length)
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drm_clflush_virt_range(void *addr, unsigned long length)
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{
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{
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#if defined(CONFIG_X86)
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#if defined(CONFIG_X86)
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	if (cpu_has_clflush) {
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	if (1) {
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		const int size = boot_cpu_data.x86_clflush_size;
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		void *end = addr + length;
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		addr = (void *)(((unsigned long)addr) & -size);
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		const int size = x86_clflush_size;
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		mb();
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		void *end = addr + length;
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		for (; addr < end; addr += size)
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		addr = (void *)(((unsigned long)addr) & -size);
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			clflushopt(addr);
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		mb();
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		mb();
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		for (; addr < end; addr += size)
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		return;
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			clflush(addr);
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	}
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