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| - | 1 | /************************************************************************** |
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| Line -... | Line 2... | ||
| - | 2 | ||
| - | 3 | Copyright 2001 VA Linux Systems Inc., Fremont, California. |
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| - | 4 | Copyright © 2002 by David Dawes |
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| - | 5 | ||
| - | 6 | All Rights Reserved. |
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| - | 7 | ||
| - | 8 | Permission is hereby granted, free of charge, to any person obtaining a |
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| - | 9 | copy of this software and associated documentation files (the "Software"), |
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| - | 10 | to deal in the Software without restriction, including without limitation |
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| - | 11 | on the rights to use, copy, modify, merge, publish, distribute, sub |
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| - | 12 | license, and/or sell copies of the Software, and to permit persons to whom |
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| - | 13 | the Software is furnished to do so, subject to the following conditions: |
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| - | 14 | ||
| - | 15 | The above copyright notice and this permission notice (including the next |
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| - | 16 | paragraph) shall be included in all copies or substantial portions of the |
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| - | 17 | Software. |
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| - | 18 | ||
| - | 19 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| - | 20 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| - | 21 | FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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| - | 22 | THE COPYRIGHT HOLDERS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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| - | 23 | DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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| - | 24 | OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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| - | 25 | USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| - | 26 | ||
| - | 27 | **************************************************************************/ |
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| - | 28 | ||
| - | 29 | /* |
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| - | 30 | * Authors: Jeff Hartmann |
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| - | 31 | * Abraham van der Merwe |
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| - | 32 | * David Dawes |
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| - | 33 | * Alan Hourihane |
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| - | 34 | */ |
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| - | 35 | ||
| - | 36 | #ifdef HAVE_CONFIG_H |
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| - | 37 | #include "config.h" |
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| Line 1... | Line 38... | ||
| 1 | #include |
38 | #endif |
| 2 | #include |
39 | |
| 3 | #include |
40 | #include |
| 4 | #include |
41 | #include |
| - | 42 | #include |
|
| Line -... | Line 43... | ||
| - | 43 | #include |
|
| 5 | 44 | #include "i915_pciids.h" |
|
| - | 45 | ||
| Line 6... | Line 46... | ||
| 6 | #include "sna.h" |
46 | #include "compiler.h" |
| Line 7... | Line 47... | ||
| 7 | 47 | #include "sna.h" |
|
| 8 | #define to_surface(x) (surface_t*)((x)->handle) |
48 | #include "intel_driver.h" |
| Line 44... | Line 84... | ||
| 44 | uint32_t kgem_surface_size(struct kgem *kgem,bool relaxed_fencing, |
84 | int kgem_init_fb(struct kgem *kgem, struct sna_fb *fb); |
| 45 | unsigned flags, uint32_t width, uint32_t height, |
85 | int kgem_update_fb(struct kgem *kgem, struct sna_fb *fb); |
| 46 | uint32_t bpp, uint32_t tiling, uint32_t *pitch); |
86 | uint32_t kgem_surface_size(struct kgem *kgem,bool relaxed_fencing, |
| 47 | 87 | unsigned flags, uint32_t width, uint32_t height, |
|
| 48 | void kgem_close_batches(struct kgem *kgem); |
88 | uint32_t bpp, uint32_t tiling, uint32_t *pitch); |
| - | 89 | struct kgem_bo *kgem_bo_from_handle(struct kgem *kgem, int handle, |
|
| - | 90 | int pitch, int height); |
|
| Line 49... | Line 91... | ||
| 49 | void sna_bo_destroy(struct kgem *kgem, struct kgem_bo *bo); |
91 | |
| 50 | 92 | void kgem_close_batches(struct kgem *kgem); |
|
| Line 51... | Line 93... | ||
| 51 | const struct intel_device_info * |
93 | void sna_bo_destroy(struct kgem *kgem, struct kgem_bo *bo); |
| 52 | intel_detect_chipset(struct pci_device *pci); |
94 | |
| Line 53... | Line -... | ||
| 53 | - | ||
| 54 | //struct kgem_bo *create_bo(bitmap_t *bitmap); |
- | |
| 55 | 95 | const struct intel_device_info * |
|
| Line 56... | Line 96... | ||
| 56 | static bool sna_solid_cache_init(struct sna *sna); |
96 | intel_detect_chipset(struct pci_device *pci); |
| Line 57... | Line 97... | ||
| 57 | 97 | ||
| Line 64... | Line 104... | ||
| 64 | (void)sna; |
104 | static void no_render_reset(struct sna *sna) |
| 65 | } |
105 | { |
| 66 | 106 | (void)sna; |
|
| 67 | void no_render_init(struct sna *sna) |
107 | } |
| Line -... | Line 108... | ||
| - | 108 | ||
| - | 109 | static void no_render_flush(struct sna *sna) |
|
| - | 110 | { |
|
| - | 111 | (void)sna; |
|
| - | 112 | } |
|
| - | 113 | ||
| - | 114 | static void |
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| - | 115 | no_render_context_switch(struct kgem *kgem, |
|
| - | 116 | int new_mode) |
|
| - | 117 | { |
|
| - | 118 | if (!kgem->nbatch) |
|
| - | 119 | return; |
|
| - | 120 | ||
| - | 121 | if (kgem_ring_is_idle(kgem, kgem->ring)) { |
|
| - | 122 | DBG(("%s: GPU idle, flushing\n", __FUNCTION__)); |
|
| - | 123 | _kgem_submit(kgem); |
|
| - | 124 | } |
|
| - | 125 | ||
| - | 126 | (void)new_mode; |
|
| - | 127 | } |
|
| - | 128 | ||
| - | 129 | static void |
|
| - | 130 | no_render_retire(struct kgem *kgem) |
|
| - | 131 | { |
|
| - | 132 | (void)kgem; |
|
| - | 133 | } |
|
| - | 134 | ||
| - | 135 | static void |
|
| - | 136 | no_render_expire(struct kgem *kgem) |
|
| - | 137 | { |
|
| - | 138 | (void)kgem; |
|
| - | 139 | } |
|
| - | 140 | ||
| 68 | { |
141 | static void |
| - | 142 | no_render_fini(struct sna *sna) |
|
| - | 143 | { |
|
| - | 144 | (void)sna; |
|
| - | 145 | } |
|
| - | 146 | ||
| 69 | struct sna_render *render = &sna->render; |
147 | const char *no_render_init(struct sna *sna) |
| 70 | 148 | { |
|
| Line 71... | Line 149... | ||
| 71 | memset (render,0, sizeof (*render)); |
149 | struct sna_render *render = &sna->render; |
| Line 72... | Line 150... | ||
| 72 | 150 | ||
| Line 73... | Line 151... | ||
| 73 | render->prefer_gpu = PREFER_GPU_BLT; |
151 | memset (render,0, sizeof (*render)); |
| 74 | 152 | ||
| Line 75... | Line -... | ||
| 75 | render->vertices = render->vertex_data; |
- | |
| 76 | render->vertex_size = ARRAY_SIZE(render->vertex_data); |
- | |
| 77 | - | ||
| 78 | // render->composite = no_render_composite; |
- | |
| 79 | - | ||
| 80 | // render->copy_boxes = no_render_copy_boxes; |
- | |
| 81 | // render->copy = no_render_copy; |
- | |
| 82 | - | ||
| 83 | // render->fill_boxes = no_render_fill_boxes; |
- | |
| 84 | // render->fill = no_render_fill; |
- | |
| 85 | // render->fill_one = no_render_fill_one; |
153 | render->prefer_gpu = PREFER_GPU_BLT; |
| 86 | // render->clear = no_render_clear; |
154 | |
| 87 | 155 | render->vertices = render->vertex_data; |
|
| Line 88... | Line 156... | ||
| 88 | render->reset = no_render_reset; |
156 | render->vertex_size = ARRAY_SIZE(render->vertex_data); |
| 89 | // render->flush = no_render_flush; |
157 | |
| - | 158 | render->reset = no_render_reset; |
|
| Line 90... | Line 159... | ||
| 90 | // render->fini = no_render_fini; |
159 | render->flush = no_render_flush; |
| 91 | 160 | render->fini = no_render_fini; |
|
| Line 92... | Line 161... | ||
| 92 | // sna->kgem.context_switch = no_render_context_switch; |
161 | |
| - | 162 | sna->kgem.context_switch = no_render_context_switch; |
|
| 93 | // sna->kgem.retire = no_render_retire; |
163 | sna->kgem.retire = no_render_retire; |
| Line 94... | Line 164... | ||
| 94 | 164 | sna->kgem.expire = no_render_expire; |
|
| 95 | if (sna->kgem.gen >= 60) |
165 | |
| 96 | sna->kgem.ring = KGEM_RENDER; |
166 | sna->kgem.mode = KGEM_RENDER; |
| Line 109... | Line 179... | ||
| 109 | { |
179 | |
| 110 | const char *backend; |
180 | int sna_accel_init(struct sna *sna) |
| 111 | 181 | { |
|
| Line 112... | Line -... | ||
| 112 | // list_init(&sna->deferred_free); |
- | |
| 113 | // list_init(&sna->dirty_pixmaps); |
- | |
| 114 | // list_init(&sna->active_pixmaps); |
- | |
| 115 | // list_init(&sna->inactive_clock[0]); |
- | |
| 116 | // list_init(&sna->inactive_clock[1]); |
- | |
| 117 | - | ||
| 118 | // sna_accel_install_timers(sna); |
- | |
| 119 | - | ||
| 120 | - | ||
| 121 | backend = "no"; |
- | |
| 122 | no_render_init(sna); |
182 | const char *backend; |
| 123 | - | ||
| 124 | if (sna->info->gen >= 0100) { |
183 | |
| - | 184 | backend = no_render_init(sna); |
|
| 125 | } else if (sna->info->gen >= 070) { |
185 | if (sna->info->gen >= 0100) |
| 126 | if (gen7_render_init(sna)) |
186 | (void)backend; |
| 127 | backend = "IvyBridge"; |
- | |
| 128 | } else if (sna->info->gen >= 060) { |
187 | else if (sna->info->gen >= 070) |
| 129 | if (gen6_render_init(sna)) |
188 | backend = gen7_render_init(sna, backend); |
| 130 | backend = "SandyBridge"; |
- | |
| 131 | } else if (sna->info->gen >= 050) { |
189 | else if (sna->info->gen >= 060) |
| 132 | if (gen5_render_init(sna)) |
190 | backend = gen6_render_init(sna, backend); |
| 133 | backend = "Ironlake"; |
- | |
| 134 | } else if (sna->info->gen >= 040) { |
191 | else if (sna->info->gen >= 050) |
| 135 | if (gen4_render_init(sna)) |
192 | backend = gen5_render_init(sna, backend); |
| 136 | backend = "Broadwater/Crestline"; |
- | |
| 137 | } else if (sna->info->gen >= 030) { |
193 | else if (sna->info->gen >= 040) |
| 138 | if (gen3_render_init(sna)) |
194 | backend = gen4_render_init(sna, backend); |
| 139 | backend = "gen3"; |
- | |
| 140 | } |
- | |
| Line 141... | Line 195... | ||
| 141 | 195 | else if (sna->info->gen >= 030) |
|
| 142 | DBG(("%s(backend=%s, prefer_gpu=%x)\n", |
196 | backend = gen3_render_init(sna, backend); |
| Line 143... | Line 197... | ||
| 143 | __FUNCTION__, backend, sna->render.prefer_gpu)); |
197 | |
| Line 144... | Line -... | ||
| 144 | - | ||
| 145 | kgem_reset(&sna->kgem); |
- | |
| 146 | - | ||
| 147 | // if (!sna_solid_cache_init(sna)) |
198 | DBG(("%s(backend=%s, prefer_gpu=%x)\n", |
| Line 148... | Line -... | ||
| 148 | // return false; |
- | |
| 149 | 199 | __FUNCTION__, backend, sna->render.prefer_gpu)); |
|
| 150 | sna_device = sna; |
200 | |
| Line 151... | Line 201... | ||
| 151 | 201 | kgem_reset(&sna->kgem); |
|
| 152 | 202 | ||
| Line 184... | Line 234... | ||
| 184 | 234 | if (sna == NULL) |
|
| 185 | memset(sna, 0, sizeof(*sna)); |
235 | goto err1; |
| Line 186... | Line 236... | ||
| 186 | 236 | ||
| Line 187... | Line 237... | ||
| 187 | sna->PciInfo = &device; |
237 | memset(sna, 0, sizeof(*sna)); |
| Line -... | Line 238... | ||
| - | 238 | ||
| 188 | 239 | sna->cpu_features = sna_cpu_detect(); |
|
| - | 240 | ||
| Line 189... | Line 241... | ||
| 189 | sna->info = intel_detect_chipset(sna->PciInfo); |
241 | sna->PciInfo = &device; |
| Line 190... | Line -... | ||
| 190 | - | ||
| 191 | kgem_init(&sna->kgem, service, sna->PciInfo, sna->info->gen); |
- | |
| 192 | - | ||
| 193 | /* |
- | |
| 194 | if (!xf86ReturnOptValBool(sna->Options, |
- | |
| 195 | OPTION_RELAXED_FENCING, |
- | |
| 196 | sna->kgem.has_relaxed_fencing)) { |
- | |
| 197 | xf86DrvMsg(scrn->scrnIndex, |
- | |
| 198 | sna->kgem.has_relaxed_fencing ? X_CONFIG : X_PROBED, |
- | |
| 199 | "Disabling use of relaxed fencing\n"); |
- | |
| 200 | sna->kgem.has_relaxed_fencing = 0; |
- | |
| 201 | } |
- | |
| 202 | if (!xf86ReturnOptValBool(sna->Options, |
- | |
| 203 | OPTION_VMAP, |
- | |
| 204 | sna->kgem.has_vmap)) { |
- | |
| 205 | xf86DrvMsg(scrn->scrnIndex, |
- | |
| 206 | sna->kgem.has_vmap ? X_CONFIG : X_PROBED, |
- | |
| 207 | "Disabling use of vmap\n"); |
- | |
| Line 208... | Line 242... | ||
| 208 | sna->kgem.has_vmap = 0; |
242 | sna->info = intel_detect_chipset(sna->PciInfo); |
| 209 | } |
243 | sna->scrn = service; |
| Line 210... | Line 244... | ||
| 210 | */ |
244 | |
| 211 | 245 | kgem_init(&sna->kgem, service, sna->PciInfo, sna->info->gen); |
|
| Line 212... | Line 246... | ||
| 212 | /* Disable tiling by default */ |
246 | |
| Line 488... | Line 522... | ||
| 488 | return -1; |
522 | free(sf); |
| 489 | }; |
523 | err_1: |
| 490 | 524 | return -1; |
|
| 491 | int sna_destroy_bitmap(bitmap_t *bitmap) |
525 | }; |
| Line -... | Line 526... | ||
| - | 526 | ||
| - | 527 | int sna_bitmap_from_handle(bitmap_t *bitmap, uint32_t handle) |
|
| - | 528 | { |
|
| - | 529 | surface_t *sf; |
|
| - | 530 | struct kgem_bo *bo; |
|
| - | 531 | ||
| - | 532 | sf = malloc(sizeof(*sf)); |
|
| - | 533 | if(sf == NULL) |
|
| - | 534 | goto err_1; |
|
| - | 535 | ||
| - | 536 | __lock_acquire_recursive(__sna_lock); |
|
| - | 537 | ||
| - | 538 | bo = kgem_bo_from_handle(&sna_device->kgem, handle, bitmap->pitch, bitmap->height); |
|
| - | 539 | ||
| - | 540 | __lock_release_recursive(__sna_lock); |
|
| - | 541 | ||
| - | 542 | sf->width = bitmap->width; |
|
| - | 543 | sf->height = bitmap->height; |
|
| - | 544 | sf->data = NULL; |
|
| - | 545 | sf->pitch = bo->pitch; |
|
| - | 546 | sf->bo = bo; |
|
| - | 547 | sf->bo_size = PAGE_SIZE * bo->size.pages.count; |
|
| - | 548 | sf->flags = bitmap->flags; |
|
| - | 549 | ||
| - | 550 | bitmap->handle = (uint32_t)sf; |
|
| - | 551 | ||
| - | 552 | return 0; |
|
| - | 553 | ||
| - | 554 | err_2: |
|
| - | 555 | __lock_release_recursive(__sna_lock); |
|
| - | 556 | free(sf); |
|
| - | 557 | err_1: |
|
| - | 558 | return -1; |
|
| - | 559 | }; |
|
| - | 560 | ||
| - | 561 | void sna_set_bo_handle(bitmap_t *bitmap, int handle) |
|
| - | 562 | { |
|
| - | 563 | surface_t *sf = to_surface(bitmap); |
|
| - | 564 | struct kgem_bo *bo = sf->bo; |
|
| - | 565 | bo->handle = handle; |
|
| - | 566 | } |
|
| 492 | { |
567 | |
| 493 | surface_t *sf = to_surface(bitmap); |
568 | int sna_destroy_bitmap(bitmap_t *bitmap) |
| 494 | 569 | { |
|
| Line 495... | Line 570... | ||
| 495 | __lock_acquire_recursive(__sna_lock); |
570 | surface_t *sf = to_surface(bitmap); |
| Line 684... | Line 759... | ||
| 684 | 759 | return -1; |
|
| 685 | VG_CLEAR(update); |
760 | } |
| Line 686... | Line 761... | ||
| 686 | update.handle = mask_bo->handle; |
761 | |
| 687 | update.bo_map = (__u32)MAP(mask_bo->map); |
762 | VG_CLEAR(update); |
| 688 | drmIoctl(sna_device->kgem.fd, SRV_MASK_UPDATE, &update); |
763 | update.handle = mask_bo->handle; |
| 689 | mask_bo->pitch = update.bo_pitch; |
764 | update.bo_map = (int)kgem_bo_map__cpu(&sna_device->kgem, mask_bo); |
| 690 | 765 | drmIoctl(sna_device->kgem.fd, SRV_MASK_UPDATE, &update); |
|
| Line 691... | Line 766... | ||
| 691 | memset(&src, 0, sizeof(src)); |
766 | mask_bo->pitch = update.bo_pitch; |
| 692 | memset(&dst, 0, sizeof(dst)); |
767 | |
| Line 754... | Line -... | ||
| 754 | - | ||
| 755 | - | ||
| 756 | 829 | ||
| 757 | 830 | ||
| 758 | 831 | ||
| Line 759... | Line 832... | ||
| 759 | static const struct intel_device_info intel_generic_info = { |
832 | |
| Line 805... | Line 878... | ||
| 805 | 878 | { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0x3 << 16, 0xff << 16, (intptr_t)(i) } |
|
| Line 806... | Line 879... | ||
| 806 | static const struct pci_id_match intel_device_match[] = { |
879 | |
| Line -... | Line 880... | ||
| - | 880 | ||
| - | 881 | static const struct pci_id_match intel_device_match[] = { |
|
| - | 882 | ||
| - | 883 | INTEL_I915G_IDS(&intel_i915_info), |
|
| Line 807... | Line -... | ||
| 807 | - | ||
| 808 | - | ||
| 809 | INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, &intel_i915_info ), |
- | |
| 810 | INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, &intel_i915_info ), |
- | |
| 811 | INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, &intel_i915_info ), |
- | |
| 812 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, &intel_i945_info ), |
- | |
| 813 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, &intel_i945_info ), |
- | |
| 814 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, &intel_i945_info ), |
- | |
| 815 | - | ||
| 816 | INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_M, &intel_g33_info ), |
884 | INTEL_I915GM_IDS(&intel_i915_info), |
| 817 | INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_G, &intel_g33_info ), |
- | |
| 818 | INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, &intel_g33_info ), |
- | |
| 819 | INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, &intel_g33_info ), |
- | |
| 820 | /* Another marketing win: Q35 is another g33 device not a gen4 part |
- | |
| 821 | * like its G35 brethren. |
885 | INTEL_I945G_IDS(&intel_i945_info), |
| Line 822... | Line -... | ||
| 822 | */ |
- | |
| 823 | INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, &intel_g33_info ), |
886 | INTEL_I945GM_IDS(&intel_i945_info), |
| 824 | 887 | ||
| 825 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, &intel_i965_info ), |
- | |
| 826 | INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, &intel_i965_info ), |
- | |
| 827 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, &intel_i965_info ), |
- | |
| 828 | INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, &intel_i965_info ), |
- | |
| 829 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, &intel_i965_info ), |
- | |
| 830 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, &intel_i965_info ), |
- | |
| 831 | - | ||
| 832 | INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, &intel_g4x_info ), |
- | |
| 833 | INTEL_DEVICE_MATCH (PCI_CHIP_G45_E_G, &intel_g4x_info ), |
- | |
| 834 | INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, &intel_g4x_info ), |
- | |
| 835 | INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, &intel_g4x_info ), |
- | |
| 836 | INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, &intel_g4x_info ), |
- | |
| 837 | INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, &intel_g4x_info ), |
- | |
| 838 | INTEL_DEVICE_MATCH (PCI_CHIP_B43_G1, &intel_g4x_info ), |
- | |
| 839 | - | ||
| 840 | INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_D_G, &intel_ironlake_info ), |
- | |
| 841 | INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_M_G, &intel_ironlake_info ), |
- | |
| 842 | - | ||
| 843 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, &intel_sandybridge_info ), |
- | |
| 844 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, &intel_sandybridge_info ), |
- | |
| 845 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, &intel_sandybridge_info ), |
- | |
| 846 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT1, &intel_sandybridge_info ), |
- | |
| 847 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2, &intel_sandybridge_info ), |
- | |
| 848 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, &intel_sandybridge_info ), |
- | |
| 849 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, &intel_sandybridge_info ), |
- | |
| 850 | - | ||
| 851 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT1, &intel_ivybridge_info ), |
- | |
| 852 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT2, &intel_ivybridge_info ), |
- | |
| 853 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT1, &intel_ivybridge_info ), |
- | |
| 854 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT2, &intel_ivybridge_info ), |
- | |
| 855 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ), |
- | |
| 856 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT2, &intel_ivybridge_info ), |
- | |
| 857 | - | ||
| 858 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT1, &intel_haswell_info ), |
- | |
| 859 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2, &intel_haswell_info ), |
- | |
| 860 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2_PLUS, &intel_haswell_info ), |
- | |
| 861 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT1, &intel_haswell_info ), |
- | |
| 862 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2, &intel_haswell_info ), |
- | |
| 863 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2_PLUS, &intel_haswell_info ), |
- | |
| 864 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ), |
- | |
| 865 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ), |
- | |
| 866 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ), |
- | |
| 867 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ), |
- | |
| 868 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ), |
- | |
| 869 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ), |
- | |
| 870 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT1, &intel_haswell_info ), |
- | |
| 871 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2, &intel_haswell_info ), |
- | |
| 872 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, &intel_haswell_info ), |
- | |
| 873 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ), |
- | |
| 874 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ), |
- | |
| 875 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ), |
- | |
| 876 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ), |
- | |
| 877 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ), |
- | |
| 878 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ), |
- | |
| 879 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT1, &intel_haswell_info ), |
- | |
| 880 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2, &intel_haswell_info ), |
- | |
| 881 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, &intel_haswell_info ), |
- | |
| 882 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ), |
- | |
| 883 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ), |
- | |
| 884 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ), |
- | |
| 885 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ), |
- | |
| 886 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ), |
- | |
| 887 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ), |
- | |
| 888 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT1, &intel_haswell_info ), |
- | |
| 889 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2, &intel_haswell_info ), |
- | |
| 890 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, &intel_haswell_info ), |
- | |
| 891 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ), |
- | |
| 892 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ), |
- | |
| 893 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ), |
- | |
| 894 | - | ||
| 895 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ), |
- | |
| Line -... | Line 888... | ||
| - | 888 | INTEL_G33_IDS(&intel_g33_info), |
|
| - | 889 | INTEL_PINEVIEW_IDS(&intel_g33_info), |
|
| - | 890 | ||
| - | 891 | INTEL_I965G_IDS(&intel_i965_info), |
|
| - | 892 | INTEL_I965GM_IDS(&intel_i965_info), |
|
| - | 893 | ||
| - | 894 | INTEL_G45_IDS(&intel_g4x_info), |
|
| - | 895 | INTEL_GM45_IDS(&intel_g4x_info), |
|
| - | 896 | ||
| - | 897 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_info), |
|
| - | 898 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_info), |
|
| - | 899 | ||
| - | 900 | INTEL_SNB_D_IDS(&intel_sandybridge_info), |
|
| - | 901 | INTEL_SNB_M_IDS(&intel_sandybridge_info), |
|
| - | 902 | ||
| - | 903 | INTEL_IVB_D_IDS(&intel_ivybridge_info), |
|
| - | 904 | INTEL_IVB_M_IDS(&intel_ivybridge_info), |
|
| - | 905 | ||
| 896 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_1, &intel_valleyview_info ), |
906 | INTEL_HSW_D_IDS(&intel_haswell_info), |
| Line 897... | Line 907... | ||
| 897 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_2, &intel_valleyview_info ), |
907 | INTEL_HSW_M_IDS(&intel_haswell_info), |
| 898 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_3, &intel_valleyview_info ), |
908 | |
| Line 899... | Line 909... | ||
| 899 | 909 | INTEL_VLV_D_IDS(&intel_valleyview_info), |
|
| Line 946... | Line 956... | ||
| 946 | 956 | scrn->chipset = name; |
|
| 947 | } |
957 | #endif |
| Line 948... | Line 958... | ||
| 948 | 958 | ||
| Line -... | Line 959... | ||
| - | 959 | } |
|
| - | 960 | ||
| - | 961 | int intel_get_device_id(int fd) |
|
| - | 962 | { |
|
| - | 963 | struct drm_i915_getparam gp; |
|
| - | 964 | int devid = 0; |
|
| - | 965 | ||
| - | 966 | memset(&gp, 0, sizeof(gp)); |
|
| - | 967 | gp.param = I915_PARAM_CHIPSET_ID; |
|
| - | 968 | gp.value = &devid; |
|
| - | 969 | ||
| - | 970 | if (drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp)) |
|
| - | 971 | return 0; |
|
| - | 972 | ||
| Line 949... | Line 973... | ||
| 949 | 973 | return devid; |
|
| 950 | int drmIoctl(int fd, unsigned long request, void *arg) |
974 | } |
| 951 | { |
975 | |