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Line 7... Line 7...
7 
 
 7 
 
8 
#define INTEL_VERSION_MAJOR PACKAGE_VERSION_MAJOR
 8 
#define INTEL_VERSION_MAJOR PACKAGE_VERSION_MAJOR
9 
#define INTEL_VERSION_MINOR PACKAGE_VERSION_MINOR
 9 
#define INTEL_VERSION_MINOR PACKAGE_VERSION_MINOR
Line 10... Line -...
10 
#define INTEL_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL
 - 
 
11 
 
 10 
#define INTEL_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL
12 
#ifndef PCI_CHIP_I810
 11 
 
13 
#define PCI_CHIP_I810              0x7121
 12 
#define PCI_CHIP_I810              0x7121
14 
#define PCI_CHIP_I810_DC100        0x7123
 13 
#define PCI_CHIP_I810_DC100        0x7123
15 
#define PCI_CHIP_I810_E            0x7125
 - 
 
16 
#define PCI_CHIP_I815              0x1132
 - 
 
17 
#define PCI_CHIP_I810_BRIDGE       0x7120
 - 
 
18 
#define PCI_CHIP_I810_DC100_BRIDGE 0x7122
 - 
 
19 
#define PCI_CHIP_I810_E_BRIDGE     0x7124
 - 
 
Line 20... Line -...
20 
#define PCI_CHIP_I815_BRIDGE       0x1130
 - 
 
21 
#endif
 14 
#define PCI_CHIP_I810_E            0x7125
22 
 
 - 
 
23 
#ifndef PCI_CHIP_I830_M
 - 
 
24 
#define PCI_CHIP_I830_M            0x3577
 - 
 
25 
#define PCI_CHIP_I830_M_BRIDGE     0x3575
 - 
 
26 
#endif
 15 
#define PCI_CHIP_I815              0x1132
27 
 
 - 
 
28 
#ifndef PCI_CHIP_845_G
 - 
 
29 
#define PCI_CHIP_845_G             0x2562
 - 
 
30 
#define PCI_CHIP_845_G_BRIDGE	   0x2560
 - 
 
31 
#endif
 16 
 
32 
 
 - 
 
33 
#ifndef PCI_CHIP_I854
 - 
 
34 
#define PCI_CHIP_I854              0x358E
 - 
 
35 
#define PCI_CHIP_I854_BRIDGE	   0x358C
 - 
 
36 
#endif
 17 
#define PCI_CHIP_I830_M            0x3577
37 
 
 - 
 
38 
#ifndef PCI_CHIP_I855_GM
 - 
 
39 
#define PCI_CHIP_I855_GM           0x3582
 - 
 
40 
#define PCI_CHIP_I855_GM_BRIDGE	   0x3580
 - 
 
41 
#endif
 18 
#define PCI_CHIP_845_G             0x2562
42 
 
 - 
 
43 
#ifndef PCI_CHIP_I865_G
 - 
 
Line 44... Line -...
44 
#define PCI_CHIP_I865_G            0x2572
 - 
 
45 
#define PCI_CHIP_I865_G_BRIDGE	   0x2570
 19 
#define PCI_CHIP_I854              0x358E
46 
#endif
 - 
 
47 
 
 - 
 
48 
#ifndef PCI_CHIP_I915_G
 - 
 
49 
#define PCI_CHIP_I915_G            0x2582
 - 
 
50 
#define PCI_CHIP_I915_G_BRIDGE	   0x2580
 20 
#define PCI_CHIP_I855_GM           0x3582
51 
#endif
 - 
 
52 
 
 - 
 
53 
#ifndef PCI_CHIP_I915_GM
 - 
 
54 
#define PCI_CHIP_I915_GM           0x2592
 - 
 
55 
#define PCI_CHIP_I915_GM_BRIDGE	   0x2590
 21 
#define PCI_CHIP_I865_G            0x2572
56 
#endif
 - 
 
57 
 
 - 
 
58 
#ifndef PCI_CHIP_E7221_G
 - 
 
59 
#define PCI_CHIP_E7221_G           0x258A
 - 
 
60 
/* Same as I915_G_BRIDGE */
 - 
 
61 
#define PCI_CHIP_E7221_G_BRIDGE	   0x2580
 22 
 
62 
#endif
 - 
 
63 
 
 - 
 
64 
#ifndef PCI_CHIP_I945_G
 - 
 
65 
#define PCI_CHIP_I945_G        0x2772
 - 
 
66 
#define PCI_CHIP_I945_G_BRIDGE 0x2770
 23 
#define PCI_CHIP_I915_G            0x2582
67 
#endif
 - 
 
68 
 
 - 
 
69 
#ifndef PCI_CHIP_I945_GM
 - 
 
70 
#define PCI_CHIP_I945_GM        0x27A2
 - 
 
71 
#define PCI_CHIP_I945_GM_BRIDGE 0x27A0
 24 
#define PCI_CHIP_I915_GM           0x2592
72 
#endif
 - 
 
73 
 
 - 
 
74 
#ifndef PCI_CHIP_I945_GME
 - 
 
75 
#define PCI_CHIP_I945_GME	 0x27AE
 - 
 
76 
#define PCI_CHIP_I945_GME_BRIDGE 0x27AC
 25 
#define PCI_CHIP_E7221_G           0x258A
77 
#endif
 - 
 
78 
 
 26 
#define PCI_CHIP_I945_G        0x2772
79 
#ifndef PCI_CHIP_PINEVIEW_M
 27 
#define PCI_CHIP_I945_GM        0x27A2
80 
#define PCI_CHIP_PINEVIEW_M		0xA011
 28 
#define PCI_CHIP_I945_GME	 0x27AE
- 
 
 29 
#define PCI_CHIP_PINEVIEW_M		0xA011
Line 81... Line -...
81 
#define PCI_CHIP_PINEVIEW_M_BRIDGE	0xA010
 - 
 
82 
#define PCI_CHIP_PINEVIEW_G		0xA001
 30 
#define PCI_CHIP_PINEVIEW_G		0xA001
83 
#define PCI_CHIP_PINEVIEW_G_BRIDGE	0xA000
 - 
 
84 
#endif
 - 
 
85 
 
 - 
 
86 
#ifndef PCI_CHIP_G35_G
 - 
 
87 
#define PCI_CHIP_G35_G		0x2982
 31 
#define PCI_CHIP_Q35_G		0x29B2
88 
#define PCI_CHIP_G35_G_BRIDGE 	0x2980
 - 
 
89 
#endif
 - 
 
90 
 
 - 
 
91 
#ifndef PCI_CHIP_I965_Q
 - 
 
92 
#define PCI_CHIP_I965_Q		0x2992
 32 
#define PCI_CHIP_G33_G		0x29C2
93 
#define PCI_CHIP_I965_Q_BRIDGE 	0x2990
 - 
 
94 
#endif
 - 
 
95 
 
 - 
 
96 
#ifndef PCI_CHIP_I965_G
 - 
 
97 
#define PCI_CHIP_I965_G		0x29A2
 33 
#define PCI_CHIP_Q33_G		0x29D2
98 
#define PCI_CHIP_I965_G_BRIDGE 	0x29A0
 - 
 
99 
#endif
 - 
 
100 
 
 - 
 
101 
#ifndef PCI_CHIP_I946_GZ
 - 
 
102 
#define PCI_CHIP_I946_GZ		0x2972
 34 
 
103 
#define PCI_CHIP_I946_GZ_BRIDGE 	0x2970
 - 
 
104 
#endif
 - 
 
105 
 
 - 
 
106 
#ifndef PCI_CHIP_I965_GM
 - 
 
107 
#define PCI_CHIP_I965_GM        0x2A02
 35 
#define PCI_CHIP_G35_G		0x2982
108 
#define PCI_CHIP_I965_GM_BRIDGE 0x2A00
 - 
 
109 
#endif
 - 
 
110 
 
 - 
 
111 
#ifndef PCI_CHIP_I965_GME
 - 
 
112 
#define PCI_CHIP_I965_GME       0x2A12
 - 
 
113 
#define PCI_CHIP_I965_GME_BRIDGE 0x2A10
 - 
 
114 
#endif
 - 
 
115 
 
 - 
 
116 
#ifndef PCI_CHIP_G33_G
 - 
 
117 
#define PCI_CHIP_G33_G		0x29C2
 - 
 
118 
#define PCI_CHIP_G33_G_BRIDGE 	0x29C0
 - 
 
119 
#endif
 - 
 
120 
 
 - 
 
121 
#ifndef PCI_CHIP_Q35_G
 - 
 
122 
#define PCI_CHIP_Q35_G		0x29B2
 - 
 
123 
#define PCI_CHIP_Q35_G_BRIDGE 	0x29B0
 - 
 
124 
#endif
 - 
 
125 
 
 - 
 
126 
#ifndef PCI_CHIP_Q33_G
 - 
 
127 
#define PCI_CHIP_Q33_G		0x29D2
 36 
#define PCI_CHIP_I965_Q		0x2992
128 
#define PCI_CHIP_Q33_G_BRIDGE 	0x29D0
 - 
 
129 
#endif
 - 
 
130 
 
 - 
 
131 
#ifndef PCI_CHIP_GM45_GM
 - 
 
132 
#define PCI_CHIP_GM45_GM	0x2A42
 37 
#define PCI_CHIP_I965_G		0x29A2
133 
#define PCI_CHIP_GM45_BRIDGE    0x2A40
 - 
 
134 
#endif
 - 
 
135 
 
 - 
 
136 
#ifndef PCI_CHIP_G45_E_G
 - 
 
137 
#define PCI_CHIP_G45_E_G	0x2E02
 38 
#define PCI_CHIP_I946_GZ		0x2972
138 
#define PCI_CHIP_G45_E_G_BRIDGE 0x2E00
 - 
 
139 
#endif
 - 
 
140 
 
 - 
 
141 
#ifndef PCI_CHIP_G45_G
 - 
 
142 
#define PCI_CHIP_G45_G		0x2E22
 39 
#define PCI_CHIP_I965_GM        0x2A02
143 
#define PCI_CHIP_G45_G_BRIDGE	0x2E20
 - 
 
144 
#endif
 - 
 
145 
 
 - 
 
146 
#ifndef PCI_CHIP_Q45_G
 - 
 
147 
#define PCI_CHIP_Q45_G		0x2E12
 40 
#define PCI_CHIP_I965_GME       0x2A12
148 
#define PCI_CHIP_Q45_G_BRIDGE	0x2E10
 - 
 
149 
#endif
 - 
 
150 
 
 - 
 
151 
#ifndef PCI_CHIP_G41_G
 - 
 
152 
#define PCI_CHIP_G41_G		0x2E32
 41 
#define PCI_CHIP_GM45_GM	0x2A42
153 
#define PCI_CHIP_G41_G_BRIDGE	0x2E30
 - 
 
154 
#endif
 - 
 
155 
 
 - 
 
156 
#ifndef PCI_CHIP_B43_G
 - 
 
157 
#define PCI_CHIP_B43_G		0x2E42
 42 
#define PCI_CHIP_G45_E_G	0x2E02
158 
#define PCI_CHIP_B43_G_BRIDGE	0x2E40
 - 
 
159 
#endif
 - 
 
Line 160... Line -...
160 
 
 - 
 
161 
#ifndef PCI_CHIP_B43_G1
 43 
#define PCI_CHIP_G45_G		0x2E22
162 
#define PCI_CHIP_B43_G1		0x2E92
 - 
 
163 
#define PCI_CHIP_B43_G1_BRIDGE	0x2E90
 - 
 
164 
#endif
 - 
 
165 
 
 - 
 
166 
#ifndef PCI_CHIP_IRONLAKE_D_G
 44 
#define PCI_CHIP_Q45_G		0x2E12
167 
#define PCI_CHIP_IRONLAKE_D_G		0x0042
 - 
 
168 
#define PCI_CHIP_IRONLAKE_D_G_BRIDGE	0x0040
 - 
 
Line 169... Line -...
169 
#endif
 - 
 
170 
 
 - 
 
171 
#ifndef PCI_CHIP_IRONLAKE_M_G
 45 
#define PCI_CHIP_G41_G		0x2E32
172 
#define PCI_CHIP_IRONLAKE_M_G		0x0046
 46 
#define PCI_CHIP_B43_G		0x2E42
173 
#define PCI_CHIP_IRONLAKE_M_G_BRIDGE	0x0044
 47 
#define PCI_CHIP_B43_G1		0x2E92
174 
#endif
 - 
 
175 
 
 48 
 
176 
#ifndef PCI_CHIP_SANDYBRIDGE_BRIDGE
 49 
#define PCI_CHIP_IRONLAKE_D_G		0x0042
177 
#define PCI_CHIP_SANDYBRIDGE_BRIDGE	0x0100	/* Desktop */
 50 
#define PCI_CHIP_IRONLAKE_M_G		0x0046
178 
#define PCI_CHIP_SANDYBRIDGE_GT1	0x0102
 - 
 
179 
#define PCI_CHIP_SANDYBRIDGE_GT2	0x0112
 51 
 
Line 180... Line 52...
180 
#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS	0x0122
 52 
#define PCI_CHIP_SANDYBRIDGE_GT1	0x0102
181 
#define PCI_CHIP_SANDYBRIDGE_BRIDGE_M	0x0104	/* Mobile */
 53 
#define PCI_CHIP_SANDYBRIDGE_GT2	0x0112
182 
#define PCI_CHIP_SANDYBRIDGE_M_GT1	0x0106
 54 
#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS	0x0122
Line 192... Line 64...
192 
#define PCI_CHIP_IVYBRIDGE_S_GT1	0x015a
 64 
#define PCI_CHIP_IVYBRIDGE_S_GT1	0x015a
193 
#define PCI_CHIP_IVYBRIDGE_S_GT2	0x016a
 65 
#define PCI_CHIP_IVYBRIDGE_S_GT2	0x016a
Line 194... Line 66...
194 
 
 66 
 
195 
#define PCI_CHIP_HASWELL_D_GT1		0x0402
 67 
#define PCI_CHIP_HASWELL_D_GT1		0x0402
196 
#define PCI_CHIP_HASWELL_D_GT2		0x0412
 68 
#define PCI_CHIP_HASWELL_D_GT2		0x0412
197 
#define PCI_CHIP_HASWELL_D_GT2_PLUS	0x0422
 69 
#define PCI_CHIP_HASWELL_D_GT3		0x0422
198 
#define PCI_CHIP_HASWELL_M_GT1		0x0406
 70 
#define PCI_CHIP_HASWELL_M_GT1		0x0406
199 
#define PCI_CHIP_HASWELL_M_GT2		0x0416
 71 
#define PCI_CHIP_HASWELL_M_GT2		0x0416
200 
#define PCI_CHIP_HASWELL_M_GT2_PLUS	0x0426
 72 
#define PCI_CHIP_HASWELL_M_GT3		0x0426
201 
#define PCI_CHIP_HASWELL_S_GT1		0x040A
 73 
#define PCI_CHIP_HASWELL_S_GT1		0x040A
202 
#define PCI_CHIP_HASWELL_S_GT2		0x041A
 74 
#define PCI_CHIP_HASWELL_S_GT2		0x041A
203 
#define PCI_CHIP_HASWELL_S_GT2_PLUS	0x042A
 75 
#define PCI_CHIP_HASWELL_S_GT3		0x042A
204 
#define PCI_CHIP_HASWELL_SDV_D_GT1	0x0C02
 76 
#define PCI_CHIP_HASWELL_B_GT1		0x040B
205 
#define PCI_CHIP_HASWELL_SDV_D_GT2	0x0C12
 - 
 
206 
#define PCI_CHIP_HASWELL_SDV_D_GT2_PLUS	0x0C22
 77 
#define PCI_CHIP_HASWELL_B_GT2		0x041B
207 
#define PCI_CHIP_HASWELL_SDV_M_GT1	0x0C06
 - 
 
208 
#define PCI_CHIP_HASWELL_SDV_M_GT2	0x0C16
 - 
 
209 
#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS	0x0C26
 78 
#define PCI_CHIP_HASWELL_B_GT3		0x042B
210 
#define PCI_CHIP_HASWELL_SDV_S_GT1	0x0C0A
 79 
#define PCI_CHIP_HASWELL_E_GT1		0x040E
211 
#define PCI_CHIP_HASWELL_SDV_S_GT2	0x0C1A
 80 
#define PCI_CHIP_HASWELL_E_GT2		0x041E
- 
 
 81 
#define PCI_CHIP_HASWELL_E_GT3		0x042E
212 
#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS	0x0C2A
 82 
 
213 
#define PCI_CHIP_HASWELL_ULT_D_GT1	0x0A02
 83 
#define PCI_CHIP_HASWELL_ULT_D_GT1	0x0A02
214 
#define PCI_CHIP_HASWELL_ULT_D_GT2	0x0A12
 84 
#define PCI_CHIP_HASWELL_ULT_D_GT2	0x0A12
215 
#define PCI_CHIP_HASWELL_ULT_D_GT2_PLUS	0x0A22
 85 
#define PCI_CHIP_HASWELL_ULT_D_GT3	0x0A22
216 
#define PCI_CHIP_HASWELL_ULT_M_GT1	0x0A06
 86 
#define PCI_CHIP_HASWELL_ULT_M_GT1	0x0A06
217 
#define PCI_CHIP_HASWELL_ULT_M_GT2	0x0A16
 87 
#define PCI_CHIP_HASWELL_ULT_M_GT2	0x0A16
218 
#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS	0x0A26
 88 
#define PCI_CHIP_HASWELL_ULT_M_GT3	0x0A26
219 
#define PCI_CHIP_HASWELL_ULT_S_GT1	0x0A0A
 89 
#define PCI_CHIP_HASWELL_ULT_S_GT1	0x0A0A
220 
#define PCI_CHIP_HASWELL_ULT_S_GT2	0x0A1A
 90 
#define PCI_CHIP_HASWELL_ULT_S_GT2	0x0A1A
221 
#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS	0x0A2A
 91 
#define PCI_CHIP_HASWELL_ULT_S_GT3	0x0A2A
222 
#define PCI_CHIP_HASWELL_CRW_D_GT1	0x0D12
 92 
#define PCI_CHIP_HASWELL_ULT_B_GT1	0x0A0B
223 
#define PCI_CHIP_HASWELL_CRW_D_GT2	0x0D22
 93 
#define PCI_CHIP_HASWELL_ULT_B_GT2	0x0A1B
224 
#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS	0x0D32
 94 
#define PCI_CHIP_HASWELL_ULT_B_GT3	0x0A2B
225 
#define PCI_CHIP_HASWELL_CRW_M_GT1	0x0D16
 95 
#define PCI_CHIP_HASWELL_ULT_E_GT1	0x0A0E
226 
#define PCI_CHIP_HASWELL_CRW_M_GT2	0x0D26
 96 
#define PCI_CHIP_HASWELL_ULT_E_GT2	0x0A1E
- 
 
 97 
#define PCI_CHIP_HASWELL_ULT_E_GT3	0x0A2E
227 
#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS	0x0D36
 98 
 
228 
#define PCI_CHIP_HASWELL_CRW_S_GT1	0x0D1A
 99 
#define PCI_CHIP_HASWELL_CRW_D_GT1	0x0D02
229 
#define PCI_CHIP_HASWELL_CRW_S_GT2	0x0D2A
 100 
#define PCI_CHIP_HASWELL_CRW_D_GT2	0x0D12
230 
#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS	0x0D3A
 - 
 
231 
 
 101 
#define PCI_CHIP_HASWELL_CRW_D_GT3	0x0D22
232 
#define PCI_CHIP_VALLEYVIEW_PO		0x0f30
 102 
#define PCI_CHIP_HASWELL_CRW_M_GT1	0x0D06
233 
#define PCI_CHIP_VALLEYVIEW_1		0x0f31
 103 
#define PCI_CHIP_HASWELL_CRW_M_GT2	0x0D16
234 
#define PCI_CHIP_VALLEYVIEW_2		0x0f32
 104 
#define PCI_CHIP_HASWELL_CRW_M_GT3	0x0D26
235 
#define PCI_CHIP_VALLEYVIEW_3		0x0f33
 - 
 
236 
 
 - 
 
237 
#endif
 - 
 
238 
 
 - 
 
239 
#define I85X_CAPID			0x44
 105 
#define PCI_CHIP_HASWELL_CRW_S_GT1	0x0D0A
240 
#define I85X_VARIANT_MASK			0x7
 106 
#define PCI_CHIP_HASWELL_CRW_S_GT2	0x0D1A
241 
#define I85X_VARIANT_SHIFT			5
 - 
 
242 
#define I855_GME				0x0
 - 
 
243 
#define I855_GM					0x4
 - 
 
244 
#define I852_GME				0x2
 - 
 
245 
#define I852_GM					0x5
 - 
 
246 
 
 - 
 
247 
#define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr
 - 
 
248 
#define VENDOR_ID(p)      (p)->vendor_id
 - 
 
249 
#define DEVICE_ID(p)      (p)->device_id
 - 
 
250 
#define SUBVENDOR_ID(p)	  (p)->subvendor_id
 - 
 
251 
#define SUBSYS_ID(p)      (p)->subdevice_id
 107 
#define PCI_CHIP_HASWELL_CRW_S_GT3	0x0D2A
252 
#define CHIP_REVISION(p)  (p)->revision
 - 
 
253 
 
 - 
 
254 
#define INTEL_INFO(intel) ((intel)->info)
 - 
 
255 
#define IS_GENx(intel, X) (INTEL_INFO(intel)->gen >= 8*(X) && INTEL_INFO(intel)->gen < 8*((X)+1))
 108 
#define PCI_CHIP_HASWELL_CRW_B_GT1	0x0D0B
256 
#define IS_GEN1(intel) IS_GENx(intel, 1)
 109 
#define PCI_CHIP_HASWELL_CRW_B_GT2	0x0D1B
257 
#define IS_GEN2(intel) IS_GENx(intel, 2)
 - 
 
258 
#define IS_GEN3(intel) IS_GENx(intel, 3)
 - 
 
259 
#define IS_GEN4(intel) IS_GENx(intel, 4)
 110 
#define PCI_CHIP_HASWELL_CRW_B_GT3	0x0D2B
260 
#define IS_GEN5(intel) IS_GENx(intel, 5)
 111 
#define PCI_CHIP_HASWELL_CRW_E_GT1	0x0D0E
261 
#define IS_GEN6(intel) IS_GENx(intel, 6)
 112 
#define PCI_CHIP_HASWELL_CRW_E_GT2	0x0D1E
262 
#define IS_GEN7(intel) IS_GENx(intel, 7)
 - 
 
263 
#define IS_HSW(intel) (INTEL_INFO(intel)->gen == 075)
 - 
 
264 
 
 - 
 
265 
/* Some chips have specific errata (or limits) that we need to workaround. */
 - 
 
266 
#define IS_I830(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I830_M)
 - 
 
267 
#define IS_845G(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_845_G)
 - 
 
268 
#define IS_I865G(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I865_G)
 - 
 
269 
 
 - 
 
270 
#define IS_I915G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_E7221_G)
 - 
 
271 
#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM)
 - 
 
272 
 
 - 
 
273 
#define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q)
 - 
 
274 
 
 - 
 
275 
/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
 - 
 
276 
#define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 040)
 - 
 
Line 277... Line 113...
277 
#define HAS_BLT(pI810) (INTEL_INFO(intel)->gen >= 060)
 113 
#define PCI_CHIP_HASWELL_CRW_E_GT3	0x0D2E
278 
 
 114 
 
279 
struct intel_device_info {
 115 
struct intel_device_info {