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| Rev 1430 | Rev 1600 | ||
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| Line 1... | Line 1... | ||
| 1 | Bool FindPciDevice() |
1 | bool FindUSBControllers() |
| 2 | { |
2 | { |
| 3 | Bool retval = FALSE; |
3 | bool retval = false; |
| 4 | u32_t bus, last_bus; |
4 | u32_t bus, last_bus; |
| 5 | PCITAG tag; |
5 | PCITAG tag; |
| Line 6... | Line 6... | ||
| 6 | 6 | ||
| 7 | if( (last_bus = PciApi(1))==-1) |
7 | if( (last_bus = PciApi(1))==-1) |
| Line 33... | Line 33... | ||
| 33 | if (! pcicmd & PCI_COMMAND_IO) |
33 | if (! pcicmd & PCI_COMMAND_IO) |
| 34 | continue; |
34 | continue; |
| 35 | 35 | ||
| Line 36... | Line 36... | ||
| 36 | hc = (hc_t*)malloc(sizeof(hc_t)); |
36 | hc = (hc_t*)kmalloc(sizeof(hc_t), 0); |
| 37 | memset(hc, 0, sizeof(hc_t)); |
- | |
| 38 | link_initialize(&hc->link); |
37 | INIT_LIST_HEAD(&hc->list); |
| Line 39... | Line 38... | ||
| 39 | 38 | ||
| 40 | hc->pciId = PciRead32(bus,devfn, 0); |
39 | hc->pciId = PciRead32(bus,devfn, 0); |
| Line 41... | Line 40... | ||
| 41 | hc->PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7); |
40 | hc->PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7); |
| 42 | 41 | ||
| 43 | for (i = 0; i < 6; i++) |
42 | for (i = 0; i < 6; i++) |
| 44 | { |
43 | { |
| Line 45... | Line 44... | ||
| 45 | u32_t base; |
44 | u32_t base; |
| 46 | Bool validSize; |
45 | bool validSize; |
| 47 | 46 | ||
| 48 | base = PciRead32(bus,devfn, PCI_MAP_REG_START + (i << 2)); |
47 | base = PciRead32(bus,devfn, PCI_MAP_REG_START + (i << 2)); |
| Line 57... | Line 56... | ||
| 57 | } |
56 | } |
| 58 | } |
57 | } |
| 59 | }; |
58 | }; |
| 60 | list_prepend(&hc->link, &hc_list); |
59 | list_add_tail(&hc->list, &hc_list); |
| 61 | retval = TRUE; |
60 | retval = true; |
| 62 | }; |
61 | }; |
| 63 | }; |
62 | }; |
| 64 | return retval; |
63 | return retval; |
| 65 | }; |
64 | }; |
| 66 | > |
65 | |
| 67 | > |
66 | |
| - | 67 | #if 0 |
|
| - | 68 | ||
| - | 69 | /* these helpers provide future and backwards compatibility |
|
| - | 70 | * for accessing popular PCI BAR info */ |
|
| - | 71 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
|
| - | 72 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
|
| - | 73 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
|
| - | 74 | #define pci_resource_len(dev,bar) \ |
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| - | 75 | ((pci_resource_start((dev), (bar)) == 0 && \ |
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| - | 76 | pci_resource_end((dev), (bar)) == \ |
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| - | 77 | pci_resource_start((dev), (bar))) ? 0 : \ |
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| - | 78 | \ |
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| - | 79 | (pci_resource_end((dev), (bar)) - \ |
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| - | 80 | pci_resource_start((dev), (bar)) + 1)) |
|
| - | 81 | ||
| - | 82 | static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx) |
|
| - | 83 | { |
|
| - | 84 | return pci_resource_start(pdev, idx) && mmio_enabled(pdev); |
|
| - | 85 | } |
|
| - | 86 | ||
| - | 87 | static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev) |
|
| - | 88 | { |
|
| - | 89 | int wait_time, delta; |
|
| - | 90 | void __iomem *base, *op_reg_base; |
|
| - | 91 | u32 hcc_params, val; |
|
| - | 92 | u8 offset, cap_length; |
|
| - | 93 | int count = 256/4; |
|
| - | 94 | int tried_handoff = 0; |
|
| - | 95 | ||
| - | 96 | if (!mmio_resource_enabled(pdev, 0)) |
|
| - | 97 | return; |
|
| - | 98 | ||
| - | 99 | base = pci_ioremap_bar(pdev, 0); |
|
| - | 100 | if (base == NULL) |
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| - | 101 | return; |
|
| - | 102 | ||
| - | 103 | cap_length = readb(base); |
|
| - | 104 | op_reg_base = base + cap_length; |
|
| - | 105 | ||
| - | 106 | /* EHCI 0.96 and later may have "extended capabilities" |
|
| - | 107 | * spec section 5.1 explains the bios handoff, e.g. for |
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| - | 108 | * booting from USB disk or using a usb keyboard |
|
| - | 109 | */ |
|
| - | 110 | hcc_params = readl(base + EHCI_HCC_PARAMS); |
|
| - | 111 | offset = (hcc_params >> 8) & 0xff; |
|
| - | 112 | while (offset && --count) { |
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| - | 113 | u32 cap; |
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| - | 114 | int msec; |
|
| - | 115 | ||
| - | 116 | pci_read_config_dword(pdev, offset, &cap); |
|
| - | 117 | switch (cap & 0xff) { |
|
| - | 118 | case 1: /* BIOS/SMM/... handoff support */ |
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| - | 119 | if ((cap & EHCI_USBLEGSUP_BIOS)) { |
|
| - | 120 | dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n"); |
|
| - | 121 | ||
| - | 122 | #if 0 |
|
| - | 123 | /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on, |
|
| - | 124 | * but that seems dubious in general (the BIOS left it off intentionally) |
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| - | 125 | * and is known to prevent some systems from booting. so we won't do this |
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| - | 126 | * unless maybe we can determine when we're on a system that needs SMI forced. |
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| - | 127 | */ |
|
| - | 128 | /* BIOS workaround (?): be sure the |
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| - | 129 | * pre-Linux code receives the SMI |
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| - | 130 | */ |
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| - | 131 | pci_read_config_dword(pdev, |
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| - | 132 | offset + EHCI_USBLEGCTLSTS, |
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| - | 133 | &val); |
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| - | 134 | pci_write_config_dword(pdev, |
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| - | 135 | offset + EHCI_USBLEGCTLSTS, |
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| - | 136 | val | EHCI_USBLEGCTLSTS_SOOE); |
|
| - | 137 | #endif |
|
| - | 138 | ||
| - | 139 | /* some systems get upset if this semaphore is |
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| - | 140 | * set for any other reason than forcing a BIOS |
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| - | 141 | * handoff.. |
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| - | 142 | */ |
|
| - | 143 | pci_write_config_byte(pdev, offset + 3, 1); |
|
| - | 144 | } |
|
| - | 145 | ||
| - | 146 | /* if boot firmware now owns EHCI, spin till |
|
| - | 147 | * it hands it over. |
|
| - | 148 | */ |
|
| - | 149 | msec = 1000; |
|
| - | 150 | while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) { |
|
| - | 151 | tried_handoff = 1; |
|
| - | 152 | msleep(10); |
|
| - | 153 | msec -= 10; |
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| - | 154 | pci_read_config_dword(pdev, offset, &cap); |
|
| - | 155 | } |
|
| - | 156 | ||
| - | 157 | if (cap & EHCI_USBLEGSUP_BIOS) { |
|
| - | 158 | /* well, possibly buggy BIOS... try to shut |
|
| - | 159 | * it down, and hope nothing goes too wrong |
|
| - | 160 | */ |
|
| - | 161 | dev_warn(&pdev->dev, "EHCI: BIOS handoff failed" |
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| - | 162 | " (BIOS bug?) %08x\n", cap); |
|
| - | 163 | pci_write_config_byte(pdev, offset + 2, 0); |
|
| - | 164 | } |
|
| - | 165 | ||
| - | 166 | /* just in case, always disable EHCI SMIs */ |
|
| - | 167 | pci_write_config_dword(pdev, |
|
| - | 168 | offset + EHCI_USBLEGCTLSTS, |
|
| - | 169 | 0); |
|
| - | 170 | ||
| - | 171 | /* If the BIOS ever owned the controller then we |
|
| - | 172 | * can't expect any power sessions to remain intact. |
|
| - | 173 | */ |
|
| - | 174 | if (tried_handoff) |
|
| - | 175 | writel(0, op_reg_base + EHCI_CONFIGFLAG); |
|
| - | 176 | break; |
|
| - | 177 | case 0: /* illegal reserved capability */ |
|
| - | 178 | cap = 0; |
|
| - | 179 | /* FALLTHROUGH */ |
|
| - | 180 | default: |
|
| - | 181 | dev_warn(&pdev->dev, "EHCI: unrecognized capability " |
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| - | 182 | "%02x\n", cap & 0xff); |
|
| - | 183 | break; |
|
| - | 184 | } |
|
| - | 185 | offset = (cap >> 8) & 0xff; |
|
| - | 186 | } |
|
| - | 187 | if (!count) |
|
| - | 188 | dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n"); |
|
| - | 189 | ||
| - | 190 | /* |
|
| - | 191 | * halt EHCI & disable its interrupts in any case |
|
| - | 192 | */ |
|
| - | 193 | val = readl(op_reg_base + EHCI_USBSTS); |
|
| - | 194 | if ((val & EHCI_USBSTS_HALTED) == 0) { |
|
| - | 195 | val = readl(op_reg_base + EHCI_USBCMD); |
|
| - | 196 | val &= ~EHCI_USBCMD_RUN; |
|
| - | 197 | writel(val, op_reg_base + EHCI_USBCMD); |
|
| - | 198 | ||
| - | 199 | wait_time = 2000; |
|
| - | 200 | delta = 100; |
|
| - | 201 | do { |
|
| - | 202 | writel(0x3f, op_reg_base + EHCI_USBSTS); |
|
| - | 203 | udelay(delta); |
|
| - | 204 | wait_time -= delta; |
|
| - | 205 | val = readl(op_reg_base + EHCI_USBSTS); |
|
| - | 206 | if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) { |
|
| - | 207 | break; |
|
| - | 208 | } |
|
| - | 209 | } while (wait_time > 0); |
|
| - | 210 | } |
|
| - | 211 | writel(0, op_reg_base + EHCI_USBINTR); |
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| - | 212 | writel(0x3f, op_reg_base + EHCI_USBSTS); |
|
| - | 213 | ||
| - | 214 | iounmap(base); |
|
| - | 215 | ||
| - | 216 | return; |
|
| - | 217 | } |
|
| - | 218 | ||
| - | 219 | #endif |
|
| - | 220 | > |
|
| - | 221 | > |
|