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Rev 4476 Rev 5066
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; This module detects and initialises all Cardbus/pc-card/PCMCIA cards.
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; This module detects and initialises all Cardbus/pc-card/PCMCIA cards.
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16
 
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; WARNING: Cards must be inserted before the driver starts, and shouldn't be removed.
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; WARNING: Cards must be inserted before the driver starts, and shouldn't be removed.
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; This module doesn't handle insertions and removals.
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; This module doesn't handle insertions and removals.
-
 
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format PE DLL native
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format MS COFF
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entry START
-
 
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        CURRENT_API             = 0x0200
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        API_VERSION             = 0x01000100
-
 
23
        DRIVER_VERSION          = 5
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        COMPATIBLE_API          = 0x0100
24
 
25
        API_VERSION             = (COMPATIBLE_API shl 16) + CURRENT_API
Line -... Line 26...
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Line -... Line 27...
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        CARDBUS_IO              = 0xFC00
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        CARDBUS_IO              = 0xFC00
28
 
26
 
29
        __DEBUG__               = 1
27
        DEBUG                   = 1
-
 
28
        __DEBUG__               = 1
-
 
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        __DEBUG_LEVEL__         = 1
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        __DEBUG_LEVEL__         = 1
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-
 
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include '../struct.inc'
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include '../macros.inc'
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include '../proc32.inc'
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35
include '../imports.inc'
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36
include '../pci.inc'
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include '../fdo.inc'
32
section '.flat' readable writable executable
38
 
33
 
39
public START
34
include '../proc32.inc'
40
public service_proc
35
include '../struct.inc'
41
public version
36
include '../macros.inc'
42
 
37
include '../pci_pe.inc'
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section '.flat' code readable align 16
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44
 
38
include '../fdo.inc'
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;                        ;;
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;; proc START             ;;
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;;                        ;;
40
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; (standard driver proc) ;;
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;;                        ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; proc START             ;;
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;;                        ;;
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align 4
44
;; (standard driver proc) ;;
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proc START stdcall, state:dword
45
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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-
 
55
        cmp [state], 1
46
 
56
        jne .exit
47
proc START c, reason:dword, cmdline:dword
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48
 
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;; proc SERVICE_PROC      ;;
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;; proc SERVICE_PROC      ;;
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;;                        ;;
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;;                        ;;
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;; (standard driver proc) ;;
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;; (standard driver proc) ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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-
 
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align 4
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proc service_proc stdcall, ioctl:dword
74
proc service_proc stdcall, ioctl:dword
85
 
75
 
Line 118... Line 108...
118
        DEBUGF  1, "Searching for cardbus bridges...\n"
108
        DEBUGF  1, "Searching for cardbus bridges...\n"
Line 119... Line 109...
119
 
109
 
120
        xor     eax, eax
110
        xor     eax, eax
121
        mov     [bus], eax
111
        mov     [bus], eax
122
        inc     eax
112
        inc     eax
123
        call    PciApi
113
        invoke  PciApi
124
        cmp     eax, -1
114
        cmp     eax, -1
125
        je      .err
115
        je      .err
Line 126... Line 116...
126
        mov     [last_bus], eax
116
        mov     [last_bus], eax
127
 
117
 
Line 128... Line 118...
128
        inc     eax
118
        inc     eax
129
        mov     [card_bus], eax
119
        mov     [card_bus], eax
130
 
120
 
131
  .next_bus:
121
  .next_bus:
132
        and     [devfn], 0
122
        and     [devfn], 0
133
  .next_dev:
123
  .next_dev:
134
        stdcall PciRead32, [bus], [devfn], PCI_VENDOR_ID
124
        invoke  PciRead32, [bus], [devfn], PCI_header02.vendor_id
135
        test    eax, eax
125
        test    eax, eax
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        jz      .next
126
        jz      .next
137
        cmp     eax, -1
127
        cmp     eax, -1
138
        je      .next
128
        je      .next
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139
 
129
 
140
        stdcall PciRead16, [bus], [devfn], 0x0a ; class & subclass
130
        invoke  PciRead16, [bus], [devfn], 0x0a ; class & subclass
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        ret
147
        ret
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148
 
159
  .found:
149
  .found:
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160
        DEBUGF  1, "Found cardbus bridge: bus=0x%x, dev=0x%x\n", [bus], [devfn]
150
        DEBUGF  1, "Found cardbus bridge: bus=0x%x, dev=0x%x\n", [bus], [devfn]
161
 
151
 
162
        stdcall PciRead8, [bus], [devfn], 0x0e                  ; get header type
-
 
163
        DEBUGF  1, "Header type=0x%x\n", eax:2
152
        invoke  PciRead8, [bus], [devfn], PCI_header.header_type
164
 
153
        DEBUGF  1, "Header type=0x%x\n", eax:2
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165
        test    al, al
154
        cmp     al, 2
Line 166... Line 155...
166
        jz      .next
155
        jne     .next
167
 
156
 
168
; Write PCI and cardbus numbers
157
; Write PCI and cardbus numbers
169
 
158
 
170
        stdcall PciRead32, [bus], [devfn], 0x18                 ; PCcard latency settings + Card bus number, PCI bus number
159
        invoke  PciRead32, [bus], [devfn], PCI_header02.pci_bus_nr      ; PCcard latency settings + Card bus number, PCI bus number
171
        and     eax, 0xff000000                                 ; Keep original latency setting, clear the rest
160
        and     eax, 0xff000000                                         ; Keep original latency setting, clear the rest
172
        mov     al, byte[bus]
161
        mov     al, byte[bus]
173
        mov     ah, byte[card_bus]
162
        mov     ah, byte[card_bus]
174
        mov     ebx, [card_bus]
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        mov     ebx, [card_bus]
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        shl     ebx, 16
164
        shl     ebx, 16
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        or      eax, ebx
165
        or      eax, ebx
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        DEBUGF  1, "Latency, bus,.. 0x%x\n", eax
166
        DEBUGF  1, "Latency, bus,.. 0x%x\n", eax
Line 178... Line 167...
178
        stdcall PciWrite32, [bus], [devfn], 0x18, eax
167
        invoke  PciWrite32, [bus], [devfn], PCI_header02.pci_bus_nr, eax
179
 
168
 
180
; set ExCA legacy mode base
169
; set ExCA legacy mode base
181
 
170
 
182
        stdcall PciWrite32, [bus], [devfn], 0x44, 1
171
        invoke  PciWrite32, [bus], [devfn], 0x44, 1
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183
 
172
 
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; Enable power
173
; Enable power
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174
 
Line 186... Line 175...
186
        stdcall PciRead8, [bus], [devfn], 0x14                  ; get capabilities offset
175
        invoke  PciRead8, [bus], [devfn], 0x14                  ; get capabilities offset
187
        movzx   eax, al                                         ; (A0 for TI bridges)
176
        movzx   eax, al                                         ; (A0 for TI bridges)
188
        DEBUGF  1, "Capabilities offset=0x%x\n", eax:2
177
        DEBUGF  1, "Capabilities offset=0x%x\n", eax:2
189
        add     al, 4                                           ; Power management control/status
178
        add     al, 4                                           ; Power management control/status
190
        stdcall PciWrite16, [bus], [devfn], eax, 0x0100         ; Enable PME signaling, power state=D0
179
        invoke  PciWrite16, [bus], [devfn], eax, 0x0100         ; Enable PME signaling, power state=D0
191
 
180
 
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; Enable Bus master, io space, memory space
181
; Enable Bus master, io space, memory space
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193
 
182
 
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        cmp     al, 00100000b                                   ; Check for inserted cardbus card
199
        cmp     al, 00100000b                                   ; Check for inserted cardbus card
211
        je      .CardbusInserted
200
        je      .CardbusInserted
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212
 
201
 
Line 213... Line 202...
213
; No card found... set PCI command back to 0
202
; No card found... set PCI command back to 0
214
 
203
 
215
        stdcall PciWrite16, [bus], [devfn], PCI_REG_COMMAND, 0  ; To avoid conflicts with other sockets
204
        invoke  PciWrite16, [bus], [devfn], PCI_header02.command, 0  ; To avoid conflicts with other sockets
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216
        DEBUGF  1, "Cardbus KO\n"
205
        DEBUGF  1, "Cardbus KO\n"
217
        jmp     .next
206
        jmp     .next
218
 
207
 
219
  .CardbusInserted:
208
  .CardbusInserted:
220
        DEBUGF  1, "Card inserted\n"
209
        DEBUGF  1, "Card inserted\n"
221
        ;mov     word[ecx + 0x802], 0x00F9       ; Assert reset, output enable, vcc=vpp=3.3V
210
        ;mov     word[ecx + 0x802], 0x00F9       ; Assert reset, output enable, vcc=vpp=3.3V
222
        mov     dword[ecx + 0x10], 0x33         ; Request 3.3V for Vcc and Vpp (Control register)
211
        mov     dword[ecx + 0x10], 0x33         ; Request 3.3V for Vcc and Vpp (Control register)
223
        ;push    ecx
212
        ;push    ecx
224
        ;mov     esi, 10
213
        ;mov     esi, 10
225
        ;call    Sleep
214
        ;invoke  Sleep
226
        ;pop     ecx
215
        ;pop     ecx
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243
irp     regvalue,   0x7efff000, 0x7effffff, 0x7effe000, 0x7effe000, CARDBUS_IO, CARDBUS_IO + 0xFF, 0, 0
232
irp     regvalue,   0x7efff000, 0x7effffff, 0x7effe000, 0x7effe000, CARDBUS_IO, CARDBUS_IO + 0xFF, 0, 0
244
{
233
{
245
common
234
common
246
        reg = 0x1C
235
        reg = 0x1C
247
forward
236
forward
248
        stdcall PciWrite32, [bus], [devfn], reg, regvalue
237
        invoke  PciWrite32, [bus], [devfn], reg, regvalue
249
        DEBUGF  1, "Writing 0x%x to 0x%x\n", regvalue, reg
238
        DEBUGF  1, "Writing 0x%x to 0x%x\n", regvalue, reg
250
        reg = reg + 4
239
        reg = reg + 4
251
}
240
}
Line 252... Line 241...
252
 
241
 
Line 253... Line 242...
253
        stdcall PciWrite8, [bus], [devfn], 0x3c, 0xc    ; IRQ line
242
        invoke  PciWrite8, [bus], [devfn], PCI_header02.interrupt_line, 0xc    ; IRQ line
254
 
243
 
255
        stdcall PciRead16, [bus], [devfn], 0x3e                 ; Bridge control
244
        invoke  PciRead16, [bus], [devfn], PCI_header02.bridge_ctrl                 ; Bridge control
256
        or      ax, 0x0700                                      ; Enable write posting, both memory windows prefetchable
245
        or      ax, 0x0700                                      ; Enable write posting, both memory windows prefetchable
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257
        stdcall PciWrite16, [bus], [devfn], 0x3e, eax
246
        invoke  PciWrite16, [bus], [devfn], PCI_header02.bridge_ctrl, eax
258
        DEBUGF  1, "Write posting enabled\n"
247
        DEBUGF  1, "Write posting enabled\n"
259
 
248
 
260
 
249
 
261
        DEBUGF  1, "Bridge PCI registers:\n"
250
        DEBUGF  1, "Bridge PCI registers:\n"
262
rept    17 reg
251
rept    17 reg
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263
{
252
{
Line 264... Line 253...
264
        stdcall PciRead32, [bus], [devfn], 4*(reg-1)
253
        invoke  PciRead32, [bus], [devfn], 4*(reg-1)
265
        DEBUGF  1, "0x%x\n", eax
254
        DEBUGF  1, "0x%x\n", eax
266
}
255
}
267
 
256
 
268
        inc     byte[0x80009021]                                ; LAST PCI bus count in kernel (dirty HACK!)
257
        inc     byte[0x80009021]                                ; LAST PCI bus count in kernel (dirty HACK!)
269
 
258
 
270
 
259
 
271
        mov     ecx, 100
260
        mov     ecx, 100
272
  .waitactive:
261
  .waitactive:
273
        push    ecx
262
        push    ecx
274
        stdcall PciRead32, [card_bus], 0, PCI_VENDOR_ID         ; Check if the card is awake yet
263
        invoke  PciRead32, [card_bus], 0, PCI_header02.vendor_id         ; Check if the card is awake yet
Line 275... Line 264...
275
        inc     eax
264
        inc     eax
Line 286... Line 275...
286
 
275
 
287
  .got_it:
276
  .got_it:
288
        pop     eax
277
        pop     eax
Line 289... Line 278...
289
        DEBUGF  1, "Card is enabled!\n"
278
        DEBUGF  1, "Card is enabled!\n"
290
 
279
 
291
        stdcall PciWrite32, [card_bus], 0, PCI_BASE_ADDRESS_0, CARDBUS_IO       ; Supposing it's IO space that is needed
280
        invoke  PciWrite32, [card_bus], 0, PCI_header02.base_addr, CARDBUS_IO       ; Supposing it's IO space that is needed
Line 292... Line 281...
292
        stdcall PciWrite8, [card_bus], 0, PCI_REG_IRQ, 0xC                      ; FIXME
281
        invoke  PciWrite8, [card_bus], 0, PCI_header02.interrupt_line, 0xC                      ; FIXME
Line 293... Line 282...
293
        stdcall PciWrite16, [card_bus], 0, PCI_REG_COMMAND, PCI_BIT_PIO or PCI_BIT_MMIO
282
        invoke  PciWrite16, [card_bus], 0, PCI_header02.command, PCI_CMD_PIO or PCI_CMD_MMIO
Line 300... Line 289...
300
        DEBUGF  1, "Error\n"
289
        DEBUGF  1, "Error\n"
301
        xor     eax, eax
290
        xor     eax, eax
Line 302... Line 291...
302
 
291
 
Line 303... Line -...
303
        ret
-
 
304
 
-
 
305
 
292
        ret
Line 306... Line -...
306
 
-
 
307
endp
-
 
308
 
293
 
Line -... Line 294...
-
 
294
endp
-
 
295
 
-
 
296
 
309
 
297
; End of code
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310
 
-
 
311
 
298
 
Line 312... Line 299...
312
; End of code
299
data fixups
313
 
300
end data