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| 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| 2 | ;; ;; |
2 | ;; ;; |
| 3 | ;; Copyright (C) KolibriOS team 2004-2015. All rights reserved. ;; |
3 | ;; Copyright (C) KolibriOS team 2004-2018. All rights reserved. ;; |
| 4 | ;; Distributed under terms of the GNU General Public License ;; |
4 | ;; Distributed under terms of the GNU General Public License ;; |
| 5 | ;; ;; |
5 | ;; ;; |
| 6 | ;; GNU GENERAL PUBLIC LICENSE ;; |
6 | ;; GNU GENERAL PUBLIC LICENSE ;; |
| 7 | ;; Version 2, June 1991 ;; |
7 | ;; Version 2, June 1991 ;; |
| 8 | ;; ;; |
8 | ;; ;; |
| 9 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
9 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| 10 | 10 | ||
| 11 | struct PCI_header |
11 | struct PCI_header |
| 12 | 12 | ||
| 13 | vendor_id dw ? ; 0x00 |
13 | vendor_id dw ? ; 0x00 |
| 14 | device_id dw ? ; 0x02 |
14 | device_id dw ? ; 0x02 |
| 15 | command dw ? ; 0x04 |
15 | command dw ? ; 0x04 |
| 16 | status dw ? ; 0x06 |
16 | status dw ? ; 0x06 |
| 17 | revision_id db ? ; 0x08 |
17 | revision_id db ? ; 0x08 |
| 18 | prog_if db ? ; 0x09 |
18 | prog_if db ? ; 0x09 |
| 19 | subclass db ? ; 0x0A |
19 | subclass db ? ; 0x0A |
| 20 | class_code db ? ; 0x0B |
20 | class_code db ? ; 0x0B |
| 21 | cache_line_size db ? ; 0x0C |
21 | cache_line_size db ? ; 0x0C |
| 22 | latency_timer db ? ; 0x0D |
22 | latency_timer db ? ; 0x0D |
| 23 | header_type db ? ; 0x0E |
23 | header_type db ? ; 0x0E |
| 24 | bist db ? ; 0x0F |
24 | bist db ? ; 0x0F |
| 25 | 25 | ||
| 26 | ends |
26 | ends |
| 27 | 27 | ||
| 28 | struct PCI_header00 PCI_header |
28 | struct PCI_header00 PCI_header |
| 29 | 29 | ||
| 30 | base_addr_0 dd ? ; 0x10 |
30 | base_addr_0 dd ? ; 0x10 |
| 31 | base_addr_1 dd ? ; 0x14 |
31 | base_addr_1 dd ? ; 0x14 |
| 32 | base_addr_2 dd ? ; 0x18 |
32 | base_addr_2 dd ? ; 0x18 |
| 33 | base_addr_3 dd ? ; 0x1C |
33 | base_addr_3 dd ? ; 0x1C |
| 34 | base_addr_4 dd ? ; 0x20 |
34 | base_addr_4 dd ? ; 0x20 |
| 35 | base_addr_5 dd ? ; 0x24 |
35 | base_addr_5 dd ? ; 0x24 |
| 36 | cardbus_cis_ptr dd ? ; 0x28 |
36 | cardbus_cis_ptr dd ? ; 0x28 |
| 37 | subsys_vendor dw ? ; 0x2C |
37 | subsys_vendor dw ? ; 0x2C |
| 38 | subsys_id dw ? ; 0x2E |
38 | subsys_id dw ? ; 0x2E |
| 39 | exp_rom_addr dd ? ; 0x30 |
39 | exp_rom_addr dd ? ; 0x30 |
| 40 | cap_ptr db ? ; 0x34 |
40 | cap_ptr db ? ; 0x34 |
| 41 | rb 7 ; reserved |
41 | rb 7 ; reserved |
| 42 | interrupt_line db ? ; 0x3C |
42 | interrupt_line db ? ; 0x3C |
| 43 | interrupt_pin db ? ; 0x3D |
43 | interrupt_pin db ? ; 0x3D |
| 44 | min_grant db ? ; 0x3E |
44 | min_grant db ? ; 0x3E |
| 45 | max_latency db ? ; 0x3F |
45 | max_latency db ? ; 0x3F |
| 46 | 46 | ||
| 47 | ends |
47 | ends |
| 48 | 48 | ||
| 49 | struct PCI_header01 PCI_header |
49 | struct PCI_header01 PCI_header |
| 50 | 50 | ||
| 51 | base_addr_0 dd ? ; 0x10 |
51 | base_addr_0 dd ? ; 0x10 |
| 52 | base_addr_1 dd ? ; 0x14 |
52 | base_addr_1 dd ? ; 0x14 |
| 53 | prim_bus_nr db ? ; 0x18 |
53 | prim_bus_nr db ? ; 0x18 |
| 54 | sec_bus_nr db ? ; 0x19 |
54 | sec_bus_nr db ? ; 0x19 |
| 55 | sub_bus_nr db ? ; 0x1A |
55 | sub_bus_nr db ? ; 0x1A |
| 56 | sec_lat_tmr db ? ; 0x1B |
56 | sec_lat_tmr db ? ; 0x1B |
| 57 | io_base db ? ; 0x1C |
57 | io_base db ? ; 0x1C |
| 58 | io_limit db ? ; 0x1D |
58 | io_limit db ? ; 0x1D |
| 59 | sec_status dw ? ; 0x1E |
59 | sec_status dw ? ; 0x1E |
| 60 | mem_base dw ? ; 0x20 |
60 | mem_base dw ? ; 0x20 |
| 61 | mem_limit dw ? ; 0x22 |
61 | mem_limit dw ? ; 0x22 |
| 62 | pref_mem_base dw ? ; 0x24 |
62 | pref_mem_base dw ? ; 0x24 |
| 63 | pref_mem_limit dw ? ; 0x26 |
63 | pref_mem_limit dw ? ; 0x26 |
| 64 | pref_base_up dd ? ; 0x28 |
64 | pref_base_up dd ? ; 0x28 |
| 65 | pref_limit_up dd ? ; 0x2C |
65 | pref_limit_up dd ? ; 0x2C |
| 66 | io_base_up dw ? ; 0x30 |
66 | io_base_up dw ? ; 0x30 |
| 67 | io_limit_up dw ? ; 0x32 |
67 | io_limit_up dw ? ; 0x32 |
| 68 | cap_ptr db ? ; 0x34 |
68 | cap_ptr db ? ; 0x34 |
| 69 | rb 3 ; reserved |
69 | rb 3 ; reserved |
| 70 | exp_rom_addr dd ? ; 0x38 |
70 | exp_rom_addr dd ? ; 0x38 |
| 71 | interrupt_line db ? ; 0x3C |
71 | interrupt_line db ? ; 0x3C |
| 72 | interrupt_pin db ? ; 0x3E |
72 | interrupt_pin db ? ; 0x3E |
| 73 | bridge_ctrl dw ? ; 0x3F |
73 | bridge_ctrl dw ? ; 0x3F |
| 74 | 74 | ||
| 75 | ends |
75 | ends |
| 76 | 76 | ||
| 77 | struct PCI_header02 PCI_header |
77 | struct PCI_header02 PCI_header |
| 78 | 78 | ||
| 79 | base_addr dd ? ; 0x10 |
79 | base_addr dd ? ; 0x10 |
| 80 | cap_list_offs db ? ; 0x14 |
80 | cap_list_offs db ? ; 0x14 |
| 81 | rb 1 ; reserved |
81 | rb 1 ; reserved |
| 82 | sec_stat dw ? ; 0x16 |
82 | sec_stat dw ? ; 0x16 |
| 83 | pci_bus_nr db ? ; 0x18 |
83 | pci_bus_nr db ? ; 0x18 |
| 84 | cardbus_bus_nr db ? ; 0x19 |
84 | cardbus_bus_nr db ? ; 0x19 |
| 85 | sub_bus_nr db ? ; 0x1A |
85 | sub_bus_nr db ? ; 0x1A |
| 86 | cardbus_lat_tmr db ? ; 0x1B |
86 | cardbus_lat_tmr db ? ; 0x1B |
| 87 | mbar_0 dd ? ; 0x1C |
87 | mbar_0 dd ? ; 0x1C |
| 88 | mlimit_0 dd ? ; 0x20 |
88 | mlimit_0 dd ? ; 0x20 |
| 89 | mbar_1 dd ? ; 0x24 |
89 | mbar_1 dd ? ; 0x24 |
| 90 | mlimit_1 dd ? ; 0x28 |
90 | mlimit_1 dd ? ; 0x28 |
| 91 | iobar_0 dd ? ; 0x2C |
91 | iobar_0 dd ? ; 0x2C |
| 92 | iolimit_0 dd ? ; 0x30 |
92 | iolimit_0 dd ? ; 0x30 |
| 93 | iobar_1 dd ? ; 0x34 |
93 | iobar_1 dd ? ; 0x34 |
| 94 | iolimit_1 dd ? ; 0x38 |
94 | iolimit_1 dd ? ; 0x38 |
| 95 | interrupt_line db ? ; 0x3C |
95 | interrupt_line db ? ; 0x3C |
| 96 | interrupt_pin db ? ; 0x3D |
96 | interrupt_pin db ? ; 0x3D |
| 97 | bridge_ctrl dw ? ; 0x3E |
97 | bridge_ctrl dw ? ; 0x3E |
| 98 | subs_did dw ? ; 0x40 |
98 | subs_did dw ? ; 0x40 |
| 99 | subs_vid dw ? ; 0x42 |
99 | subs_vid dw ? ; 0x42 |
| 100 | legacy_bar dd ? ; 0x44 |
100 | legacy_bar dd ? ; 0x44 |
| 101 | 101 | ||
| 102 | ends |
102 | ends |
| 103 | 103 | ||
| 104 | ; Base address bits |
104 | ; Base address bits |
| 105 | PCI_BASE_ADDRESS_SPACE_IO = 0x01 |
105 | PCI_BASE_ADDRESS_SPACE_IO = 0x01 |
| 106 | PCI_BASE_ADDRESS_IO_MASK = 0xFFFFFFFC |
106 | PCI_BASE_ADDRESS_IO_MASK = 0xFFFFFFFC |
| 107 | PCI_BASE_ADDRESS_MEM_MASK = 0xFFFFFFF0 |
107 | PCI_BASE_ADDRESS_MEM_MASK = 0xFFFFFFF0 |
| - | 108 | PCI_BASE_ADDRESS_MEM_TYPE_MASK = 0x00000006 |
|
| - | 109 | PCI_BASE_ADDRESS_MEM_TYPE_32 = 0x0 |
|
| - | 110 | PCI_BASE_ADDRESS_MEM_TYPE_RESERVED = 0x02 |
|
| - | 111 | PCI_BASE_ADDRESS_MEM_TYPE_64 = 0x4 |
|
| - | 112 | ||
| 108 | 113 | ||
| 109 | ; command bits |
114 | ; command bits |
| 110 | PCI_CMD_PIO = 0x01 ; bit0: io space control |
115 | PCI_CMD_PIO = 0x01 ; bit0: io space control |
| 111 | PCI_CMD_MMIO = 0x02 ; bit1: memory space control |
116 | PCI_CMD_MMIO = 0x02 ; bit1: memory space control |
| 112 | PCI_CMD_MASTER = 0x04 ; bit2: device acts as a PCI master |
117 | PCI_CMD_MASTER = 0x04 ; bit2: device acts as a PCI master |
| - | 118 | PCI_CMD_INTX_DISABLE = 0x400 ; INTx emulation disable |
|
| 113 | 119 | ||
| 114 | ; status bits |
120 | ; status bits |
| 115 | PCI_STATUS_CAPA = 0x10 ; bit4: new capabilities available |
121 | PCI_STATUS_CAPA = 0x10 ; bit4: new capabilities available |
| 116 | 122 | ||
| 117 | 123 | ||
| 118 | if used PCI_find_io |
124 | if used PCI_find_io |
| 119 | proc PCI_find_io stdcall bus, dev |
125 | proc PCI_find_io stdcall bus, dev |
| 120 | 126 | ||
| 121 | push esi |
127 | push esi |
| 122 | xor eax, eax |
128 | xor eax, eax |
| 123 | mov esi, PCI_header00.base_addr_0 |
129 | mov esi, PCI_header00.base_addr_0 |
| 124 | .check: |
130 | .check: |
| 125 | invoke PciRead32, [bus], [dev], esi |
131 | invoke PciRead32, [bus], [dev], esi |
| 126 | test eax, PCI_BASE_ADDRESS_IO_MASK |
132 | test eax, PCI_BASE_ADDRESS_IO_MASK |
| 127 | jz .inc |
133 | jz .inc |
| 128 | test eax, PCI_BASE_ADDRESS_SPACE_IO |
134 | test eax, PCI_BASE_ADDRESS_SPACE_IO |
| 129 | jz .inc |
135 | jz .inc |
| 130 | and eax, PCI_BASE_ADDRESS_IO_MASK |
136 | and eax, PCI_BASE_ADDRESS_IO_MASK |
| 131 | pop esi |
137 | pop esi |
| 132 | ret |
138 | ret |
| 133 | 139 | ||
| 134 | .inc: |
140 | .inc: |
| 135 | add esi, 4 |
141 | add esi, 4 |
| 136 | cmp esi, PCI_header00.base_addr_5 |
142 | cmp esi, PCI_header00.base_addr_5 |
| 137 | jbe .check |
143 | jbe .check |
| 138 | pop esi |
144 | pop esi |
| 139 | xor eax, eax |
145 | xor eax, eax |
| 140 | ret |
146 | ret |
| 141 | 147 | ||
| 142 | endp |
148 | endp |
| 143 | end if |
149 | end if |
| 144 | 150 | ||
| 145 | 151 | ||
| 146 | if used PCI_find_mmio32 |
152 | if used PCI_find_mmio |
| 147 | proc PCI_find_mmio32 stdcall bus, dev |
153 | proc PCI_find_mmio stdcall bus, dev |
| 148 | 154 | ||
| 149 | push esi |
155 | push esi ebx |
| 150 | mov esi, PCI_header00.base_addr_0 |
156 | mov esi, PCI_header00.base_addr_0 |
| 151 | .check: |
157 | .check: |
| 152 | invoke PciRead32, [bus], [dev], esi |
158 | invoke PciRead32, [bus], [dev], esi |
| - | 159 | DEBUGF 1, "BAR: 0x%x\n", eax |
|
| - | 160 | mov ebx, eax |
|
| 153 | test eax, PCI_BASE_ADDRESS_SPACE_IO ; mmio address? |
161 | test eax, PCI_BASE_ADDRESS_SPACE_IO ; MMIO address? |
| 154 | jnz .inc |
162 | jnz .next |
| 155 | test eax, 100b ; 64 bit? |
163 | and ebx, PCI_BASE_ADDRESS_MEM_TYPE_MASK |
| - | 164 | cmp bl, PCI_BASE_ADDRESS_MEM_TYPE_64 |
|
| 156 | jnz .inc |
165 | je .is64 |
| - | 166 | cmp bl, PCI_BASE_ADDRESS_MEM_TYPE_32 |
|
| 157 | and eax, not 1111b |
167 | jne .next |
| - | 168 | ; Ok, we have a 32-bit BAR. |
|
| - | 169 | and eax, PCI_BASE_ADDRESS_MEM_MASK |
|
| 158 | pop esi |
170 | pop ebx esi |
| - | 171 | DEBUGF 1, "32-bit MMIO address found: 0x%x\n", eax |
|
| 159 | ret |
172 | ret |
| 160 | 173 | ||
| - | 174 | .is64: |
|
| - | 175 | ; Ok, we have a 64-bit BAR, check if the upper 32-bits are 0, then we can use it.. |
|
| - | 176 | push eax |
|
| - | 177 | add esi, 4 |
|
| - | 178 | cmp esi, PCI_header00.base_addr_5 |
|
| - | 179 | ja .fail |
|
| - | 180 | invoke PciRead32, [bus], [dev], esi |
|
| - | 181 | test eax, eax |
|
| - | 182 | pop eax |
|
| - | 183 | jnz .next |
|
| - | 184 | and eax, PCI_BASE_ADDRESS_MEM_MASK |
|
| - | 185 | pop ebx esi |
|
| - | 186 | DEBUGF 1, "64-bit MMIO address found: 0x00000000%x\n", eax |
|
| - | 187 | ret |
|
| - | 188 | ||
| 161 | .inc: |
189 | .next: |
| 162 | add esi, 4 |
190 | add esi, 4 |
| 163 | cmp esi, PCI_header00.base_addr_5 |
191 | cmp esi, PCI_header00.base_addr_5 |
| 164 | jbe .check |
192 | jbe .check |
| - | 193 | .fail: |
|
| 165 | xor eax, eax |
194 | xor eax, eax |
| 166 | pop esi |
195 | pop ebx esi |
| - | 196 | DEBUGF 1, "No usable MMIO addresses found!\n" |
|
| 167 | ret |
197 | ret |
| 168 | 198 | ||
| 169 | endp |
199 | endp |
| 170 | end if |
200 | end if |