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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;                                                                 ;;
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;;                                                                 ;;
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;; Copyright (C) KolibriOS team 2004-2015. All rights reserved.    ;;
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;; Copyright (C) KolibriOS team 2004-2018. All rights reserved.    ;;
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;; Distributed under terms of the GNU General Public License       ;;
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;; Distributed under terms of the GNU General Public License       ;;
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;;                                                                 ;;
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;;                                                                 ;;
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;;          GNU GENERAL PUBLIC LICENSE                             ;;
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;;          GNU GENERAL PUBLIC LICENSE                             ;;
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;;             Version 2, June 1991                                ;;
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;;             Version 2, June 1991                                ;;
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;;                                                                 ;;
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;;                                                                 ;;
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; Base address bits
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; Base address bits
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        PCI_BASE_ADDRESS_SPACE_IO       = 0x01
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        PCI_BASE_ADDRESS_SPACE_IO               = 0x01
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        PCI_BASE_ADDRESS_IO_MASK        = 0xFFFFFFFC
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        PCI_BASE_ADDRESS_IO_MASK                = 0xFFFFFFFC
-
 
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        PCI_BASE_ADDRESS_MEM_MASK               = 0xFFFFFFF0
-
 
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        PCI_BASE_ADDRESS_MEM_TYPE_MASK          = 0x00000006
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        PCI_BASE_ADDRESS_MEM_TYPE_32            = 0x0
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        PCI_BASE_ADDRESS_MEM_TYPE_RESERVED      = 0x02
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        PCI_BASE_ADDRESS_MEM_TYPE_64            = 0x4
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        PCI_BASE_ADDRESS_MEM_MASK       = 0xFFFFFFF0
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; command bits
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; command bits
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        PCI_CMD_PIO                     = 0x01          ; bit0: io space control
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        PCI_CMD_PIO                     = 0x01          ; bit0: io space control
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        PCI_CMD_MMIO                    = 0x02          ; bit1: memory space control
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        PCI_CMD_MMIO                    = 0x02          ; bit1: memory space control
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        PCI_CMD_MASTER                  = 0x04          ; bit2: device acts as a PCI master
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        PCI_CMD_MASTER                  = 0x04          ; bit2: device acts as a PCI master
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        PCI_CMD_INTX_DISABLE            = 0x400         ; INTx emulation disable
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endp
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endp
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end if
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end if
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if used PCI_find_mmio32
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if used PCI_find_mmio
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proc PCI_find_mmio32 stdcall bus, dev
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proc PCI_find_mmio stdcall bus, dev
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-
 
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        push    esi ebx
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        mov     esi, PCI_header00.base_addr_0
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        push    esi
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  .check:
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        mov     esi, PCI_header00.base_addr_0
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        invoke  PciRead32, [bus], [dev], esi
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  .check:
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        DEBUGF  1, "BAR: 0x%x\n", eax
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        mov     ebx, eax
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        invoke  PciRead32, [bus], [dev], esi
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        test    eax, PCI_BASE_ADDRESS_SPACE_IO  ; MMIO address?
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        jnz     .next
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        test    eax, PCI_BASE_ADDRESS_SPACE_IO  ; mmio address?
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        and     ebx, PCI_BASE_ADDRESS_MEM_TYPE_MASK
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        cmp     bl, PCI_BASE_ADDRESS_MEM_TYPE_64
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        je      .is64
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        jnz     .inc
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        cmp     bl, PCI_BASE_ADDRESS_MEM_TYPE_32
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        jne     .next
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        test    eax, 100b       ; 64 bit?
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        ; Ok, we have a 32-bit BAR.
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        jnz     .inc
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        and     eax, PCI_BASE_ADDRESS_MEM_MASK
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        pop     ebx esi
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        DEBUGF  1, "32-bit MMIO address found: 0x%x\n", eax
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        ret
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  .is64:
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        ; Ok, we have a 64-bit BAR, check if the upper 32-bits are 0, then we can use it..
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        push    eax
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        add     esi, 4
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        cmp     esi, PCI_header00.base_addr_5
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        ja      .fail
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        invoke  PciRead32, [bus], [dev], esi
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        test    eax, eax
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        pop     eax
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        jnz     .next
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        and     eax, PCI_BASE_ADDRESS_MEM_MASK
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        and     eax, not 1111b
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        pop     ebx esi
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        pop     esi
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        DEBUGF  1, "64-bit MMIO address found: 0x00000000%x\n", eax
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        ret
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        ret
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  .next:
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  .inc:
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        add     esi, 4
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        cmp     esi, PCI_header00.base_addr_5
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        add     esi, 4
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        jbe     .check
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        cmp     esi, PCI_header00.base_addr_5
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  .fail:
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        jbe     .check
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        xor     eax, eax
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        xor     eax, eax
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        pop     ebx esi