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Rev 1970 Rev 2967
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#define PCI_ATS_CTRL		0x06	/* ATS Control Register */
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#define PCI_ATS_CTRL		0x06	/* ATS Control Register */
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#define  PCI_ATS_CTRL_ENABLE	0x8000	/* ATS Enable */
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#define  PCI_ATS_CTRL_ENABLE	0x8000	/* ATS Enable */
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#define  PCI_ATS_CTRL_STU(x)	((x) & 0x1f)	/* Smallest Translation Unit */
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#define  PCI_ATS_CTRL_STU(x)	((x) & 0x1f)	/* Smallest Translation Unit */
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#define  PCI_ATS_MIN_STU	12	/* shift of minimum STU block */
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#define  PCI_ATS_MIN_STU	12	/* shift of minimum STU block */
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/* Page Request Interface */
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#define PCI_PRI_CAP		0x13    /* PRI capability ID */
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#define PCI_PRI_CONTROL_OFF	0x04	/* Offset of control register */
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#define PCI_PRI_STATUS_OFF	0x06	/* Offset of status register */
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#define PCI_PRI_ENABLE		0x0001	/* Enable mask */
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#define PCI_PRI_RESET		0x0002	/* Reset bit mask */
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#define PCI_PRI_STATUS_RF	0x0001  /* Request Failure */
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#define PCI_PRI_STATUS_UPRGI	0x0002  /* Unexpected PRG index */
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#define PCI_PRI_STATUS_STOPPED	0x0100  /* PRI Stopped */
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#define PCI_PRI_MAX_REQ_OFF	0x08	/* Cap offset for max reqs supported */
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#define PCI_PRI_ALLOC_REQ_OFF	0x0c	/* Cap offset for max reqs allowed */
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/* PASID capability */
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#define PCI_PASID_CAP		0x1b    /* PASID capability ID */
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#define PCI_PASID_CAP_OFF	0x04    /* PASID feature register */
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#define PCI_PASID_CONTROL_OFF   0x06    /* PASID control register */
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#define PCI_PASID_ENABLE	0x01	/* Enable/Supported bit */
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#define PCI_PASID_EXEC		0x02	/* Exec permissions Enable/Supported */
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#define PCI_PASID_PRIV		0x04	/* Priviledge Mode Enable/Support */
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/* Single Root I/O Virtualization */
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/* Single Root I/O Virtualization */
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#define PCI_SRIOV_CAP		0x04	/* SR-IOV Capabilities */
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#define PCI_SRIOV_CAP		0x04	/* SR-IOV Capabilities */
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#define  PCI_SRIOV_CAP_VFM	0x01	/* VF Migration Capable */
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#define  PCI_SRIOV_CAP_VFM	0x01	/* VF Migration Capable */
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#define  PCI_SRIOV_CAP_INTR(x)	((x) >> 21) /* Interrupt Message Number */
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#define  PCI_SRIOV_CAP_INTR(x)	((x) >> 21) /* Interrupt Message Number */