Rev 1628 | Rev 2967 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 1628 | Rev 1970 | ||
---|---|---|---|
Line 221... | Line 221... | ||
221 | #define PCI_PM_PMC 2 /* PM Capabilities Register */ |
221 | #define PCI_PM_PMC 2 /* PM Capabilities Register */ |
222 | #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ |
222 | #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ |
223 | #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ |
223 | #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ |
224 | #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ |
224 | #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ |
225 | #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ |
225 | #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ |
226 | #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */ |
226 | #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxiliary power support mask */ |
227 | #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ |
227 | #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ |
228 | #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ |
228 | #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ |
229 | #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ |
229 | #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ |
230 | #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */ |
230 | #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */ |
231 | #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ |
231 | #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ |
Line 298... | Line 298... | ||
298 | #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ |
298 | #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ |
299 | #define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */ |
299 | #define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */ |
300 | #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ |
300 | #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ |
301 | #define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ |
301 | #define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ |
Line 302... | Line 302... | ||
302 | 302 | ||
303 | /* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */ |
303 | /* MSI-X registers */ |
304 | #define PCI_MSIX_FLAGS 2 |
304 | #define PCI_MSIX_FLAGS 2 |
305 | #define PCI_MSIX_FLAGS_QSIZE 0x7FF |
305 | #define PCI_MSIX_FLAGS_QSIZE 0x7FF |
306 | #define PCI_MSIX_FLAGS_ENABLE (1 << 15) |
306 | #define PCI_MSIX_FLAGS_ENABLE (1 << 15) |
- | 307 | #define PCI_MSIX_FLAGS_MASKALL (1 << 14) |
|
- | 308 | #define PCI_MSIX_TABLE 4 |
|
307 | #define PCI_MSIX_FLAGS_MASKALL (1 << 14) |
309 | #define PCI_MSIX_PBA 8 |
Line -... | Line 310... | ||
- | 310 | #define PCI_MSIX_FLAGS_BIRMASK (7 << 0) |
|
- | 311 | ||
- | 312 | /* MSI-X entry's format */ |
|
- | 313 | #define PCI_MSIX_ENTRY_SIZE 16 |
|
- | 314 | #define PCI_MSIX_ENTRY_LOWER_ADDR 0 |
|
- | 315 | #define PCI_MSIX_ENTRY_UPPER_ADDR 4 |
|
- | 316 | #define PCI_MSIX_ENTRY_DATA 8 |
|
- | 317 | #define PCI_MSIX_ENTRY_VECTOR_CTRL 12 |
|
308 | #define PCI_MSIX_FLAGS_BIRMASK (7 << 0) |
318 | #define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 |
Line 309... | Line 319... | ||
309 | 319 | ||
310 | /* CompactPCI Hotswap Register */ |
320 | /* CompactPCI Hotswap Register */ |
311 | 321 | ||
Line 423... | Line 433... | ||
423 | #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ |
433 | #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ |
424 | #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ |
434 | #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ |
425 | #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ |
435 | #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ |
426 | #define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */ |
436 | #define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */ |
427 | #define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* L1 Clock Power Management */ |
437 | #define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* L1 Clock Power Management */ |
428 | #define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Suprise Down Error Reporting Capable */ |
438 | #define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Surprise Down Error Reporting Capable */ |
429 | #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ |
439 | #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ |
430 | #define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */ |
440 | #define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */ |
431 | #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ |
441 | #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ |
432 | #define PCI_EXP_LNKCTL 16 /* Link Control */ |
442 | #define PCI_EXP_LNKCTL 16 /* Link Control */ |
433 | #define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ |
443 | #define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ |
Line 492... | Line 502... | ||
492 | #define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */ |
502 | #define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */ |
493 | #define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */ |
503 | #define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */ |
494 | #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ |
504 | #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ |
495 | #define PCI_EXP_RTCAP 30 /* Root Capabilities */ |
505 | #define PCI_EXP_RTCAP 30 /* Root Capabilities */ |
496 | #define PCI_EXP_RTSTA 32 /* Root Status */ |
506 | #define PCI_EXP_RTSTA 32 /* Root Status */ |
- | 507 | #define PCI_EXP_RTSTA_PME 0x10000 /* PME status */ |
|
- | 508 | #define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */ |
|
497 | #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ |
509 | #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ |
498 | #define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */ |
510 | #define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */ |
- | 511 | #define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */ |
|
- | 512 | #define PCI_EXP_OBFF_MASK 0xc0000 /* OBFF support mechanism */ |
|
- | 513 | #define PCI_EXP_OBFF_MSG 0x40000 /* New message signaling */ |
|
- | 514 | #define PCI_EXP_OBFF_WAKE 0x80000 /* Re-use WAKE# for OBFF */ |
|
499 | #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ |
515 | #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ |
500 | #define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */ |
516 | #define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */ |
- | 517 | #define PCI_EXP_IDO_REQ_EN 0x100 /* ID-based ordering request enable */ |
|
- | 518 | #define PCI_EXP_IDO_CMP_EN 0x200 /* ID-based ordering completion enable */ |
|
- | 519 | #define PCI_EXP_LTR_EN 0x400 /* Latency tolerance reporting */ |
|
- | 520 | #define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */ |
|
- | 521 | #define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */ |
|
- | 522 | #define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ |
|
501 | #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ |
523 | #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ |
502 | #define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ |
524 | #define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ |
Line 503... | Line 525... | ||
503 | 525 | ||
504 | /* Extended Capabilities (PCI-X 2.0 and Express) */ |
526 | /* Extended Capabilities (PCI-X 2.0 and Express) */ |
Line 513... | Line 535... | ||
513 | #define PCI_EXT_CAP_ID_VNDR 11 |
535 | #define PCI_EXT_CAP_ID_VNDR 11 |
514 | #define PCI_EXT_CAP_ID_ACS 13 |
536 | #define PCI_EXT_CAP_ID_ACS 13 |
515 | #define PCI_EXT_CAP_ID_ARI 14 |
537 | #define PCI_EXT_CAP_ID_ARI 14 |
516 | #define PCI_EXT_CAP_ID_ATS 15 |
538 | #define PCI_EXT_CAP_ID_ATS 15 |
517 | #define PCI_EXT_CAP_ID_SRIOV 16 |
539 | #define PCI_EXT_CAP_ID_SRIOV 16 |
- | 540 | #define PCI_EXT_CAP_ID_LTR 24 |
|
Line 518... | Line 541... | ||
518 | 541 | ||
519 | /* Advanced Error Reporting */ |
542 | /* Advanced Error Reporting */ |
520 | #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ |
543 | #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ |
521 | #define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ |
544 | #define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ |
Line 669... | Line 692... | ||
669 | #define PCI_SRIOV_VFM_UA 0x0 /* Inactive.Unavailable */ |
692 | #define PCI_SRIOV_VFM_UA 0x0 /* Inactive.Unavailable */ |
670 | #define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */ |
693 | #define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */ |
671 | #define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */ |
694 | #define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */ |
672 | #define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */ |
695 | #define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */ |
Line -... | Line 696... | ||
- | 696 | ||
- | 697 | #define PCI_LTR_MAX_SNOOP_LAT 0x4 |
|
- | 698 | #define PCI_LTR_MAX_NOSNOOP_LAT 0x6 |
|
- | 699 | #define PCI_LTR_VALUE_MASK 0x000003ff |
|
- | 700 | #define PCI_LTR_SCALE_MASK 0x00001c00 |
|
- | 701 | #define PCI_LTR_SCALE_SHIFT 10 |
|
673 | 702 | ||
674 | /* Access Control Service */ |
703 | /* Access Control Service */ |
675 | #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ |
704 | #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ |
676 | #define PCI_ACS_SV 0x01 /* Source Validation */ |
705 | #define PCI_ACS_SV 0x01 /* Source Validation */ |
677 | #define PCI_ACS_TB 0x02 /* Translation Blocking */ |
706 | #define PCI_ACS_TB 0x02 /* Translation Blocking */ |