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 *	PCI BIOS Specification
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 *	PCI BIOS Specification
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 *	PCI Local Bus Specification
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 *	PCI Local Bus Specification
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 *	PCI to PCI Bridge Specification
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 *	PCI to PCI Bridge Specification
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 *	PCI System Design Guide
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 *	PCI System Design Guide
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 */
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 */
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#ifndef LINUX_PCI_H
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#ifndef LINUX_PCI_H
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#define LINUX_PCI_H
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#define LINUX_PCI_H
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#include 
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#include 
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#include 
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#include 
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#include 	/* The pci register defines */
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#include 	/* The pci register defines */
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#define PCI_D2		((pci_power_t __force) 2)
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#define PCI_D2		((pci_power_t __force) 2)
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#define PCI_D3hot	((pci_power_t __force) 3)
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#define PCI_D3hot	((pci_power_t __force) 3)
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#define PCI_D3cold	((pci_power_t __force) 4)
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#define PCI_D3cold	((pci_power_t __force) 4)
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#define PCI_UNKNOWN	((pci_power_t __force) 5)
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#define PCI_UNKNOWN	((pci_power_t __force) 5)
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#define PCI_POWER_ERROR	((pci_power_t __force) -1)
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#define PCI_POWER_ERROR	((pci_power_t __force) -1)
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/* Remember to update this when the list above changes! */
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extern const char *pci_power_names[];
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281
 
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static inline const char *pci_power_name(pci_power_t state)
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283
{
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	return pci_power_names[1 + (int) state];
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}
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286
 
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#define PCI_PM_D2_DELAY		200
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#define PCI_PM_D3_WAIT		10
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#define PCI_PM_D3COLD_WAIT	100
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#define PCI_PM_BUS_WAIT		50
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/** The pci_channel state describes connectivity between the CPU and
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/** The pci_channel state describes connectivity between the CPU and
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 *  the pci device.  If some PCI bus between here and the pci device
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 *  the pci device.  If some PCI bus between here and the pci device
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 *  has crashed or locked up, this info is reflected here.
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 *  has crashed or locked up, this info is reflected here.
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 */
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 */
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typedef unsigned int __bitwise pci_channel_state_t;
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typedef unsigned int __bitwise pci_channel_state_t;
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	unsigned short	subsystem_device;
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	unsigned short	subsystem_device;
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	unsigned int	class;		/* 3 bytes: (base,sub,prog-if) */
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	unsigned int	class;		/* 3 bytes: (base,sub,prog-if) */
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	u8		revision;	/* PCI revision, low byte of class word */
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	u8		revision;	/* PCI revision, low byte of class word */
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	u8		hdr_type;	/* PCI header type (`multi' flag masked out) */
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	u8		hdr_type;	/* PCI header type (`multi' flag masked out) */
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	u8		pcie_cap;	/* PCI-E capability offset */
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	u8		pcie_cap;	/* PCI-E capability offset */
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	u8		pcie_type;	/* PCI-E device/port type */
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	u8		pcie_mpss:3;	/* PCI-E Max Payload Size Supported */
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	u8		rom_base_reg;	/* which config register controls the ROM */
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	u8		rom_base_reg;	/* which config register controls the ROM */
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	u8		pin;  		/* which interrupt pin this device uses */
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	u8		pin;  		/* which interrupt pin this device uses */
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365
	u16		pcie_flags_reg;	/* cached PCI-E Capabilities Register */
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366
 
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 //   struct pci_driver *driver;  /* which driver has allocated this device */
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 //   struct pci_driver *driver;  /* which driver has allocated this device */
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    uint64_t     dma_mask;   /* Mask of the bits of bus address this
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    uint64_t     dma_mask;   /* Mask of the bits of bus address this
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                       device implements.  Normally this is
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                       device implements.  Normally this is
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	int		pm_cap;		/* PM capability offset in the
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	int		pm_cap;		/* PM capability offset in the
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					   configuration space */
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					   configuration space */
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    unsigned int    pme_support:5;  /* Bitmask of states from which PME#
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    unsigned int    pme_support:5;  /* Bitmask of states from which PME#
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                       can be generated */
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                       can be generated */
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	unsigned int	pme_interrupt:1;
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	unsigned int	pme_interrupt:1;
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	unsigned int	pme_poll:1;	/* Poll device's PME status bit */
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    unsigned int    d1_support:1;   /* Low power state D1 is supported */
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    unsigned int    d1_support:1;   /* Low power state D1 is supported */
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    unsigned int    d2_support:1;   /* Low power state D2 is supported */
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    unsigned int    d2_support:1;   /* Low power state D2 is supported */
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    unsigned int    no_d1d2:1;  /* Only allow D0 and D3 */
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	unsigned int	no_d1d2:1;	/* D1 and D2 are forbidden */
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	unsigned int	no_d3cold:1;	/* D3cold is forbidden */
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	unsigned int	d3cold_allowed:1;	/* D3cold is allowed by user */
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	unsigned int	mmio_always_on:1;	/* disallow turning off io/mem
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	unsigned int	mmio_always_on:1;	/* disallow turning off io/mem
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						   decoding during bar sizing */
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						   decoding during bar sizing */
375
	unsigned int	wakeup_prepared:1;
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	unsigned int	wakeup_prepared:1;
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	unsigned int	runtime_d3cold:1;	/* whether go through runtime
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						   D3cold, not set for devices
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395
						   powered on/off by the
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						   corresponding bridge */
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	unsigned int	d3_delay;	/* D3->D0 transition time in ms */
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	unsigned int	d3_delay;	/* D3->D0 transition time in ms */
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	unsigned int	d3cold_delay;	/* D3cold->D0 transition time in ms */
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#ifdef CONFIG_PCIEASPM
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	struct pcie_link_state	*link_state;	/* ASPM link state. */
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402
#endif
378
 
403
 
379
	pci_channel_state_t error_state;	/* current connectivity state */
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	pci_channel_state_t error_state;	/* current connectivity state */
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    struct  device  dev;        /* Generic device interface */
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    struct  device  dev;        /* Generic device interface */
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     * Instead of touching interrupt line and base address registers
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     * Instead of touching interrupt line and base address registers
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     * directly, use the values stored here. They might be different!
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     * directly, use the values stored here. They might be different!
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     */
412
     */
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    unsigned int    irq;
413
    unsigned int    irq;
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    struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
414
    struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
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	resource_size_t	fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */
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415
 
392
    /* These fields are used by common fixups */
416
    /* These fields are used by common fixups */
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    unsigned int    transparent:1;  /* Transparent PCI bridge */
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    unsigned int    transparent:1;  /* Transparent PCI bridge */
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    unsigned int    multifunction:1;/* Part of multi-function device */
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    unsigned int    multifunction:1;/* Part of multi-function device */
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    /* keep track of device state */
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    /* keep track of device state */
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    unsigned int    is_added:1;
420
    unsigned int    is_added:1;
397
    unsigned int    is_busmaster:1; /* device is busmaster */
421
    unsigned int    is_busmaster:1; /* device is busmaster */
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    unsigned int    no_msi:1;   /* device may not use msi */
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    unsigned int    no_msi:1;   /* device may not use msi */
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    unsigned int    block_ucfg_access:1;    /* userspace config space access is blocked */
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	unsigned int	block_cfg_access:1;	/* config space access is blocked */
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    unsigned int    broken_parity_status:1; /* Device generates false positive parity */
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    unsigned int    broken_parity_status:1; /* Device generates false positive parity */
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    unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
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    unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
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    unsigned int    msi_enabled:1;
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    unsigned int    msi_enabled:1;
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    unsigned int    msix_enabled:1;
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    unsigned int    msix_enabled:1;
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    unsigned int    state_saved:1;
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    unsigned int    state_saved:1;
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    unsigned int    is_physfn:1;
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    unsigned int    is_physfn:1;
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    unsigned int    is_virtfn:1;
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    unsigned int    is_virtfn:1;
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	unsigned int	reset_fn:1;
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	unsigned int	reset_fn:1;
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	unsigned int    is_hotplug_bridge:1;
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	unsigned int    is_hotplug_bridge:1;
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	unsigned int    __aer_firmware_first_valid:1;
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	unsigned int	__aer_firmware_first:1;
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	unsigned int	broken_intx_masking:1;
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	unsigned int	io_window_1k:1;	/* Intel P2P bridge 1K I/O windows */
414
//    pci_dev_flags_t dev_flags;
442
//	pci_dev_flags_t dev_flags;
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//    atomic_t    enable_cnt;   /* pci_enable_device has been called */
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	atomic_t	enable_cnt;	/* pci_enable_device has been called */
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//    u32     saved_config_space[16]; /* config space saved at suspend time */
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//    struct hlist_head saved_cap_space;
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//    struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
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//    int rom_attr_enabled;       /* has display of the rom attribute been enabled? */
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//    struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
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//    struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
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423
};
447
};
424
 
448
 
425
#define pci_resource_start(dev, bar)    ((dev)->resource[(bar)].start)
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#define pci_resource_start(dev, bar)    ((dev)->resource[(bar)].start)
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    struct list_head devices;   /* list of devices on this bus */
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    struct list_head devices;   /* list of devices on this bus */
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    struct pci_dev  *self;      /* bridge device as seen by parent */
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    struct pci_dev  *self;      /* bridge device as seen by parent */
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    struct list_head slots;     /* list of slots on this bus */
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    struct list_head slots;     /* list of slots on this bus */
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    struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
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    struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
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    struct list_head resources; /* address space routed to this bus */
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    struct list_head resources; /* address space routed to this bus */
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	struct resource busn_res;	/* bus numbers routed to this bus */
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471
 
447
    struct pci_ops  *ops;       /* configuration access functions */
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    struct pci_ops  *ops;       /* configuration access functions */
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    void        *sysdata;   /* hook for sys-specific extension */
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    void        *sysdata;   /* hook for sys-specific extension */
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    struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
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    struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
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475
 
451
    unsigned char   number;     /* bus number */
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    unsigned char   primary;    /* number of primary bridge */
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    unsigned char   secondary;  /* number of secondary bridge */
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    unsigned char   number;     /* bus number */
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    unsigned char   subordinate;    /* max number of subordinate buses */
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    unsigned char   primary;    /* number of primary bridge */
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    unsigned char   max_bus_speed;  /* enum pci_bus_speed */
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    unsigned char   max_bus_speed;  /* enum pci_bus_speed */
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static inline bool pci_is_pcie(struct pci_dev *dev)
592
static inline bool pci_is_pcie(struct pci_dev *dev)
570
{
593
{
571
    return !!pci_pcie_cap(dev);
594
    return !!pci_pcie_cap(dev);
572
}
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}
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596
 
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597
/**
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598
 * pci_pcie_type - get the PCIe device/port type
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599
 * @dev: PCI device
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600
 */
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601
static inline int pci_pcie_type(const struct pci_dev *dev)
-
 
602
{
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603
	return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4;
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604
}
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605
 
573
 
606
 
574
static inline int pci_iov_init(struct pci_dev *dev)
607
static inline int pci_iov_init(struct pci_dev *dev)
575
{
608
{
576
    return -ENODEV;
609
    return -ENODEV;
577
}
610
}