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11 | * PCI BIOS Specification |
11 | * PCI BIOS Specification |
12 | * PCI Local Bus Specification |
12 | * PCI Local Bus Specification |
13 | * PCI to PCI Bridge Specification |
13 | * PCI to PCI Bridge Specification |
14 | * PCI System Design Guide |
14 | * PCI System Design Guide |
15 | */ |
15 | */ |
16 | - | ||
17 | #ifndef LINUX_PCI_H |
16 | #ifndef LINUX_PCI_H |
18 | #define LINUX_PCI_H |
17 | #define LINUX_PCI_H |
Line 19... | Line 18... | ||
19 | 18 | ||
20 | #include |
19 | #include |
21 | #include |
20 | #include |
22 | #include |
21 | #include |
Line 274... | Line 273... | ||
274 | #define PCI_D2 ((pci_power_t __force) 2) |
273 | #define PCI_D2 ((pci_power_t __force) 2) |
275 | #define PCI_D3hot ((pci_power_t __force) 3) |
274 | #define PCI_D3hot ((pci_power_t __force) 3) |
276 | #define PCI_D3cold ((pci_power_t __force) 4) |
275 | #define PCI_D3cold ((pci_power_t __force) 4) |
277 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
276 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
278 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
277 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
- | 278 | ||
- | 279 | /* Remember to update this when the list above changes! */ |
|
- | 280 | extern const char *pci_power_names[]; |
|
- | 281 | ||
- | 282 | static inline const char *pci_power_name(pci_power_t state) |
|
- | 283 | { |
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- | 284 | return pci_power_names[1 + (int) state]; |
|
- | 285 | } |
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- | 286 | ||
- | 287 | #define PCI_PM_D2_DELAY 200 |
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- | 288 | #define PCI_PM_D3_WAIT 10 |
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- | 289 | #define PCI_PM_D3COLD_WAIT 100 |
|
- | 290 | #define PCI_PM_BUS_WAIT 50 |
|
- | 291 | ||
279 | /** The pci_channel state describes connectivity between the CPU and |
292 | /** The pci_channel state describes connectivity between the CPU and |
280 | * the pci device. If some PCI bus between here and the pci device |
293 | * the pci device. If some PCI bus between here and the pci device |
281 | * has crashed or locked up, this info is reflected here. |
294 | * has crashed or locked up, this info is reflected here. |
282 | */ |
295 | */ |
283 | typedef unsigned int __bitwise pci_channel_state_t; |
296 | typedef unsigned int __bitwise pci_channel_state_t; |
Line 344... | Line 357... | ||
344 | unsigned short subsystem_device; |
357 | unsigned short subsystem_device; |
345 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ |
358 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ |
346 | u8 revision; /* PCI revision, low byte of class word */ |
359 | u8 revision; /* PCI revision, low byte of class word */ |
347 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
360 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
348 | u8 pcie_cap; /* PCI-E capability offset */ |
361 | u8 pcie_cap; /* PCI-E capability offset */ |
349 | u8 pcie_type; /* PCI-E device/port type */ |
362 | u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ |
350 | u8 rom_base_reg; /* which config register controls the ROM */ |
363 | u8 rom_base_reg; /* which config register controls the ROM */ |
351 | u8 pin; /* which interrupt pin this device uses */ |
364 | u8 pin; /* which interrupt pin this device uses */ |
- | 365 | u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */ |
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Line 352... | Line 366... | ||
352 | 366 | ||
353 | // struct pci_driver *driver; /* which driver has allocated this device */ |
367 | // struct pci_driver *driver; /* which driver has allocated this device */ |
354 | uint64_t dma_mask; /* Mask of the bits of bus address this |
368 | uint64_t dma_mask; /* Mask of the bits of bus address this |
355 | device implements. Normally this is |
369 | device implements. Normally this is |
Line 365... | Line 379... | ||
365 | int pm_cap; /* PM capability offset in the |
379 | int pm_cap; /* PM capability offset in the |
366 | configuration space */ |
380 | configuration space */ |
367 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
381 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
368 | can be generated */ |
382 | can be generated */ |
369 | unsigned int pme_interrupt:1; |
383 | unsigned int pme_interrupt:1; |
- | 384 | unsigned int pme_poll:1; /* Poll device's PME status bit */ |
|
370 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
385 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
371 | unsigned int d2_support:1; /* Low power state D2 is supported */ |
386 | unsigned int d2_support:1; /* Low power state D2 is supported */ |
372 | unsigned int no_d1d2:1; /* Only allow D0 and D3 */ |
387 | unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ |
- | 388 | unsigned int no_d3cold:1; /* D3cold is forbidden */ |
|
- | 389 | unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ |
|
373 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
390 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
374 | decoding during bar sizing */ |
391 | decoding during bar sizing */ |
375 | unsigned int wakeup_prepared:1; |
392 | unsigned int wakeup_prepared:1; |
- | 393 | unsigned int runtime_d3cold:1; /* whether go through runtime |
|
- | 394 | D3cold, not set for devices |
|
- | 395 | powered on/off by the |
|
- | 396 | corresponding bridge */ |
|
376 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
397 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
- | 398 | unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ |
|
Line -... | Line 399... | ||
- | 399 | ||
- | 400 | #ifdef CONFIG_PCIEASPM |
|
- | 401 | struct pcie_link_state *link_state; /* ASPM link state. */ |
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Line 377... | Line 402... | ||
377 | 402 | #endif |
|
378 | 403 | ||
379 | pci_channel_state_t error_state; /* current connectivity state */ |
404 | pci_channel_state_t error_state; /* current connectivity state */ |
380 | struct device dev; /* Generic device interface */ |
405 | struct device dev; /* Generic device interface */ |
Line 385... | Line 410... | ||
385 | * Instead of touching interrupt line and base address registers |
410 | * Instead of touching interrupt line and base address registers |
386 | * directly, use the values stored here. They might be different! |
411 | * directly, use the values stored here. They might be different! |
387 | */ |
412 | */ |
388 | unsigned int irq; |
413 | unsigned int irq; |
389 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
414 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
390 | resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */ |
- | |
Line 391... | Line 415... | ||
391 | 415 | ||
392 | /* These fields are used by common fixups */ |
416 | /* These fields are used by common fixups */ |
393 | unsigned int transparent:1; /* Transparent PCI bridge */ |
417 | unsigned int transparent:1; /* Transparent PCI bridge */ |
394 | unsigned int multifunction:1;/* Part of multi-function device */ |
418 | unsigned int multifunction:1;/* Part of multi-function device */ |
395 | /* keep track of device state */ |
419 | /* keep track of device state */ |
396 | unsigned int is_added:1; |
420 | unsigned int is_added:1; |
397 | unsigned int is_busmaster:1; /* device is busmaster */ |
421 | unsigned int is_busmaster:1; /* device is busmaster */ |
398 | unsigned int no_msi:1; /* device may not use msi */ |
422 | unsigned int no_msi:1; /* device may not use msi */ |
399 | unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
423 | unsigned int block_cfg_access:1; /* config space access is blocked */ |
400 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
424 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
401 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
425 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
402 | unsigned int msi_enabled:1; |
426 | unsigned int msi_enabled:1; |
403 | unsigned int msix_enabled:1; |
427 | unsigned int msix_enabled:1; |
Line 409... | Line 433... | ||
409 | unsigned int state_saved:1; |
433 | unsigned int state_saved:1; |
410 | unsigned int is_physfn:1; |
434 | unsigned int is_physfn:1; |
411 | unsigned int is_virtfn:1; |
435 | unsigned int is_virtfn:1; |
412 | unsigned int reset_fn:1; |
436 | unsigned int reset_fn:1; |
413 | unsigned int is_hotplug_bridge:1; |
437 | unsigned int is_hotplug_bridge:1; |
- | 438 | unsigned int __aer_firmware_first_valid:1; |
|
- | 439 | unsigned int __aer_firmware_first:1; |
|
- | 440 | unsigned int broken_intx_masking:1; |
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- | 441 | unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ |
|
414 | // pci_dev_flags_t dev_flags; |
442 | // pci_dev_flags_t dev_flags; |
415 | // atomic_t enable_cnt; /* pci_enable_device has been called */ |
443 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
- | 444 | ||
- | 445 | ||
Line 416... | Line -... | ||
416 | - | ||
417 | // u32 saved_config_space[16]; /* config space saved at suspend time */ |
- | |
418 | // struct hlist_head saved_cap_space; |
- | |
419 | // struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
- | |
420 | // int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
- | |
421 | // struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
- | |
422 | // struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
446 | |
Line 423... | Line 447... | ||
423 | }; |
447 | }; |
424 | 448 | ||
425 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
449 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
Line 441... | Line 465... | ||
441 | struct list_head devices; /* list of devices on this bus */ |
465 | struct list_head devices; /* list of devices on this bus */ |
442 | struct pci_dev *self; /* bridge device as seen by parent */ |
466 | struct pci_dev *self; /* bridge device as seen by parent */ |
443 | struct list_head slots; /* list of slots on this bus */ |
467 | struct list_head slots; /* list of slots on this bus */ |
444 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
468 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
445 | struct list_head resources; /* address space routed to this bus */ |
469 | struct list_head resources; /* address space routed to this bus */ |
- | 470 | struct resource busn_res; /* bus numbers routed to this bus */ |
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Line 446... | Line 471... | ||
446 | 471 | ||
447 | struct pci_ops *ops; /* configuration access functions */ |
472 | struct pci_ops *ops; /* configuration access functions */ |
448 | void *sysdata; /* hook for sys-specific extension */ |
473 | void *sysdata; /* hook for sys-specific extension */ |
Line 449... | Line 474... | ||
449 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ |
474 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ |
450 | 475 | ||
451 | unsigned char number; /* bus number */ |
- | |
452 | unsigned char primary; /* number of primary bridge */ |
- | |
453 | unsigned char secondary; /* number of secondary bridge */ |
476 | unsigned char number; /* bus number */ |
454 | unsigned char subordinate; /* max number of subordinate buses */ |
477 | unsigned char primary; /* number of primary bridge */ |
Line 455... | Line 478... | ||
455 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
478 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
Line 569... | Line 592... | ||
569 | static inline bool pci_is_pcie(struct pci_dev *dev) |
592 | static inline bool pci_is_pcie(struct pci_dev *dev) |
570 | { |
593 | { |
571 | return !!pci_pcie_cap(dev); |
594 | return !!pci_pcie_cap(dev); |
572 | } |
595 | } |
Line -... | Line 596... | ||
- | 596 | ||
- | 597 | /** |
|
- | 598 | * pci_pcie_type - get the PCIe device/port type |
|
- | 599 | * @dev: PCI device |
|
- | 600 | */ |
|
- | 601 | static inline int pci_pcie_type(const struct pci_dev *dev) |
|
- | 602 | { |
|
- | 603 | return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4; |
|
- | 604 | } |
|
- | 605 | ||
573 | 606 | ||
574 | static inline int pci_iov_init(struct pci_dev *dev) |
607 | static inline int pci_iov_init(struct pci_dev *dev) |
575 | { |
608 | { |
576 | return -ENODEV; |
609 | return -ENODEV; |
577 | } |
610 | } |