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1 | /* |
1 | /* |
2 | * pci.h |
2 | * pci.h |
3 | * |
3 | * |
4 | * PCI defines and function prototypes |
4 | * PCI defines and function prototypes |
5 | * Copyright 1994, Drew Eckhardt |
5 | * Copyright 1994, Drew Eckhardt |
6 | * Copyright 1997--1999 Martin Mares |
6 | * Copyright 1997--1999 Martin Mares |
7 | * |
7 | * |
8 | * For more information, please consult the following manuals (look at |
8 | * For more information, please consult the following manuals (look at |
9 | * http://www.pcisig.com/ for how to get them): |
9 | * http://www.pcisig.com/ for how to get them): |
10 | * |
10 | * |
11 | * PCI BIOS Specification |
11 | * PCI BIOS Specification |
12 | * PCI Local Bus Specification |
12 | * PCI Local Bus Specification |
13 | * PCI to PCI Bridge Specification |
13 | * PCI to PCI Bridge Specification |
14 | * PCI System Design Guide |
14 | * PCI System Design Guide |
15 | */ |
15 | */ |
16 | 16 | ||
17 | #ifndef LINUX_PCI_H |
17 | #ifndef LINUX_PCI_H |
18 | #define LINUX_PCI_H |
18 | #define LINUX_PCI_H |
19 | 19 | ||
20 | #include |
20 | #include |
21 | #include |
21 | #include |
22 | #include |
22 | #include |
23 | #include |
23 | #include |
24 | 24 | ||
25 | 25 | ||
26 | #define PCI_CFG_SPACE_SIZE 256 |
26 | #define PCI_CFG_SPACE_SIZE 256 |
27 | #define PCI_CFG_SPACE_EXP_SIZE 4096 |
27 | #define PCI_CFG_SPACE_EXP_SIZE 4096 |
28 | 28 | ||
29 | 29 | ||
30 | #define PCI_ANY_ID (~0) |
30 | #define PCI_ANY_ID (~0) |
31 | 31 | ||
32 | 32 | ||
33 | #define PCI_CLASS_NOT_DEFINED 0x0000 |
33 | #define PCI_CLASS_NOT_DEFINED 0x0000 |
34 | #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 |
34 | #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 |
35 | 35 | ||
36 | #define PCI_BASE_CLASS_STORAGE 0x01 |
36 | #define PCI_BASE_CLASS_STORAGE 0x01 |
37 | #define PCI_CLASS_STORAGE_SCSI 0x0100 |
37 | #define PCI_CLASS_STORAGE_SCSI 0x0100 |
38 | #define PCI_CLASS_STORAGE_IDE 0x0101 |
38 | #define PCI_CLASS_STORAGE_IDE 0x0101 |
39 | #define PCI_CLASS_STORAGE_FLOPPY 0x0102 |
39 | #define PCI_CLASS_STORAGE_FLOPPY 0x0102 |
40 | #define PCI_CLASS_STORAGE_IPI 0x0103 |
40 | #define PCI_CLASS_STORAGE_IPI 0x0103 |
41 | #define PCI_CLASS_STORAGE_RAID 0x0104 |
41 | #define PCI_CLASS_STORAGE_RAID 0x0104 |
42 | #define PCI_CLASS_STORAGE_SATA 0x0106 |
42 | #define PCI_CLASS_STORAGE_SATA 0x0106 |
43 | #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 |
43 | #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 |
44 | #define PCI_CLASS_STORAGE_SAS 0x0107 |
44 | #define PCI_CLASS_STORAGE_SAS 0x0107 |
45 | #define PCI_CLASS_STORAGE_OTHER 0x0180 |
45 | #define PCI_CLASS_STORAGE_OTHER 0x0180 |
46 | 46 | ||
47 | #define PCI_BASE_CLASS_NETWORK 0x02 |
47 | #define PCI_BASE_CLASS_NETWORK 0x02 |
48 | #define PCI_CLASS_NETWORK_ETHERNET 0x0200 |
48 | #define PCI_CLASS_NETWORK_ETHERNET 0x0200 |
49 | #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 |
49 | #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 |
50 | #define PCI_CLASS_NETWORK_FDDI 0x0202 |
50 | #define PCI_CLASS_NETWORK_FDDI 0x0202 |
51 | #define PCI_CLASS_NETWORK_ATM 0x0203 |
51 | #define PCI_CLASS_NETWORK_ATM 0x0203 |
52 | #define PCI_CLASS_NETWORK_OTHER 0x0280 |
52 | #define PCI_CLASS_NETWORK_OTHER 0x0280 |
53 | 53 | ||
54 | #define PCI_BASE_CLASS_DISPLAY 0x03 |
54 | #define PCI_BASE_CLASS_DISPLAY 0x03 |
55 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
55 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
56 | #define PCI_CLASS_DISPLAY_XGA 0x0301 |
56 | #define PCI_CLASS_DISPLAY_XGA 0x0301 |
57 | #define PCI_CLASS_DISPLAY_3D 0x0302 |
57 | #define PCI_CLASS_DISPLAY_3D 0x0302 |
58 | #define PCI_CLASS_DISPLAY_OTHER 0x0380 |
58 | #define PCI_CLASS_DISPLAY_OTHER 0x0380 |
59 | 59 | ||
60 | #define PCI_BASE_CLASS_MULTIMEDIA 0x04 |
60 | #define PCI_BASE_CLASS_MULTIMEDIA 0x04 |
61 | #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 |
61 | #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 |
62 | #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 |
62 | #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 |
63 | #define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 |
63 | #define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 |
64 | #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 |
64 | #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 |
65 | 65 | ||
66 | #define PCI_BASE_CLASS_MEMORY 0x05 |
66 | #define PCI_BASE_CLASS_MEMORY 0x05 |
67 | #define PCI_CLASS_MEMORY_RAM 0x0500 |
67 | #define PCI_CLASS_MEMORY_RAM 0x0500 |
68 | #define PCI_CLASS_MEMORY_FLASH 0x0501 |
68 | #define PCI_CLASS_MEMORY_FLASH 0x0501 |
69 | #define PCI_CLASS_MEMORY_OTHER 0x0580 |
69 | #define PCI_CLASS_MEMORY_OTHER 0x0580 |
70 | 70 | ||
71 | #define PCI_BASE_CLASS_BRIDGE 0x06 |
71 | #define PCI_BASE_CLASS_BRIDGE 0x06 |
72 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
72 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
73 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
73 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
74 | #define PCI_CLASS_BRIDGE_EISA 0x0602 |
74 | #define PCI_CLASS_BRIDGE_EISA 0x0602 |
75 | #define PCI_CLASS_BRIDGE_MC 0x0603 |
75 | #define PCI_CLASS_BRIDGE_MC 0x0603 |
76 | #define PCI_CLASS_BRIDGE_PCI 0x0604 |
76 | #define PCI_CLASS_BRIDGE_PCI 0x0604 |
77 | #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 |
77 | #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 |
78 | #define PCI_CLASS_BRIDGE_NUBUS 0x0606 |
78 | #define PCI_CLASS_BRIDGE_NUBUS 0x0606 |
79 | #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 |
79 | #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 |
80 | #define PCI_CLASS_BRIDGE_RACEWAY 0x0608 |
80 | #define PCI_CLASS_BRIDGE_RACEWAY 0x0608 |
81 | #define PCI_CLASS_BRIDGE_OTHER 0x0680 |
81 | #define PCI_CLASS_BRIDGE_OTHER 0x0680 |
82 | 82 | ||
83 | #define PCI_BASE_CLASS_COMMUNICATION 0x07 |
83 | #define PCI_BASE_CLASS_COMMUNICATION 0x07 |
84 | #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 |
84 | #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 |
85 | #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 |
85 | #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 |
86 | #define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 |
86 | #define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 |
87 | #define PCI_CLASS_COMMUNICATION_MODEM 0x0703 |
87 | #define PCI_CLASS_COMMUNICATION_MODEM 0x0703 |
88 | #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 |
88 | #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 |
89 | 89 | ||
90 | #define PCI_BASE_CLASS_SYSTEM 0x08 |
90 | #define PCI_BASE_CLASS_SYSTEM 0x08 |
91 | #define PCI_CLASS_SYSTEM_PIC 0x0800 |
91 | #define PCI_CLASS_SYSTEM_PIC 0x0800 |
92 | #define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 |
92 | #define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 |
93 | #define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 |
93 | #define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 |
94 | #define PCI_CLASS_SYSTEM_DMA 0x0801 |
94 | #define PCI_CLASS_SYSTEM_DMA 0x0801 |
95 | #define PCI_CLASS_SYSTEM_TIMER 0x0802 |
95 | #define PCI_CLASS_SYSTEM_TIMER 0x0802 |
96 | #define PCI_CLASS_SYSTEM_RTC 0x0803 |
96 | #define PCI_CLASS_SYSTEM_RTC 0x0803 |
97 | #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 |
97 | #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 |
98 | #define PCI_CLASS_SYSTEM_SDHCI 0x0805 |
98 | #define PCI_CLASS_SYSTEM_SDHCI 0x0805 |
99 | #define PCI_CLASS_SYSTEM_OTHER 0x0880 |
99 | #define PCI_CLASS_SYSTEM_OTHER 0x0880 |
100 | 100 | ||
101 | #define PCI_BASE_CLASS_INPUT 0x09 |
101 | #define PCI_BASE_CLASS_INPUT 0x09 |
102 | #define PCI_CLASS_INPUT_KEYBOARD 0x0900 |
102 | #define PCI_CLASS_INPUT_KEYBOARD 0x0900 |
103 | #define PCI_CLASS_INPUT_PEN 0x0901 |
103 | #define PCI_CLASS_INPUT_PEN 0x0901 |
104 | #define PCI_CLASS_INPUT_MOUSE 0x0902 |
104 | #define PCI_CLASS_INPUT_MOUSE 0x0902 |
105 | #define PCI_CLASS_INPUT_SCANNER 0x0903 |
105 | #define PCI_CLASS_INPUT_SCANNER 0x0903 |
106 | #define PCI_CLASS_INPUT_GAMEPORT 0x0904 |
106 | #define PCI_CLASS_INPUT_GAMEPORT 0x0904 |
107 | #define PCI_CLASS_INPUT_OTHER 0x0980 |
107 | #define PCI_CLASS_INPUT_OTHER 0x0980 |
108 | 108 | ||
109 | #define PCI_BASE_CLASS_DOCKING 0x0a |
109 | #define PCI_BASE_CLASS_DOCKING 0x0a |
110 | #define PCI_CLASS_DOCKING_GENERIC 0x0a00 |
110 | #define PCI_CLASS_DOCKING_GENERIC 0x0a00 |
111 | #define PCI_CLASS_DOCKING_OTHER 0x0a80 |
111 | #define PCI_CLASS_DOCKING_OTHER 0x0a80 |
112 | 112 | ||
113 | #define PCI_BASE_CLASS_PROCESSOR 0x0b |
113 | #define PCI_BASE_CLASS_PROCESSOR 0x0b |
114 | #define PCI_CLASS_PROCESSOR_386 0x0b00 |
114 | #define PCI_CLASS_PROCESSOR_386 0x0b00 |
115 | #define PCI_CLASS_PROCESSOR_486 0x0b01 |
115 | #define PCI_CLASS_PROCESSOR_486 0x0b01 |
116 | #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 |
116 | #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 |
117 | #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 |
117 | #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 |
118 | #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
118 | #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
119 | #define PCI_CLASS_PROCESSOR_MIPS 0x0b30 |
119 | #define PCI_CLASS_PROCESSOR_MIPS 0x0b30 |
120 | #define PCI_CLASS_PROCESSOR_CO 0x0b40 |
120 | #define PCI_CLASS_PROCESSOR_CO 0x0b40 |
121 | 121 | ||
122 | #define PCI_BASE_CLASS_SERIAL 0x0c |
122 | #define PCI_BASE_CLASS_SERIAL 0x0c |
123 | #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 |
123 | #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 |
124 | #define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 |
124 | #define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 |
125 | #define PCI_CLASS_SERIAL_ACCESS 0x0c01 |
125 | #define PCI_CLASS_SERIAL_ACCESS 0x0c01 |
126 | #define PCI_CLASS_SERIAL_SSA 0x0c02 |
126 | #define PCI_CLASS_SERIAL_SSA 0x0c02 |
127 | #define PCI_CLASS_SERIAL_USB 0x0c03 |
127 | #define PCI_CLASS_SERIAL_USB 0x0c03 |
128 | #define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 |
128 | #define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 |
129 | #define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 |
129 | #define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 |
130 | #define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 |
130 | #define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 |
131 | #define PCI_CLASS_SERIAL_FIBER 0x0c04 |
131 | #define PCI_CLASS_SERIAL_FIBER 0x0c04 |
132 | #define PCI_CLASS_SERIAL_SMBUS 0x0c05 |
132 | #define PCI_CLASS_SERIAL_SMBUS 0x0c05 |
133 | 133 | ||
134 | #define PCI_BASE_CLASS_WIRELESS 0x0d |
134 | #define PCI_BASE_CLASS_WIRELESS 0x0d |
135 | #define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 |
135 | #define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 |
136 | #define PCI_CLASS_WIRELESS_WHCI 0x0d1010 |
136 | #define PCI_CLASS_WIRELESS_WHCI 0x0d1010 |
137 | 137 | ||
138 | #define PCI_BASE_CLASS_INTELLIGENT 0x0e |
138 | #define PCI_BASE_CLASS_INTELLIGENT 0x0e |
139 | #define PCI_CLASS_INTELLIGENT_I2O 0x0e00 |
139 | #define PCI_CLASS_INTELLIGENT_I2O 0x0e00 |
140 | 140 | ||
141 | #define PCI_BASE_CLASS_SATELLITE 0x0f |
141 | #define PCI_BASE_CLASS_SATELLITE 0x0f |
142 | #define PCI_CLASS_SATELLITE_TV 0x0f00 |
142 | #define PCI_CLASS_SATELLITE_TV 0x0f00 |
143 | #define PCI_CLASS_SATELLITE_AUDIO 0x0f01 |
143 | #define PCI_CLASS_SATELLITE_AUDIO 0x0f01 |
144 | #define PCI_CLASS_SATELLITE_VOICE 0x0f03 |
144 | #define PCI_CLASS_SATELLITE_VOICE 0x0f03 |
145 | #define PCI_CLASS_SATELLITE_DATA 0x0f04 |
145 | #define PCI_CLASS_SATELLITE_DATA 0x0f04 |
146 | 146 | ||
147 | #define PCI_BASE_CLASS_CRYPT 0x10 |
147 | #define PCI_BASE_CLASS_CRYPT 0x10 |
148 | #define PCI_CLASS_CRYPT_NETWORK 0x1000 |
148 | #define PCI_CLASS_CRYPT_NETWORK 0x1000 |
149 | #define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 |
149 | #define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 |
150 | #define PCI_CLASS_CRYPT_OTHER 0x1080 |
150 | #define PCI_CLASS_CRYPT_OTHER 0x1080 |
151 | 151 | ||
152 | #define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 |
152 | #define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 |
153 | #define PCI_CLASS_SP_DPIO 0x1100 |
153 | #define PCI_CLASS_SP_DPIO 0x1100 |
154 | #define PCI_CLASS_SP_OTHER 0x1180 |
154 | #define PCI_CLASS_SP_OTHER 0x1180 |
155 | 155 | ||
156 | #define PCI_CLASS_OTHERS 0xff |
156 | #define PCI_CLASS_OTHERS 0xff |
157 | 157 | ||
158 | 158 | ||
159 | 159 | ||
160 | 160 | ||
161 | 161 | ||
162 | #define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) |
162 | #define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) |
163 | #define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) |
163 | #define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) |
164 | 164 | ||
165 | #define PCI_MAP_IS64BITMEM(b) \ |
165 | #define PCI_MAP_IS64BITMEM(b) \ |
166 | (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) |
166 | (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) |
167 | 167 | ||
168 | #define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) |
168 | #define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) |
169 | #define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) |
169 | #define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) |
170 | #define PCIGETMEMORY64(b) \ |
170 | #define PCIGETMEMORY64(b) \ |
171 | (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) |
171 | (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) |
172 | 172 | ||
173 | #define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc |
173 | #define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc |
174 | 174 | ||
175 | #define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) |
175 | #define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) |
176 | 176 | ||
177 | #define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 |
177 | #define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 |
178 | #define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 |
178 | #define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 |
179 | 179 | ||
180 | #define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) |
180 | #define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) |
181 | 181 | ||
182 | 182 | ||
183 | #ifndef PCI_DOM_MASK |
183 | #ifndef PCI_DOM_MASK |
184 | # define PCI_DOM_MASK 0x0ffu |
184 | # define PCI_DOM_MASK 0x0ffu |
185 | #endif |
185 | #endif |
186 | #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) |
186 | #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) |
187 | 187 | ||
188 | #define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ |
188 | #define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ |
189 | (((d) & 0x00001fu) << 11) | \ |
189 | (((d) & 0x00001fu) << 11) | \ |
190 | (((f) & 0x000007u) << 8)) |
190 | (((f) & 0x000007u) << 8)) |
191 | 191 | ||
192 | #define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) |
192 | #define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) |
193 | #define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) |
193 | #define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) |
194 | #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) |
194 | #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) |
195 | #define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
195 | #define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
196 | 196 | ||
197 | /* |
197 | /* |
198 | * The PCI interface treats multi-function devices as independent |
198 | * The PCI interface treats multi-function devices as independent |
199 | * devices. The slot/function address of each device is encoded |
199 | * devices. The slot/function address of each device is encoded |
200 | * in a single byte as follows: |
200 | * in a single byte as follows: |
201 | * |
201 | * |
202 | * 7:3 = slot |
202 | * 7:3 = slot |
203 | * 2:0 = function |
203 | * 2:0 = function |
204 | */ |
204 | */ |
205 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
205 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
206 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
206 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
207 | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
207 | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
208 | 208 | ||
209 | 209 | ||
210 | 210 | ||
211 | typedef unsigned int PCITAG; |
211 | typedef unsigned int PCITAG; |
212 | 212 | ||
213 | extern inline PCITAG |
213 | extern inline PCITAG |
214 | pciTag(int busnum, int devnum, int funcnum) |
214 | pciTag(int busnum, int devnum, int funcnum) |
215 | { |
215 | { |
216 | return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
216 | return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
217 | } |
217 | } |
218 | 218 | ||
219 | /* pci_slot represents a physical slot */ |
219 | /* pci_slot represents a physical slot */ |
220 | struct pci_slot { |
220 | struct pci_slot { |
221 | struct pci_bus *bus; /* The bus this slot is on */ |
221 | struct pci_bus *bus; /* The bus this slot is on */ |
222 | struct list_head list; /* node in list of slots on this bus */ |
222 | struct list_head list; /* node in list of slots on this bus */ |
223 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ |
223 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ |
224 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ |
224 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ |
225 | }; |
225 | }; |
226 | 226 | ||
227 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
227 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
228 | enum pci_mmap_state { |
228 | enum pci_mmap_state { |
229 | pci_mmap_io, |
229 | pci_mmap_io, |
230 | pci_mmap_mem |
230 | pci_mmap_mem |
231 | }; |
231 | }; |
232 | 232 | ||
233 | /* This defines the direction arg to the DMA mapping routines. */ |
233 | /* This defines the direction arg to the DMA mapping routines. */ |
234 | #define PCI_DMA_BIDIRECTIONAL 0 |
234 | #define PCI_DMA_BIDIRECTIONAL 0 |
235 | #define PCI_DMA_TODEVICE 1 |
235 | #define PCI_DMA_TODEVICE 1 |
236 | #define PCI_DMA_FROMDEVICE 2 |
236 | #define PCI_DMA_FROMDEVICE 2 |
237 | #define PCI_DMA_NONE 3 |
237 | #define PCI_DMA_NONE 3 |
238 | 238 | ||
239 | /* |
239 | /* |
240 | * For PCI devices, the region numbers are assigned this way: |
240 | * For PCI devices, the region numbers are assigned this way: |
241 | */ |
241 | */ |
242 | enum { |
242 | enum { |
243 | /* #0-5: standard PCI resources */ |
243 | /* #0-5: standard PCI resources */ |
244 | PCI_STD_RESOURCES, |
244 | PCI_STD_RESOURCES, |
245 | PCI_STD_RESOURCE_END = 5, |
245 | PCI_STD_RESOURCE_END = 5, |
246 | 246 | ||
247 | /* #6: expansion ROM resource */ |
247 | /* #6: expansion ROM resource */ |
248 | PCI_ROM_RESOURCE, |
248 | PCI_ROM_RESOURCE, |
249 | 249 | ||
250 | /* device specific resources */ |
250 | /* device specific resources */ |
251 | #ifdef CONFIG_PCI_IOV |
251 | #ifdef CONFIG_PCI_IOV |
252 | PCI_IOV_RESOURCES, |
252 | PCI_IOV_RESOURCES, |
253 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, |
253 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, |
254 | #endif |
254 | #endif |
255 | 255 | ||
256 | /* resources assigned to buses behind the bridge */ |
256 | /* resources assigned to buses behind the bridge */ |
257 | #define PCI_BRIDGE_RESOURCE_NUM 4 |
257 | #define PCI_BRIDGE_RESOURCE_NUM 4 |
258 | 258 | ||
259 | PCI_BRIDGE_RESOURCES, |
259 | PCI_BRIDGE_RESOURCES, |
260 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + |
260 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + |
261 | PCI_BRIDGE_RESOURCE_NUM - 1, |
261 | PCI_BRIDGE_RESOURCE_NUM - 1, |
262 | 262 | ||
263 | /* total resources associated with a PCI device */ |
263 | /* total resources associated with a PCI device */ |
264 | PCI_NUM_RESOURCES, |
264 | PCI_NUM_RESOURCES, |
265 | 265 | ||
266 | /* preserve this for compatibility */ |
266 | /* preserve this for compatibility */ |
267 | DEVICE_COUNT_RESOURCE |
267 | DEVICE_COUNT_RESOURCE |
268 | }; |
268 | }; |
269 | 269 | ||
270 | typedef int __bitwise pci_power_t; |
270 | typedef int __bitwise pci_power_t; |
271 | 271 | ||
272 | #define PCI_D0 ((pci_power_t __force) 0) |
272 | #define PCI_D0 ((pci_power_t __force) 0) |
273 | #define PCI_D1 ((pci_power_t __force) 1) |
273 | #define PCI_D1 ((pci_power_t __force) 1) |
274 | #define PCI_D2 ((pci_power_t __force) 2) |
274 | #define PCI_D2 ((pci_power_t __force) 2) |
275 | #define PCI_D3hot ((pci_power_t __force) 3) |
275 | #define PCI_D3hot ((pci_power_t __force) 3) |
276 | #define PCI_D3cold ((pci_power_t __force) 4) |
276 | #define PCI_D3cold ((pci_power_t __force) 4) |
277 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
277 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
278 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
278 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
279 | /** The pci_channel state describes connectivity between the CPU and |
279 | /** The pci_channel state describes connectivity between the CPU and |
280 | * the pci device. If some PCI bus between here and the pci device |
280 | * the pci device. If some PCI bus between here and the pci device |
281 | * has crashed or locked up, this info is reflected here. |
281 | * has crashed or locked up, this info is reflected here. |
282 | */ |
282 | */ |
283 | typedef unsigned int __bitwise pci_channel_state_t; |
283 | typedef unsigned int __bitwise pci_channel_state_t; |
284 | 284 | ||
285 | enum pci_channel_state { |
285 | enum pci_channel_state { |
286 | /* I/O channel is in normal state */ |
286 | /* I/O channel is in normal state */ |
287 | pci_channel_io_normal = (__force pci_channel_state_t) 1, |
287 | pci_channel_io_normal = (__force pci_channel_state_t) 1, |
288 | 288 | ||
289 | /* I/O to channel is blocked */ |
289 | /* I/O to channel is blocked */ |
290 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, |
290 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, |
291 | 291 | ||
292 | /* PCI card is dead */ |
292 | /* PCI card is dead */ |
293 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, |
293 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, |
294 | }; |
294 | }; |
295 | typedef unsigned short __bitwise pci_bus_flags_t; |
295 | typedef unsigned short __bitwise pci_bus_flags_t; |
296 | enum pci_bus_flags { |
296 | enum pci_bus_flags { |
297 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
297 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
298 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, |
298 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, |
299 | }; |
299 | }; |
300 | 300 | ||
301 | /* Based on the PCI Hotplug Spec, but some values are made up by us */ |
301 | /* Based on the PCI Hotplug Spec, but some values are made up by us */ |
302 | enum pci_bus_speed { |
302 | enum pci_bus_speed { |
303 | PCI_SPEED_33MHz = 0x00, |
303 | PCI_SPEED_33MHz = 0x00, |
304 | PCI_SPEED_66MHz = 0x01, |
304 | PCI_SPEED_66MHz = 0x01, |
305 | PCI_SPEED_66MHz_PCIX = 0x02, |
305 | PCI_SPEED_66MHz_PCIX = 0x02, |
306 | PCI_SPEED_100MHz_PCIX = 0x03, |
306 | PCI_SPEED_100MHz_PCIX = 0x03, |
307 | PCI_SPEED_133MHz_PCIX = 0x04, |
307 | PCI_SPEED_133MHz_PCIX = 0x04, |
308 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, |
308 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, |
309 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, |
309 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, |
310 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, |
310 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, |
311 | PCI_SPEED_66MHz_PCIX_266 = 0x09, |
311 | PCI_SPEED_66MHz_PCIX_266 = 0x09, |
312 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, |
312 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, |
313 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, |
313 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, |
314 | AGP_UNKNOWN = 0x0c, |
314 | AGP_UNKNOWN = 0x0c, |
315 | AGP_1X = 0x0d, |
315 | AGP_1X = 0x0d, |
316 | AGP_2X = 0x0e, |
316 | AGP_2X = 0x0e, |
317 | AGP_4X = 0x0f, |
317 | AGP_4X = 0x0f, |
318 | AGP_8X = 0x10, |
318 | AGP_8X = 0x10, |
319 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
319 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
320 | PCI_SPEED_100MHz_PCIX_533 = 0x12, |
320 | PCI_SPEED_100MHz_PCIX_533 = 0x12, |
321 | PCI_SPEED_133MHz_PCIX_533 = 0x13, |
321 | PCI_SPEED_133MHz_PCIX_533 = 0x13, |
322 | PCIE_SPEED_2_5GT = 0x14, |
322 | PCIE_SPEED_2_5GT = 0x14, |
323 | PCIE_SPEED_5_0GT = 0x15, |
323 | PCIE_SPEED_5_0GT = 0x15, |
324 | PCIE_SPEED_8_0GT = 0x16, |
324 | PCIE_SPEED_8_0GT = 0x16, |
325 | PCI_SPEED_UNKNOWN = 0xff, |
325 | PCI_SPEED_UNKNOWN = 0xff, |
326 | }; |
326 | }; |
327 | 327 | ||
328 | /* |
328 | /* |
329 | * The pci_dev structure is used to describe PCI devices. |
329 | * The pci_dev structure is used to describe PCI devices. |
330 | */ |
330 | */ |
331 | struct pci_dev { |
331 | struct pci_dev { |
332 | struct list_head bus_list; /* node in per-bus list */ |
332 | struct list_head bus_list; /* node in per-bus list */ |
333 | struct pci_bus *bus; /* bus this device is on */ |
333 | struct pci_bus *bus; /* bus this device is on */ |
334 | struct pci_bus *subordinate; /* bus this device bridges to */ |
334 | struct pci_bus *subordinate; /* bus this device bridges to */ |
335 | 335 | ||
336 | void *sysdata; /* hook for sys-specific extension */ |
336 | void *sysdata; /* hook for sys-specific extension */ |
337 | // struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ |
337 | // struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ |
338 | struct pci_slot *slot; /* Physical slot this device is in */ |
338 | struct pci_slot *slot; /* Physical slot this device is in */ |
339 | u32_t busnr; |
339 | u32_t busnr; |
340 | unsigned int devfn; /* encoded device & function index */ |
340 | unsigned int devfn; /* encoded device & function index */ |
341 | unsigned short vendor; |
341 | unsigned short vendor; |
342 | unsigned short device; |
342 | unsigned short device; |
343 | unsigned short subsystem_vendor; |
343 | unsigned short subsystem_vendor; |
344 | unsigned short subsystem_device; |
344 | unsigned short subsystem_device; |
345 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ |
345 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ |
346 | u8 revision; /* PCI revision, low byte of class word */ |
346 | u8 revision; /* PCI revision, low byte of class word */ |
347 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
347 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
348 | u8 pcie_cap; /* PCI-E capability offset */ |
348 | u8 pcie_cap; /* PCI-E capability offset */ |
349 | u8 pcie_type; /* PCI-E device/port type */ |
349 | u8 pcie_type; /* PCI-E device/port type */ |
350 | u8 rom_base_reg; /* which config register controls the ROM */ |
350 | u8 rom_base_reg; /* which config register controls the ROM */ |
351 | u8 pin; /* which interrupt pin this device uses */ |
351 | u8 pin; /* which interrupt pin this device uses */ |
352 | 352 | ||
353 | // struct pci_driver *driver; /* which driver has allocated this device */ |
353 | // struct pci_driver *driver; /* which driver has allocated this device */ |
354 | uint64_t dma_mask; /* Mask of the bits of bus address this |
354 | uint64_t dma_mask; /* Mask of the bits of bus address this |
355 | device implements. Normally this is |
355 | device implements. Normally this is |
356 | 0xffffffff. You only need to change |
356 | 0xffffffff. You only need to change |
357 | this if your device has broken DMA |
357 | this if your device has broken DMA |
358 | or supports 64-bit transfers. */ |
358 | or supports 64-bit transfers. */ |
359 | 359 | ||
360 | // struct device_dma_parameters dma_parms; |
360 | // struct device_dma_parameters dma_parms; |
361 | 361 | ||
362 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
362 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
363 | this is D0-D3, D0 being fully functional, |
363 | this is D0-D3, D0 being fully functional, |
364 | and D3 being off. */ |
364 | and D3 being off. */ |
365 | int pm_cap; /* PM capability offset in the |
365 | int pm_cap; /* PM capability offset in the |
366 | configuration space */ |
366 | configuration space */ |
367 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
367 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
368 | can be generated */ |
368 | can be generated */ |
369 | unsigned int pme_interrupt:1; |
369 | unsigned int pme_interrupt:1; |
370 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
370 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
371 | unsigned int d2_support:1; /* Low power state D2 is supported */ |
371 | unsigned int d2_support:1; /* Low power state D2 is supported */ |
372 | unsigned int no_d1d2:1; /* Only allow D0 and D3 */ |
372 | unsigned int no_d1d2:1; /* Only allow D0 and D3 */ |
373 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
373 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
374 | decoding during bar sizing */ |
374 | decoding during bar sizing */ |
375 | unsigned int wakeup_prepared:1; |
375 | unsigned int wakeup_prepared:1; |
376 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
376 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
377 | 377 | ||
378 | 378 | ||
379 | pci_channel_state_t error_state; /* current connectivity state */ |
379 | pci_channel_state_t error_state; /* current connectivity state */ |
380 | struct device dev; /* Generic device interface */ |
380 | struct device dev; /* Generic device interface */ |
381 | struct acpi_device *acpi_dev; |
381 | struct acpi_device *acpi_dev; |
382 | int cfg_size; /* Size of configuration space */ |
382 | int cfg_size; /* Size of configuration space */ |
383 | 383 | ||
384 | /* |
384 | /* |
385 | * Instead of touching interrupt line and base address registers |
385 | * Instead of touching interrupt line and base address registers |
386 | * directly, use the values stored here. They might be different! |
386 | * directly, use the values stored here. They might be different! |
387 | */ |
387 | */ |
388 | unsigned int irq; |
388 | unsigned int irq; |
389 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
389 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
390 | resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */ |
390 | resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */ |
391 | 391 | ||
392 | /* These fields are used by common fixups */ |
392 | /* These fields are used by common fixups */ |
393 | unsigned int transparent:1; /* Transparent PCI bridge */ |
393 | unsigned int transparent:1; /* Transparent PCI bridge */ |
394 | unsigned int multifunction:1;/* Part of multi-function device */ |
394 | unsigned int multifunction:1;/* Part of multi-function device */ |
395 | /* keep track of device state */ |
395 | /* keep track of device state */ |
396 | unsigned int is_added:1; |
396 | unsigned int is_added:1; |
397 | unsigned int is_busmaster:1; /* device is busmaster */ |
397 | unsigned int is_busmaster:1; /* device is busmaster */ |
398 | unsigned int no_msi:1; /* device may not use msi */ |
398 | unsigned int no_msi:1; /* device may not use msi */ |
399 | unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
399 | unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
400 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
400 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
401 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
401 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
402 | unsigned int msi_enabled:1; |
402 | unsigned int msi_enabled:1; |
403 | unsigned int msix_enabled:1; |
403 | unsigned int msix_enabled:1; |
404 | unsigned int ari_enabled:1; /* ARI forwarding */ |
404 | unsigned int ari_enabled:1; /* ARI forwarding */ |
405 | unsigned int is_managed:1; |
405 | unsigned int is_managed:1; |
406 | unsigned int is_pcie:1; /* Obsolete. Will be removed. |
406 | unsigned int is_pcie:1; /* Obsolete. Will be removed. |
407 | Use pci_is_pcie() instead */ |
407 | Use pci_is_pcie() instead */ |
408 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
408 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
409 | unsigned int state_saved:1; |
409 | unsigned int state_saved:1; |
410 | unsigned int is_physfn:1; |
410 | unsigned int is_physfn:1; |
411 | unsigned int is_virtfn:1; |
411 | unsigned int is_virtfn:1; |
412 | unsigned int reset_fn:1; |
412 | unsigned int reset_fn:1; |
413 | unsigned int is_hotplug_bridge:1; |
413 | unsigned int is_hotplug_bridge:1; |
414 | // pci_dev_flags_t dev_flags; |
414 | // pci_dev_flags_t dev_flags; |
415 | // atomic_t enable_cnt; /* pci_enable_device has been called */ |
415 | // atomic_t enable_cnt; /* pci_enable_device has been called */ |
416 | 416 | ||
417 | // u32 saved_config_space[16]; /* config space saved at suspend time */ |
417 | // u32 saved_config_space[16]; /* config space saved at suspend time */ |
418 | // struct hlist_head saved_cap_space; |
418 | // struct hlist_head saved_cap_space; |
419 | // struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
419 | // struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
420 | // int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
420 | // int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
421 | // struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
421 | // struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
422 | // struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
422 | // struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
423 | }; |
423 | }; |
424 | 424 | ||
425 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
425 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
426 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
426 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
427 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
427 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
428 | #define pci_resource_len(dev,bar) \ |
428 | #define pci_resource_len(dev,bar) \ |
429 | ((pci_resource_start((dev), (bar)) == 0 && \ |
429 | ((pci_resource_start((dev), (bar)) == 0 && \ |
430 | pci_resource_end((dev), (bar)) == \ |
430 | pci_resource_end((dev), (bar)) == \ |
431 | pci_resource_start((dev), (bar))) ? 0 : \ |
431 | pci_resource_start((dev), (bar))) ? 0 : \ |
432 | \ |
432 | \ |
433 | (pci_resource_end((dev), (bar)) - \ |
433 | (pci_resource_end((dev), (bar)) - \ |
434 | pci_resource_start((dev), (bar)) + 1)) |
434 | pci_resource_start((dev), (bar)) + 1)) |
435 | 435 | ||
436 | 436 | ||
437 | struct pci_bus { |
437 | struct pci_bus { |
438 | struct list_head node; /* node in list of buses */ |
438 | struct list_head node; /* node in list of buses */ |
439 | struct pci_bus *parent; /* parent bus this bridge is on */ |
439 | struct pci_bus *parent; /* parent bus this bridge is on */ |
440 | struct list_head children; /* list of child buses */ |
440 | struct list_head children; /* list of child buses */ |
441 | struct list_head devices; /* list of devices on this bus */ |
441 | struct list_head devices; /* list of devices on this bus */ |
442 | struct pci_dev *self; /* bridge device as seen by parent */ |
442 | struct pci_dev *self; /* bridge device as seen by parent */ |
443 | struct list_head slots; /* list of slots on this bus */ |
443 | struct list_head slots; /* list of slots on this bus */ |
444 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
444 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
445 | struct list_head resources; /* address space routed to this bus */ |
445 | struct list_head resources; /* address space routed to this bus */ |
446 | 446 | ||
447 | struct pci_ops *ops; /* configuration access functions */ |
447 | struct pci_ops *ops; /* configuration access functions */ |
448 | void *sysdata; /* hook for sys-specific extension */ |
448 | void *sysdata; /* hook for sys-specific extension */ |
449 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ |
449 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ |
450 | 450 | ||
451 | unsigned char number; /* bus number */ |
451 | unsigned char number; /* bus number */ |
452 | unsigned char primary; /* number of primary bridge */ |
452 | unsigned char primary; /* number of primary bridge */ |
453 | unsigned char secondary; /* number of secondary bridge */ |
453 | unsigned char secondary; /* number of secondary bridge */ |
454 | unsigned char subordinate; /* max number of subordinate buses */ |
454 | unsigned char subordinate; /* max number of subordinate buses */ |
455 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
455 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
456 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ |
456 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ |
457 | 457 | ||
458 | char name[48]; |
458 | char name[48]; |
459 | 459 | ||
460 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ |
460 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ |
461 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
461 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
462 | struct device *bridge; |
462 | struct device *bridge; |
463 | struct device dev; |
463 | struct device dev; |
464 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
464 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
465 | struct bin_attribute *legacy_mem; /* legacy mem */ |
465 | struct bin_attribute *legacy_mem; /* legacy mem */ |
466 | unsigned int is_added:1; |
466 | unsigned int is_added:1; |
467 | }; |
467 | }; |
468 | 468 | ||
469 | 469 | ||
470 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
470 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
471 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
471 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
472 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
472 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
473 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
473 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
474 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) |
474 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) |
475 | 475 | ||
476 | 476 | ||
477 | /* Low-level architecture-dependent routines */ |
477 | /* Low-level architecture-dependent routines */ |
478 | 478 | ||
479 | struct pci_sysdata { |
479 | struct pci_sysdata { |
480 | int domain; /* PCI domain */ |
480 | int domain; /* PCI domain */ |
481 | int node; /* NUMA node */ |
481 | int node; /* NUMA node */ |
482 | }; |
482 | }; |
483 | 483 | ||
484 | 484 | ||
485 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
485 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
486 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
486 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
487 | 487 | ||
488 | /* |
488 | /* |
489 | * Returns true if the pci bus is root (behind host-pci bridge), |
489 | * Returns true if the pci bus is root (behind host-pci bridge), |
490 | * false otherwise |
490 | * false otherwise |
491 | */ |
491 | */ |
492 | static inline bool pci_is_root_bus(struct pci_bus *pbus) |
492 | static inline bool pci_is_root_bus(struct pci_bus *pbus) |
493 | { |
493 | { |
494 | return !(pbus->parent); |
494 | return !(pbus->parent); |
495 | } |
495 | } |
496 | 496 | ||
497 | struct pci_bus * |
497 | struct pci_bus * |
498 | pci_find_next_bus(const struct pci_bus *from); |
498 | pci_find_next_bus(const struct pci_bus *from); |
499 | 499 | ||
500 | 500 | ||
501 | /* |
501 | /* |
502 | * Error values that may be returned by PCI functions. |
502 | * Error values that may be returned by PCI functions. |
503 | */ |
503 | */ |
504 | #define PCIBIOS_SUCCESSFUL 0x00 |
504 | #define PCIBIOS_SUCCESSFUL 0x00 |
505 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 |
505 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 |
506 | #define PCIBIOS_BAD_VENDOR_ID 0x83 |
506 | #define PCIBIOS_BAD_VENDOR_ID 0x83 |
507 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 |
507 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 |
508 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 |
508 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 |
509 | #define PCIBIOS_SET_FAILED 0x88 |
509 | #define PCIBIOS_SET_FAILED 0x88 |
510 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 |
510 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 |
511 | 511 | ||
512 | /* Low-level architecture-dependent routines */ |
512 | /* Low-level architecture-dependent routines */ |
513 | 513 | ||
514 | struct pci_ops { |
514 | struct pci_ops { |
515 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
515 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
516 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); |
516 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); |
517 | }; |
517 | }; |
518 | 518 | ||
519 | 519 | ||
520 | enum pci_bar_type { |
520 | enum pci_bar_type { |
521 | pci_bar_unknown, /* Standard PCI BAR probe */ |
521 | pci_bar_unknown, /* Standard PCI BAR probe */ |
522 | pci_bar_io, /* An io port BAR */ |
522 | pci_bar_io, /* An io port BAR */ |
523 | pci_bar_mem32, /* A 32-bit memory BAR */ |
523 | pci_bar_mem32, /* A 32-bit memory BAR */ |
524 | pci_bar_mem64, /* A 64-bit memory BAR */ |
524 | pci_bar_mem64, /* A 64-bit memory BAR */ |
525 | }; |
525 | }; |
526 | 526 | ||
527 | /* |
527 | /* |
528 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), |
528 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), |
529 | * a PCI domain is defined to be a set of PCI busses which share |
529 | * a PCI domain is defined to be a set of PCI busses which share |
530 | * configuration space. |
530 | * configuration space. |
531 | */ |
531 | */ |
532 | #ifdef CONFIG_PCI_DOMAINS |
532 | #ifdef CONFIG_PCI_DOMAINS |
533 | extern int pci_domains_supported; |
533 | extern int pci_domains_supported; |
534 | #else |
534 | #else |
535 | enum { pci_domains_supported = 0 }; |
535 | enum { pci_domains_supported = 0 }; |
536 | static inline int pci_domain_nr(struct pci_bus *bus) |
536 | static inline int pci_domain_nr(struct pci_bus *bus) |
537 | { |
537 | { |
538 | return 0; |
538 | return 0; |
539 | } |
539 | } |
540 | 540 | ||
541 | static inline int pci_proc_domain(struct pci_bus *bus) |
541 | static inline int pci_proc_domain(struct pci_bus *bus) |
542 | { |
542 | { |
543 | return 0; |
543 | return 0; |
544 | } |
544 | } |
545 | #endif /* CONFIG_PCI_DOMAINS */ |
545 | #endif /* CONFIG_PCI_DOMAINS */ |
546 | 546 | ||
547 | /** |
547 | /** |
548 | * pci_pcie_cap - get the saved PCIe capability offset |
548 | * pci_pcie_cap - get the saved PCIe capability offset |
549 | * @dev: PCI device |
549 | * @dev: PCI device |
550 | * |
550 | * |
551 | * PCIe capability offset is calculated at PCI device initialization |
551 | * PCIe capability offset is calculated at PCI device initialization |
552 | * time and saved in the data structure. This function returns saved |
552 | * time and saved in the data structure. This function returns saved |
553 | * PCIe capability offset. Using this instead of pci_find_capability() |
553 | * PCIe capability offset. Using this instead of pci_find_capability() |
554 | * reduces unnecessary search in the PCI configuration space. If you |
554 | * reduces unnecessary search in the PCI configuration space. If you |
555 | * need to calculate PCIe capability offset from raw device for some |
555 | * need to calculate PCIe capability offset from raw device for some |
556 | * reasons, please use pci_find_capability() instead. |
556 | * reasons, please use pci_find_capability() instead. |
557 | */ |
557 | */ |
558 | static inline int pci_pcie_cap(struct pci_dev *dev) |
558 | static inline int pci_pcie_cap(struct pci_dev *dev) |
559 | { |
559 | { |
560 | return dev->pcie_cap; |
560 | return dev->pcie_cap; |
561 | } |
561 | } |
562 | 562 | ||
563 | /** |
563 | /** |
564 | * pci_is_pcie - check if the PCI device is PCI Express capable |
564 | * pci_is_pcie - check if the PCI device is PCI Express capable |
565 | * @dev: PCI device |
565 | * @dev: PCI device |
566 | * |
566 | * |
567 | * Retrun true if the PCI device is PCI Express capable, false otherwise. |
567 | * Retrun true if the PCI device is PCI Express capable, false otherwise. |
568 | */ |
568 | */ |
569 | static inline bool pci_is_pcie(struct pci_dev *dev) |
569 | static inline bool pci_is_pcie(struct pci_dev *dev) |
570 | { |
570 | { |
571 | return !!pci_pcie_cap(dev); |
571 | return !!pci_pcie_cap(dev); |
572 | } |
572 | } |
573 | 573 | ||
574 | static inline int pci_iov_init(struct pci_dev *dev) |
574 | static inline int pci_iov_init(struct pci_dev *dev) |
575 | { |
575 | { |
576 | return -ENODEV; |
576 | return -ENODEV; |
577 | } |
577 | } |
578 | static inline void pci_iov_release(struct pci_dev *dev) |
578 | static inline void pci_iov_release(struct pci_dev *dev) |
579 | 579 | ||
580 | {} |
580 | {} |
581 | 581 | ||
582 | static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno, |
582 | static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno, |
583 | enum pci_bar_type *type) |
583 | enum pci_bar_type *type) |
584 | { |
584 | { |
585 | return 0; |
585 | return 0; |
586 | } |
586 | } |
587 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
587 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
588 | { |
588 | { |
589 | } |
589 | } |
590 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
590 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
591 | { |
591 | { |
592 | return 0; |
592 | return 0; |
593 | } |
593 | } |
594 | 594 | ||
595 | static inline int pci_enable_ats(struct pci_dev *dev, int ps) |
595 | static inline int pci_enable_ats(struct pci_dev *dev, int ps) |
596 | { |
596 | { |
597 | return -ENODEV; |
597 | return -ENODEV; |
598 | } |
598 | } |
599 | static inline void pci_disable_ats(struct pci_dev *dev) |
599 | static inline void pci_disable_ats(struct pci_dev *dev) |
600 | { |
600 | { |
601 | } |
601 | } |
602 | static inline int pci_ats_queue_depth(struct pci_dev *dev) |
602 | static inline int pci_ats_queue_depth(struct pci_dev *dev) |
603 | { |
603 | { |
604 | return -ENODEV; |
604 | return -ENODEV; |
605 | } |
605 | } |
606 | static inline int pci_ats_enabled(struct pci_dev *dev) |
606 | static inline int pci_ats_enabled(struct pci_dev *dev) |
607 | { |
607 | { |
608 | return 0; |
608 | return 0; |
609 | } |
609 | } |
610 | 610 | ||
611 | int pci_setup_device(struct pci_dev *dev); |
611 | int pci_setup_device(struct pci_dev *dev); |
612 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
612 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
613 | struct resource *res, unsigned int reg); |
613 | struct resource *res, unsigned int reg); |
614 | int pci_resource_bar(struct pci_dev *dev, int resno, |
614 | int pci_resource_bar(struct pci_dev *dev, int resno, |
615 | enum pci_bar_type *type); |
615 | enum pci_bar_type *type); |
616 | int pci_bus_add_child(struct pci_bus *bus); |
616 | int pci_bus_add_child(struct pci_bus *bus); |
617 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
617 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
618 | 618 | ||
619 | 619 | ||
620 | typedef struct |
620 | typedef struct |
621 | { |
621 | { |
622 | struct list_head link; |
622 | struct list_head link; |
623 | struct pci_dev pci_dev; |
623 | struct pci_dev pci_dev; |
624 | }pci_dev_t; |
624 | }pci_dev_t; |
625 | 625 | ||
626 | int enum_pci_devices(void); |
626 | int enum_pci_devices(void); |
627 | 627 | ||
628 | struct pci_device_id* |
628 | const struct pci_device_id* |
629 | find_pci_device(pci_dev_t* pdev, struct pci_device_id *idlist); |
629 | find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist); |
630 | 630 | ||
631 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) |
631 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) |
632 | 632 | ||
633 | int pci_set_dma_mask(struct pci_dev *dev, u64 mask); |
633 | int pci_set_dma_mask(struct pci_dev *dev, u64 mask); |
- | 634 | ||
- | 635 | struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn); |
|
- | 636 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
|
- | 637 | ||
634 | 638 | void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size); |
|
635 | 639 | ||
636 | #define pci_name(x) "radeon" |
640 | #define pci_name(x) "radeon" |
637 | 641 | ||
638 | #endif //__PCI__H__(n))-1)) |
642 | #endif //__PCI__H__(n))-1)) |
639 | 643 | ||
640 | int><(n))-1)) |
644 | int><(n))-1)) |
641 | 645 | ||
642 | int>><>><>><>><>><>><> |
646 | int>><>><>><>><>><>><> |