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#include
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#include
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#include
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#ifndef __PCI_H__
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#ifndef __PCI_H__
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#define __PCI_H__
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#define __PCI_H__
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#include
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#include
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#include
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#include
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#include
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/* pci_slot represents a physical slot */
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/* pci_slot represents a physical slot */
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struct pci_slot {
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struct pci_slot {
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{
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{
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    return(PCI_MAKE_TAG(busnum,devnum,funcnum));
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    return(PCI_MAKE_TAG(busnum,devnum,funcnum));
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}
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}
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struct resource
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{
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         resource_size_t start;
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         resource_size_t end;
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         const char *name;
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         unsigned long flags;
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         struct resource *parent, *sibling, *child;
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};
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/* This defines the direction arg to the DMA mapping routines. */
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/* This defines the direction arg to the DMA mapping routines. */
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#define PCI_DMA_BIDIRECTIONAL	0
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#define PCI_DMA_BIDIRECTIONAL	0
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#define PCI_DMA_TODEVICE	1
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#define PCI_DMA_TODEVICE	1
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#define PCI_DMA_FROMDEVICE	2
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#define PCI_DMA_FROMDEVICE	2
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#define PCI_DMA_NONE		3
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#define PCI_DMA_NONE		3
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};
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};
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/*
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 * IO resources have these defined flags.
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 */
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#define IORESOURCE_BITS         0x000000ff      /* Bus-specific bits */
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#define IORESOURCE_IO           0x00000100      /* Resource type */
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#define IORESOURCE_MEM          0x00000200
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#define IORESOURCE_IRQ          0x00000400
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#define IORESOURCE_DMA          0x00000800
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#define IORESOURCE_PREFETCH     0x00001000      /* No side effects */
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#define IORESOURCE_READONLY     0x00002000
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#define IORESOURCE_CACHEABLE    0x00004000
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#define IORESOURCE_RANGELENGTH  0x00008000
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#define IORESOURCE_SHADOWABLE   0x00010000
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#define IORESOURCE_BUS_HAS_VGA  0x00080000
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#define IORESOURCE_DISABLED     0x10000000
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#define IORESOURCE_UNSET        0x20000000
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#define IORESOURCE_AUTO         0x40000000
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#define IORESOURCE_BUSY         0x80000000      /* Driver has marked this resource busy */
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/* ISA PnP IRQ specific bits (IORESOURCE_BITS) */
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#define IORESOURCE_IRQ_HIGHEDGE         (1<<0)
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#define IORESOURCE_IRQ_LOWEDGE          (1<<1)
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#define IORESOURCE_IRQ_HIGHLEVEL        (1<<2)
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#define IORESOURCE_IRQ_LOWLEVEL         (1<<3)
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#define IORESOURCE_IRQ_SHAREABLE        (1<<4)
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/* ISA PnP DMA specific bits (IORESOURCE_BITS) */
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#define IORESOURCE_DMA_TYPE_MASK        (3<<0)
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#define IORESOURCE_DMA_8BIT             (0<<0)
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#define IORESOURCE_DMA_8AND16BIT        (1<<0)
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#define IORESOURCE_DMA_16BIT            (2<<0)
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#define IORESOURCE_DMA_MASTER           (1<<2)
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#define IORESOURCE_DMA_BYTE             (1<<3)
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#define IORESOURCE_DMA_WORD             (1<<4)
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#define IORESOURCE_DMA_SPEED_MASK       (3<<6)
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#define IORESOURCE_DMA_COMPATIBLE       (0<<6)
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#define IORESOURCE_DMA_TYPEA            (1<<6)
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#define IORESOURCE_DMA_TYPEB            (2<<6)
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#define IORESOURCE_DMA_TYPEF            (3<<6)
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/* ISA PnP memory I/O specific bits (IORESOURCE_BITS) */
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#define IORESOURCE_MEM_WRITEABLE        (1<<0)  /* dup: IORESOURCE_READONLY */
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#define IORESOURCE_MEM_CACHEABLE        (1<<1)  /* dup: IORESOURCE_CACHEABLE */
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#define IORESOURCE_MEM_RANGELENGTH      (1<<2)  /* dup: IORESOURCE_RANGELENGTH */
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#define IORESOURCE_MEM_TYPE_MASK        (3<<3)
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#define IORESOURCE_MEM_8BIT             (0<<3)
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#define IORESOURCE_MEM_16BIT            (1<<3)
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#define IORESOURCE_MEM_8AND16BIT        (2<<3)
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#define IORESOURCE_MEM_32BIT            (3<<3)
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#define IORESOURCE_MEM_SHADOWABLE       (1<<5)  /* dup: IORESOURCE_SHADOWABLE */
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#define IORESOURCE_MEM_EXPANSIONROM     (1<<6)
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/* PCI ROM control bits (IORESOURCE_BITS) */
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#define IORESOURCE_ROM_ENABLE           (1<<0)  /* ROM is enabled, same as PCI_ROM_ADDRESS_ENABLE */
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#define IORESOURCE_ROM_SHADOW           (1<<1)  /* ROM is copy at C000:0 */
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#define IORESOURCE_ROM_COPY             (1<<2)  /* ROM is alloc'd copy, resource field overlaid */
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#define IORESOURCE_ROM_BIOS_COPY        (1<<3)  /* ROM is BIOS copy, resource field overlaid */
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/* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
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#define IORESOURCE_PCI_FIXED            (1<<4)  /* Do not move resource */
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/*
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/*
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 *  For PCI devices, the region numbers are assigned this way:
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 *  For PCI devices, the region numbers are assigned this way:
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 *
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 *
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 *      0-5     standard PCI regions
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 *      0-5     standard PCI regions
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 *      6       expansion ROM
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 *      6       expansion ROM
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#define PCI_D3cold  ((pci_power_t __force) 4)
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#define PCI_D3cold  ((pci_power_t __force) 4)
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#define PCI_UNKNOWN ((pci_power_t __force) 5)
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#define PCI_UNKNOWN ((pci_power_t __force) 5)
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#define PCI_POWER_ERROR ((pci_power_t __force) -1)
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#define PCI_POWER_ERROR ((pci_power_t __force) -1)
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enum pci_bar_type {
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    pci_bar_unknown,    /* Standard PCI BAR probe */
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    pci_bar_io,         /* An io port BAR */
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    pci_bar_mem32,      /* A 32-bit memory BAR */
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    pci_bar_mem64,      /* A 64-bit memory BAR */
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};
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/*
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/*
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 * The pci_dev structure is used to describe PCI devices.
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 * The pci_dev structure is used to describe PCI devices.
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 */
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 */
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struct pci_dev {
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struct pci_dev {
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    struct list_head bus_list;  /* node in per-bus list */
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    struct list_head bus_list;  /* node in per-bus list */
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//    u32     saved_config_space[16]; /* config space saved at suspend time */
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//    u32     saved_config_space[16]; /* config space saved at suspend time */
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//    struct hlist_head saved_cap_space;
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//    struct hlist_head saved_cap_space;
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//    struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
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//    struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
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//    int rom_attr_enabled;       /* has display of the rom attribute been enabled? */
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    int rom_attr_enabled;       /* has display of the rom attribute been enabled? */
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//    struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
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//    struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
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//    struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
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//    struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
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};
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};
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int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
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int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
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				int cap);
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				int cap);
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int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
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int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
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struct pci_bus * pci_find_next_bus(const struct pci_bus *from);
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struct pci_bus * pci_find_next_bus(const struct pci_bus *from);
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unsigned int pci_scan_child_bus(struct pci_bus *bus);
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void pcibios_fixup_bus(struct pci_bus *b);
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static inline bool pci_is_root_bus(struct pci_bus *pbus)
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static inline bool pci_is_root_bus(struct pci_bus *pbus)
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{
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{
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    return !(pbus->parent);
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    return !(pbus->parent);
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}
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}
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{
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{
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    return !!pci_pcie_cap(dev);
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    return !!pci_pcie_cap(dev);
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}
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}
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int pci_read_config_dyte(struct pci_dev *dev, int where, u16 *val);
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int pci_read_config_word(struct pci_dev *dev, int where, u16 *val);
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int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val);
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static inline int pci_iov_init(struct pci_dev *dev)
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{
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    return -ENODEV;
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}
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static inline void pci_iov_release(struct pci_dev *dev)
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{
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}
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static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
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 626 
                       enum pci_bar_type *type)
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 627 
{
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 628 
    return 0;
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}
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static inline void pci_restore_iov_state(struct pci_dev *dev)
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 631 
{
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}
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static inline int pci_iov_bus_range(struct pci_bus *bus)
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{
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 635 
    return 0;
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}
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static inline int pci_enable_ats(struct pci_dev *dev, int ps)
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 639 
{
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 640 
    return -ENODEV;
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 641 
}
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 642 
static inline void pci_disable_ats(struct pci_dev *dev)
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 643 
{
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 644 
}
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static inline int pci_ats_queue_depth(struct pci_dev *dev)
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 646 
{
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 647 
    return -ENODEV;
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 648 
}
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 649 
static inline int pci_ats_enabled(struct pci_dev *dev)
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 650 
{
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 651 
    return 0;
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}
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 653 
 
677 
#define pci_name(x) "radeon"
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#define pci_name(x) "radeon"
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