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| Rev 9078 | Rev 9493 | ||
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| Line 32... | Line 32... | ||
| 32 | #include |
32 | #include |
| 33 | #include |
33 | #include |
| Line 34... | Line 34... | ||
| 34 | 34 | ||
| 35 | #include |
35 | #include |
| - | 36 | #include |
|
| - | 37 | ||
| - | 38 | #ifdef HAVE_ACPICA |
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| - | 39 | #include |
|
| - | 40 | #endif |
|
| 36 | #include |
41 | |
| 37 | /* |
42 | /* |
| 38 | * The PCI interface treats multi-function devices as independent |
43 | * The PCI interface treats multi-function devices as independent |
| 39 | * devices. The slot/function address of each device is encoded |
44 | * devices. The slot/function address of each device is encoded |
| 40 | * in a single byte as follows: |
45 | * in a single byte as follows: |
| Line 48... | Line 53... | ||
| 48 | */ |
53 | */ |
| 49 | #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) |
54 | #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) |
| 50 | /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ |
55 | /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ |
| 51 | #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) |
56 | #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) |
| Line -... | Line 57... | ||
| - | 57 | ||
| - | 58 | #define PCI_CFG_SPACE_SIZE 256 |
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| - | 59 | #define PCI_CFG_SPACE_EXP_SIZE 4096 |
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| - | 60 | ||
| - | 61 | enum pci_bar_type { |
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| - | 62 | pci_bar_unknown, /* Standard PCI BAR probe */ |
|
| - | 63 | pci_bar_io, /* An io port BAR */ |
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| - | 64 | pci_bar_mem32, /* A 32-bit memory BAR */ |
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| - | 65 | pci_bar_mem64, /* A 64-bit memory BAR */ |
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| - | 66 | }; |
|
| 52 | 67 | ||
| 53 | /* pci_slot represents a physical slot */ |
68 | /* pci_slot represents a physical slot */ |
| 54 | struct pci_slot { |
69 | struct pci_slot { |
| 55 | struct pci_bus *bus; /* The bus this slot is on */ |
70 | struct pci_bus *bus; /* The bus this slot is on */ |
| 56 | struct list_head list; /* node in list of slots on this bus */ |
71 | struct list_head list; /* node in list of slots on this bus */ |
| Line 277... | Line 292... | ||
| 277 | u8 msix_cap; /* MSI-X capability offset */ |
292 | u8 msix_cap; /* MSI-X capability offset */ |
| 278 | u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ |
293 | u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ |
| 279 | u8 rom_base_reg; /* which config register controls the ROM */ |
294 | u8 rom_base_reg; /* which config register controls the ROM */ |
| 280 | u8 pin; /* which interrupt pin this device uses */ |
295 | u8 pin; /* which interrupt pin this device uses */ |
| 281 | u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ |
296 | u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ |
| - | 297 | int pcie_type; |
|
| 282 | u8 dma_alias_devfn;/* devfn of DMA alias, if any */ |
298 | u8 dma_alias_devfn;/* devfn of DMA alias, if any */ |
| Line 283... | Line 299... | ||
| 283 | 299 | ||
| 284 | u64 dma_mask; /* Mask of the bits of bus address this |
300 | u64 dma_mask; /* Mask of the bits of bus address this |
| 285 | device implements. Normally this is |
301 | device implements. Normally this is |
| Line 378... | Line 394... | ||
| 378 | atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */ |
394 | atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */ |
| 379 | #endif |
395 | #endif |
| 380 | phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ |
396 | phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ |
| 381 | size_t romlen; /* Length of ROM if it's not from the BAR */ |
397 | size_t romlen; /* Length of ROM if it's not from the BAR */ |
| 382 | char *driver_override; /* Driver name to force a match */ |
398 | char *driver_override; /* Driver name to force a match */ |
| - | 399 | #ifdef HAVE_ACPICA |
|
| - | 400 | struct acpi_device *acpi_dev; |
|
| - | 401 | #endif |
|
| 383 | }; |
402 | }; |
| Line 384... | Line 403... | ||
| 384 | 403 | ||
| 385 | static inline struct pci_dev *pci_physfn(struct pci_dev *dev) |
404 | static inline struct pci_dev *pci_physfn(struct pci_dev *dev) |
| 386 | { |
405 | { |
| Line 450... | Line 469... | ||
| 450 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ |
469 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ |
| Line 451... | Line 470... | ||
| 451 | 470 | ||
| 452 | struct pci_bus { |
471 | struct pci_bus { |
| 453 | struct list_head node; /* node in list of buses */ |
472 | struct list_head node; /* node in list of buses */ |
| - | 473 | struct pci_bus *parent; /* parent bus this bridge is on */ |
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| - | 474 | struct pci_bus *subordinate; |
|
| 454 | struct pci_bus *parent; /* parent bus this bridge is on */ |
475 | struct pci_bus *secondary; |
| 455 | struct list_head children; /* list of child buses */ |
476 | struct list_head children; /* list of child buses */ |
| 456 | struct list_head devices; /* list of devices on this bus */ |
477 | struct list_head devices; /* list of devices on this bus */ |
| 457 | struct pci_dev *self; /* bridge device as seen by parent */ |
478 | struct pci_dev *self; /* bridge device as seen by parent */ |
| 458 | struct list_head slots; /* list of slots on this bus; |
479 | struct list_head slots; /* list of slots on this bus; |
| Line 483... | Line 504... | ||
| 483 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
504 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
| 484 | struct bin_attribute *legacy_mem; /* legacy mem */ |
505 | struct bin_attribute *legacy_mem; /* legacy mem */ |
| 485 | unsigned int is_added:1; |
506 | unsigned int is_added:1; |
| 486 | }; |
507 | }; |
| Line -... | Line 508... | ||
| - | 508 | ||
| - | 509 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
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| 487 | 510 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
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| Line 488... | Line 511... | ||
| 488 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
511 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
| 489 | 512 | ||
| 490 | /* |
513 | /* |
| Line 842... | Line 865... | ||
| 842 | void pci_bus_add_device(struct pci_dev *dev); |
865 | void pci_bus_add_device(struct pci_dev *dev); |
| 843 | void pci_read_bridge_bases(struct pci_bus *child); |
866 | void pci_read_bridge_bases(struct pci_bus *child); |
| 844 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
867 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
| 845 | struct resource *res); |
868 | struct resource *res); |
| 846 | struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); |
869 | struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); |
| 847 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); |
870 | u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin); |
| 848 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
871 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
| 849 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
872 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
| 850 | struct pci_dev *pci_dev_get(struct pci_dev *dev); |
873 | struct pci_dev *pci_dev_get(struct pci_dev *dev); |
| 851 | void pci_dev_put(struct pci_dev *dev); |
874 | void pci_dev_put(struct pci_dev *dev); |
| 852 | void pci_remove_bus(struct pci_bus *b); |
875 | void pci_remove_bus(struct pci_bus *b); |