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#ifndef _ASM_X86_CPUFEATURE_H
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#ifndef _ASM_X86_CPUFEATURE_H
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#define _ASM_X86_CPUFEATURE_H
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#define _ASM_X86_CPUFEATURE_H
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#include
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#include
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#define NCAPINTS	9	/* N 32-bit words worth of info */
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#define NCAPINTS	10	/* N 32-bit words worth of info */
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 10 
 
11 
/*
 11 
/*
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#define X86_FEATURE_REP_GOOD	(3*32+16) /* rep microcode works well */
 87 
#define X86_FEATURE_REP_GOOD	(3*32+16) /* rep microcode works well */
88 
#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */
 88 
#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */
89 
#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */
 89 
#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */
90 
#define X86_FEATURE_11AP	(3*32+19) /* "" Bad local APIC aka 11AP */
 90 
#define X86_FEATURE_11AP	(3*32+19) /* "" Bad local APIC aka 11AP */
91 
#define X86_FEATURE_NOPL	(3*32+20) /* The NOPL (0F 1F) instructions */
 91 
#define X86_FEATURE_NOPL	(3*32+20) /* The NOPL (0F 1F) instructions */
92 
#define X86_FEATURE_AMDC1E	(3*32+21) /* AMD C1E detected */
 92 
					  /* 21 available, was AMD_C1E */
93 
#define X86_FEATURE_XTOPOLOGY	(3*32+22) /* cpu topology enum extensions */
 93 
#define X86_FEATURE_XTOPOLOGY	(3*32+22) /* cpu topology enum extensions */
94 
#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
 94 
#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
95 
#define X86_FEATURE_NONSTOP_TSC	(3*32+24) /* TSC does not stop in C states */
 95 
#define X86_FEATURE_NONSTOP_TSC	(3*32+24) /* TSC does not stop in C states */
96 
#define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */
 96 
#define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */
97 
#define X86_FEATURE_EXTD_APICID	(3*32+26) /* has extended APICID (8 bits) */
 97 
#define X86_FEATURE_EXTD_APICID	(3*32+26) /* has extended APICID (8 bits) */
98 
#define X86_FEATURE_AMD_DCM     (3*32+27) /* multi-node processor */
 98 
#define X86_FEATURE_AMD_DCM     (3*32+27) /* multi-node processor */
99 
#define X86_FEATURE_APERFMPERF	(3*32+28) /* APERFMPERF */
 99 
#define X86_FEATURE_APERFMPERF	(3*32+28) /* APERFMPERF */
- 
 
 100 
#define X86_FEATURE_EAGER_FPU	(3*32+29) /* "eagerfpu" Non lazy FPU restore */
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 101 
 
101 
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 102 
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
102 
#define X86_FEATURE_XMM3	(4*32+ 0) /* "pni" SSE-3 */
 103 
#define X86_FEATURE_XMM3	(4*32+ 0) /* "pni" SSE-3 */
103 
#define X86_FEATURE_PCLMULQDQ	(4*32+ 1) /* PCLMULQDQ instruction */
 104 
#define X86_FEATURE_PCLMULQDQ	(4*32+ 1) /* PCLMULQDQ instruction */
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112 
#define X86_FEATURE_CID		(4*32+10) /* Context ID */
 113 
#define X86_FEATURE_CID		(4*32+10) /* Context ID */
113 
#define X86_FEATURE_FMA		(4*32+12) /* Fused multiply-add */
 114 
#define X86_FEATURE_FMA		(4*32+12) /* Fused multiply-add */
114 
#define X86_FEATURE_CX16	(4*32+13) /* CMPXCHG16B */
 115 
#define X86_FEATURE_CX16	(4*32+13) /* CMPXCHG16B */
115 
#define X86_FEATURE_XTPR	(4*32+14) /* Send Task Priority Messages */
 116 
#define X86_FEATURE_XTPR	(4*32+14) /* Send Task Priority Messages */
116 
#define X86_FEATURE_PDCM	(4*32+15) /* Performance Capabilities */
 117 
#define X86_FEATURE_PDCM	(4*32+15) /* Performance Capabilities */
- 
 
 118 
#define X86_FEATURE_PCID	(4*32+17) /* Process Context Identifiers */
117 
#define X86_FEATURE_DCA		(4*32+18) /* Direct Cache Access */
 119 
#define X86_FEATURE_DCA		(4*32+18) /* Direct Cache Access */
118 
#define X86_FEATURE_XMM4_1	(4*32+19) /* "sse4_1" SSE-4.1 */
 120 
#define X86_FEATURE_XMM4_1	(4*32+19) /* "sse4_1" SSE-4.1 */
119 
#define X86_FEATURE_XMM4_2	(4*32+20) /* "sse4_2" SSE-4.2 */
 121 
#define X86_FEATURE_XMM4_2	(4*32+20) /* "sse4_2" SSE-4.2 */
120 
#define X86_FEATURE_X2APIC	(4*32+21) /* x2APIC */
 122 
#define X86_FEATURE_X2APIC	(4*32+21) /* x2APIC */
121 
#define X86_FEATURE_MOVBE	(4*32+22) /* MOVBE instruction */
 123 
#define X86_FEATURE_MOVBE	(4*32+22) /* MOVBE instruction */
122 
#define X86_FEATURE_POPCNT      (4*32+23) /* POPCNT instruction */
 124 
#define X86_FEATURE_POPCNT      (4*32+23) /* POPCNT instruction */
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 125 
#define X86_FEATURE_TSC_DEADLINE_TIMER	(4*32+24) /* Tsc deadline timer */
123 
#define X86_FEATURE_AES		(4*32+25) /* AES instructions */
 126 
#define X86_FEATURE_AES		(4*32+25) /* AES instructions */
124 
#define X86_FEATURE_XSAVE	(4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
 127 
#define X86_FEATURE_XSAVE	(4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
125 
#define X86_FEATURE_OSXSAVE	(4*32+27) /* "" XSAVE enabled in the OS */
 128 
#define X86_FEATURE_OSXSAVE	(4*32+27) /* "" XSAVE enabled in the OS */
126 
#define X86_FEATURE_AVX		(4*32+28) /* Advanced Vector Extensions */
 129 
#define X86_FEATURE_AVX		(4*32+28) /* Advanced Vector Extensions */
- 
 
 130 
#define X86_FEATURE_F16C	(4*32+29) /* 16-bit fp conversions */
- 
 
 131 
#define X86_FEATURE_RDRAND	(4*32+30) /* The RDRAND instruction */
127 
#define X86_FEATURE_HYPERVISOR	(4*32+31) /* Running on a hypervisor */
 132 
#define X86_FEATURE_HYPERVISOR	(4*32+31) /* Running on a hypervisor */
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 133 
 
129 
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
 134 
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
130 
#define X86_FEATURE_XSTORE	(5*32+ 2) /* "rng" RNG present (xstore) */
 135 
#define X86_FEATURE_XSTORE	(5*32+ 2) /* "rng" RNG present (xstore) */
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148 
#define X86_FEATURE_SSE4A	(6*32+ 6) /* SSE-4A */
 153 
#define X86_FEATURE_SSE4A	(6*32+ 6) /* SSE-4A */
149 
#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
 154 
#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
150 
#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
 155 
#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
151 
#define X86_FEATURE_OSVW	(6*32+ 9) /* OS Visible Workaround */
 156 
#define X86_FEATURE_OSVW	(6*32+ 9) /* OS Visible Workaround */
152 
#define X86_FEATURE_IBS		(6*32+10) /* Instruction Based Sampling */
 157 
#define X86_FEATURE_IBS		(6*32+10) /* Instruction Based Sampling */
153 
#define X86_FEATURE_SSE5	(6*32+11) /* SSE-5 */
 158 
#define X86_FEATURE_XOP		(6*32+11) /* extended AVX instructions */
154 
#define X86_FEATURE_SKINIT	(6*32+12) /* SKINIT/STGI instructions */
 159 
#define X86_FEATURE_SKINIT	(6*32+12) /* SKINIT/STGI instructions */
155 
#define X86_FEATURE_WDT		(6*32+13) /* Watchdog timer */
 160 
#define X86_FEATURE_WDT		(6*32+13) /* Watchdog timer */
- 
 
 161 
#define X86_FEATURE_LWP		(6*32+15) /* Light Weight Profiling */
- 
 
 162 
#define X86_FEATURE_FMA4	(6*32+16) /* 4 operands MAC instructions */
- 
 
 163 
#define X86_FEATURE_TCE		(6*32+17) /* translation cache extension */
- 
 
 164 
#define X86_FEATURE_NODEID_MSR	(6*32+19) /* NodeId MSR */
- 
 
 165 
#define X86_FEATURE_TBM		(6*32+21) /* trailing bit manipulations */
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 166 
#define X86_FEATURE_TOPOEXT	(6*32+22) /* topology extensions CPUID leafs */
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 167 
#define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
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 168 
 
157 
/*
 169 
/*
158 
 * Auxiliary flags: Linux defined - For features scattered in various
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 * Auxiliary flags: Linux defined - For features scattered in various
159 
 * CPUID levels like 0x6, 0xA etc
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 * CPUID levels like 0x6, 0xA etc, word 7
160 
 */
 172 
 */
161 
#define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration */
 173 
#define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration */
- 
 
 174 
#define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer */
- 
 
 175 
#define X86_FEATURE_CPB		(7*32+ 2) /* AMD Core Performance Boost */
- 
 
 176 
#define X86_FEATURE_EPB		(7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
- 
 
 177 
#define X86_FEATURE_XSAVEOPT	(7*32+ 4) /* Optimized Xsave */
- 
 
 178 
#define X86_FEATURE_PLN		(7*32+ 5) /* Intel Power Limit Notification */
- 
 
 179 
#define X86_FEATURE_PTS		(7*32+ 6) /* Intel Package Thermal Status */
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 180 
#define X86_FEATURE_DTHERM	(7*32+ 7) /* Digital Thermal Sensor */
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162 
#define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer */
 181 
#define X86_FEATURE_HW_PSTATE	(7*32+ 8) /* AMD HW-PState */
163 
 
 182 
 
164 
/* Virtualization flags: Linux defined */
 183 
/* Virtualization flags: Linux defined, word 8 */
165 
#define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
 184 
#define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
166 
#define X86_FEATURE_VNMI        (8*32+ 1) /* Intel Virtual NMI */
 185 
#define X86_FEATURE_VNMI        (8*32+ 1) /* Intel Virtual NMI */
167 
#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
 186 
#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
- 
 
 187 
#define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
- 
 
 188 
#define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
- 
 
 189 
#define X86_FEATURE_NPT		(8*32+ 5) /* AMD Nested Page Table support */
- 
 
 190 
#define X86_FEATURE_LBRV	(8*32+ 6) /* AMD LBR Virtualization support */
- 
 
 191 
#define X86_FEATURE_SVML	(8*32+ 7) /* "svm_lock" AMD SVM locking MSR */
- 
 
 192 
#define X86_FEATURE_NRIPS	(8*32+ 8) /* "nrip_save" AMD SVM next_rip save */
- 
 
 193 
#define X86_FEATURE_TSCRATEMSR  (8*32+ 9) /* "tsc_scale" AMD TSC scaling support */
- 
 
 194 
#define X86_FEATURE_VMCBCLEAN   (8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */
- 
 
 195 
#define X86_FEATURE_FLUSHBYASID (8*32+11) /* AMD flush-by-ASID support */
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 196 
#define X86_FEATURE_DECODEASSISTS (8*32+12) /* AMD Decode Assists support */
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 197 
#define X86_FEATURE_PAUSEFILTER (8*32+13) /* AMD filtered pause intercept */
- 
 
 198 
#define X86_FEATURE_PFTHRESHOLD (8*32+14) /* AMD pause filter threshold */
- 
 
 199 
 
- 
 
 200 
 
- 
 
 201 
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
- 
 
 202 
#define X86_FEATURE_FSGSBASE	(9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
- 
 
 203 
#define X86_FEATURE_BMI1	(9*32+ 3) /* 1st group bit manipulation extensions */
- 
 
 204 
#define X86_FEATURE_HLE		(9*32+ 4) /* Hardware Lock Elision */
- 
 
 205 
#define X86_FEATURE_AVX2	(9*32+ 5) /* AVX2 instructions */
- 
 
 206 
#define X86_FEATURE_SMEP	(9*32+ 7) /* Supervisor Mode Execution Protection */
- 
 
 207 
#define X86_FEATURE_BMI2	(9*32+ 8) /* 2nd group bit manipulation extensions */
- 
 
 208 
#define X86_FEATURE_ERMS	(9*32+ 9) /* Enhanced REP MOVSB/STOSB */
- 
 
 209 
#define X86_FEATURE_INVPCID	(9*32+10) /* Invalidate Processor Context ID */
- 
 
 210 
#define X86_FEATURE_RTM		(9*32+11) /* Restricted Transactional Memory */
- 
 
 211 
#define X86_FEATURE_RDSEED	(9*32+18) /* The RDSEED instruction */
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168 
#define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
 212 
#define X86_FEATURE_ADX		(9*32+19) /* The ADCX and ADOX instructions */
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169 
#define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
 213 
#define X86_FEATURE_SMAP	(9*32+20) /* Supervisor Mode Access Prevention */
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176 
extern const char * const x86_power_flags[32];
 220 
extern const char * const x86_power_flags[32];
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177 
 
 221 
 
178 
#define test_cpu_cap(c, bit)						\
 222 
#define test_cpu_cap(c, bit)						\
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179 
	 test_bit(bit, (unsigned long *)((c)->x86_capability))
 223 
	 test_bit(bit, (unsigned long *)((c)->x86_capability))
180 
 
 - 
 
181 
#define cpu_has(c, bit)							\
 224 
 
182 
	(__builtin_constant_p(bit) &&					\
 225 
#define REQUIRED_MASK_BIT_SET(bit)					\
183 
	 ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) ||	\
 226 
	 ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) ||	\
184 
	   (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) ||	\
 227 
	   (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) ||	\
185 
	   (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) ||	\
 228 
	   (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) ||	\
186 
	   (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) ||	\
 229 
	   (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) ||	\
187 
	   (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) ||	\
 230 
	   (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) ||	\
188 
	   (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) ||	\
 231 
	   (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) ||	\
- 
 
 232 
	   (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) ||	\
- 
 
 233 
	   (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ||	\
- 
 
 234 
	   (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) ||	\
189 
	   (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) ||	\
 235 
	   (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) )
- 
 
 236 
 
190 
	   (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) )	\
 237 
#define cpu_has(c, bit)							\
Line -... Line 238...
- 
 
 238 
	(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 :	\
- 
 
 239 
	 test_cpu_cap(c, bit))
- 
 
 240 
 
- 
 
 241 
#define this_cpu_has(bit)						\
191 
	  ? 1 :								\
 242 
	(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : 	\
Line 192... Line 243...
192 
	 test_cpu_cap(c, bit))
 243 
	 x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability))
193 
 
 244 
 
194 
#define boot_cpu_has(bit)	cpu_has(&boot_cpu_data, bit)
 245 
#define boot_cpu_has(bit)	cpu_has(&boot_cpu_data, bit)
Line 217... Line 268...
217 
#define cpu_has_mmx		boot_cpu_has(X86_FEATURE_MMX)
 268 
#define cpu_has_mmx		boot_cpu_has(X86_FEATURE_MMX)
218 
#define cpu_has_fxsr		boot_cpu_has(X86_FEATURE_FXSR)
 269 
#define cpu_has_fxsr		boot_cpu_has(X86_FEATURE_FXSR)
219 
#define cpu_has_xmm		boot_cpu_has(X86_FEATURE_XMM)
 270 
#define cpu_has_xmm		boot_cpu_has(X86_FEATURE_XMM)
220 
#define cpu_has_xmm2		boot_cpu_has(X86_FEATURE_XMM2)
 271 
#define cpu_has_xmm2		boot_cpu_has(X86_FEATURE_XMM2)
221 
#define cpu_has_xmm3		boot_cpu_has(X86_FEATURE_XMM3)
 272 
#define cpu_has_xmm3		boot_cpu_has(X86_FEATURE_XMM3)
- 
 
 273 
#define cpu_has_ssse3		boot_cpu_has(X86_FEATURE_SSSE3)
222 
#define cpu_has_aes		boot_cpu_has(X86_FEATURE_AES)
 274 
#define cpu_has_aes		boot_cpu_has(X86_FEATURE_AES)
- 
 
 275 
#define cpu_has_avx		boot_cpu_has(X86_FEATURE_AVX)
223 
#define cpu_has_ht		boot_cpu_has(X86_FEATURE_HT)
 276 
#define cpu_has_ht		boot_cpu_has(X86_FEATURE_HT)
224 
#define cpu_has_mp		boot_cpu_has(X86_FEATURE_MP)
 277 
#define cpu_has_mp		boot_cpu_has(X86_FEATURE_MP)
225 
#define cpu_has_nx		boot_cpu_has(X86_FEATURE_NX)
 278 
#define cpu_has_nx		boot_cpu_has(X86_FEATURE_NX)
226 
#define cpu_has_k6_mtrr		boot_cpu_has(X86_FEATURE_K6_MTRR)
 279 
#define cpu_has_k6_mtrr		boot_cpu_has(X86_FEATURE_K6_MTRR)
227 
#define cpu_has_cyrix_arr	boot_cpu_has(X86_FEATURE_CYRIX_ARR)
 280 
#define cpu_has_cyrix_arr	boot_cpu_has(X86_FEATURE_CYRIX_ARR)
Line 245... Line 298...
245 
#define cpu_has_pat		boot_cpu_has(X86_FEATURE_PAT)
 298 
#define cpu_has_pat		boot_cpu_has(X86_FEATURE_PAT)
246 
#define cpu_has_xmm4_1		boot_cpu_has(X86_FEATURE_XMM4_1)
 299 
#define cpu_has_xmm4_1		boot_cpu_has(X86_FEATURE_XMM4_1)
247 
#define cpu_has_xmm4_2		boot_cpu_has(X86_FEATURE_XMM4_2)
 300 
#define cpu_has_xmm4_2		boot_cpu_has(X86_FEATURE_XMM4_2)
248 
#define cpu_has_x2apic		boot_cpu_has(X86_FEATURE_X2APIC)
 301 
#define cpu_has_x2apic		boot_cpu_has(X86_FEATURE_X2APIC)
249 
#define cpu_has_xsave		boot_cpu_has(X86_FEATURE_XSAVE)
 302 
#define cpu_has_xsave		boot_cpu_has(X86_FEATURE_XSAVE)
- 
 
 303 
#define cpu_has_xsaveopt	boot_cpu_has(X86_FEATURE_XSAVEOPT)
- 
 
 304 
#define cpu_has_osxsave		boot_cpu_has(X86_FEATURE_OSXSAVE)
250 
#define cpu_has_hypervisor	boot_cpu_has(X86_FEATURE_HYPERVISOR)
 305 
#define cpu_has_hypervisor	boot_cpu_has(X86_FEATURE_HYPERVISOR)
251 
#define cpu_has_pclmulqdq	boot_cpu_has(X86_FEATURE_PCLMULQDQ)
 306 
#define cpu_has_pclmulqdq	boot_cpu_has(X86_FEATURE_PCLMULQDQ)
- 
 
 307 
#define cpu_has_perfctr_core	boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
- 
 
 308 
#define cpu_has_cx8		boot_cpu_has(X86_FEATURE_CX8)
- 
 
 309 
#define cpu_has_cx16		boot_cpu_has(X86_FEATURE_CX16)
- 
 
 310 
#define cpu_has_eager_fpu	boot_cpu_has(X86_FEATURE_EAGER_FPU)
Line 252... Line 311...
252 
 
 311 
 
253 
#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
 312 
#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
254 
# define cpu_has_invlpg		1
 313 
# define cpu_has_invlpg		1
255 
#else
 314 
#else