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| Rev 2967 | Rev 3031 | ||
|---|---|---|---|
| Line 31... | Line 31... | ||
| 31 | */ |
31 | */ |
| Line 32... | Line 32... | ||
| 32 | 32 | ||
| 33 | #ifndef __RADEON_DRM_H__ |
33 | #ifndef __RADEON_DRM_H__ |
| Line 34... | Line 34... | ||
| 34 | #define __RADEON_DRM_H__ |
34 | #define __RADEON_DRM_H__ |
| Line 35... | Line 35... | ||
| 35 | 35 | ||
| 36 | #include "drm.h" |
36 | #include |
| 37 | 37 | ||
| 38 | /* WARNING: If you change any of these defines, make sure to change the |
38 | /* WARNING: If you change any of these defines, make sure to change the |
| Line 507... | Line 507... | ||
| 507 | #define DRM_RADEON_CS 0x26 |
507 | #define DRM_RADEON_CS 0x26 |
| 508 | #define DRM_RADEON_INFO 0x27 |
508 | #define DRM_RADEON_INFO 0x27 |
| 509 | #define DRM_RADEON_GEM_SET_TILING 0x28 |
509 | #define DRM_RADEON_GEM_SET_TILING 0x28 |
| 510 | #define DRM_RADEON_GEM_GET_TILING 0x29 |
510 | #define DRM_RADEON_GEM_GET_TILING 0x29 |
| 511 | #define DRM_RADEON_GEM_BUSY 0x2a |
511 | #define DRM_RADEON_GEM_BUSY 0x2a |
| - | 512 | #define DRM_RADEON_GEM_VA 0x2b |
|
| Line 512... | Line 513... | ||
| 512 | 513 | ||
| 513 | #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) |
514 | #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) |
| 514 | #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) |
515 | #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) |
| 515 | #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) |
516 | #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) |
| Line 805... | Line 806... | ||
| 805 | 806 | ||
| 806 | #define RADEON_TILING_MACRO 0x1 |
807 | #define RADEON_TILING_MACRO 0x1 |
| 807 | #define RADEON_TILING_MICRO 0x2 |
808 | #define RADEON_TILING_MICRO 0x2 |
| 808 | #define RADEON_TILING_SWAP_16BIT 0x4 |
809 | #define RADEON_TILING_SWAP_16BIT 0x4 |
| 809 | #define RADEON_TILING_SWAP_32BIT 0x8 |
810 | #define RADEON_TILING_SWAP_32BIT 0x8 |
| 810 | #define RADEON_TILING_SURFACE 0x10 /* this object requires a surface |
811 | /* this object requires a surface when mapped - i.e. front buffer */ |
| 811 | * when mapped - i.e. front buffer */ |
812 | #define RADEON_TILING_SURFACE 0x10 |
| - | 813 | #define RADEON_TILING_MICRO_SQUARE 0x20 |
|
| - | 814 | #define RADEON_TILING_EG_BANKW_SHIFT 8 |
|
| - | 815 | #define RADEON_TILING_EG_BANKW_MASK 0xf |
|
| - | 816 | #define RADEON_TILING_EG_BANKH_SHIFT 12 |
|
| - | 817 | #define RADEON_TILING_EG_BANKH_MASK 0xf |
|
| - | 818 | #define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 |
|
| - | 819 | #define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf |
|
| - | 820 | #define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24 |
|
| - | 821 | #define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf |
|
| - | 822 | #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 |
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| Line 812... | Line 823... | ||
| 812 | #define RADEON_TILING_MICRO_SQUARE 0x20 |
823 | #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf |
| 813 | 824 | ||
| 814 | struct drm_radeon_gem_set_tiling { |
825 | struct drm_radeon_gem_set_tiling { |
| 815 | uint32_t handle; |
826 | uint32_t handle; |
| Line 895... | Line 906... | ||
| 895 | }; |
906 | }; |
| Line 896... | Line 907... | ||
| 896 | 907 | ||
| 897 | #define RADEON_CHUNK_ID_RELOCS 0x01 |
908 | #define RADEON_CHUNK_ID_RELOCS 0x01 |
| 898 | #define RADEON_CHUNK_ID_IB 0x02 |
909 | #define RADEON_CHUNK_ID_IB 0x02 |
| - | 910 | #define RADEON_CHUNK_ID_FLAGS 0x03 |
|
| Line 899... | Line 911... | ||
| 899 | #define RADEON_CHUNK_ID_FLAGS 0x03 |
911 | #define RADEON_CHUNK_ID_CONST_IB 0x04 |
| 900 | 912 | ||
| 901 | /* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */ |
913 | /* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */ |
| 902 | #define RADEON_CS_KEEP_TILING_FLAGS 0x01 |
914 | #define RADEON_CS_KEEP_TILING_FLAGS 0x01 |
| Line 912... | Line 924... | ||
| 912 | uint32_t length_dw; |
924 | uint32_t length_dw; |
| 913 | uint64_t chunk_data; |
925 | uint64_t chunk_data; |
| 914 | }; |
926 | }; |
| Line 915... | Line 927... | ||
| 915 | 927 | ||
| 916 | /* drm_radeon_cs_reloc.flags */ |
- | |
| Line 917... | Line 928... | ||
| 917 | #define RADEON_RELOC_DONT_SYNC 0x01 |
928 | /* drm_radeon_cs_reloc.flags */ |
| 918 | 929 | ||
| 919 | struct drm_radeon_cs_reloc { |
930 | struct drm_radeon_cs_reloc { |
| 920 | uint32_t handle; |
931 | uint32_t handle; |
| Line 949... | Line 960... | ||
| 949 | #define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */ |
960 | #define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */ |
| 950 | /* virtual address start, va < start are reserved by the kernel */ |
961 | /* virtual address start, va < start are reserved by the kernel */ |
| 951 | #define RADEON_INFO_VA_START 0x0e |
962 | #define RADEON_INFO_VA_START 0x0e |
| 952 | /* maximum size of ib using the virtual memory cs */ |
963 | /* maximum size of ib using the virtual memory cs */ |
| 953 | #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f |
964 | #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f |
| - | 965 | /* max pipes - needed for compute shaders */ |
|
| - | 966 | #define RADEON_INFO_MAX_PIPES 0x10 |
|
| - | 967 | /* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */ |
|
| - | 968 | #define RADEON_INFO_TIMESTAMP 0x11 |
|
| Line 954... | Line 969... | ||
| 954 | 969 | ||
| 955 | struct drm_radeon_info { |
970 | struct drm_radeon_info { |
| 956 | uint32_t request; |
971 | uint32_t request; |
| 957 | uint32_t pad; |
972 | uint32_t pad; |