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/* Common header for intel-gtt.ko and i915.ko */
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/* Common header for intel-gtt.ko and i915.ko */
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#ifndef _DRM_INTEL_GTT_H
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#ifndef _DRM_INTEL_GTT_H
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#define	_DRM_INTEL_GTT_H
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#define	_DRM_INTEL_GTT_H
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struct agp_bridge_data;
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struct agp_bridge_data;
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struct intel_gtt {
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	/* Size of memory reserved for graphics by the BIOS */
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	unsigned int stolen_size;
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	/* Total number of gtt entries. */
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	unsigned int gtt_total_entries;
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void intel_gtt_get(size_t *gtt_total, size_t *stolen_size,
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	/* Part of the gtt that is mappable by the cpu, for those chips where
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	 * this is not the full gtt. */
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	unsigned int gtt_mappable_entries;
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	/* Whether i915 needs to use the dmar apis or not. */
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	unsigned int needs_dmar : 1;
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	/* Whether we idle the gpu before mapping/unmapping */
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	unsigned int do_idle_maps : 1;
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	/* Share the scratch page dma with ppgtts. */
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	dma_addr_t scratch_page_dma;
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	struct page *scratch_page;
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	/* for ppgtt PDE access */
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	u32 __iomem *gtt;
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	/* needed for ioremap in drm/i915 */
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	phys_addr_t gma_bus_addr;
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} *intel_gtt_get(void);
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		   phys_addr_t *mappable_base, unsigned long *mappable_end);
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int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
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int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
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		     struct agp_bridge_data *bridge);
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		     struct agp_bridge_data *bridge);
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void intel_gmch_remove(void);
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void intel_gmch_remove(void);
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bool intel_enable_gtt(void);
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bool intel_enable_gtt(void);
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void intel_gtt_chipset_flush(void);
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void intel_gtt_chipset_flush(void);
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void intel_gtt_insert_sg_entries(struct sg_table *st,
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void intel_gtt_insert_sg_entries(struct sg_table *st,
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				 unsigned int pg_start,
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				 unsigned int pg_start,
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				 unsigned int flags);
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				 unsigned int flags);
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void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
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void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
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/* Special gtt memory types */
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/* Special gtt memory types */
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#define AGP_DCACHE_MEMORY	1
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#define AGP_DCACHE_MEMORY	1
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#define AGP_PHYS_MEMORY		2
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#define AGP_PHYS_MEMORY		2
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/* New caching attributes for gen6/sandybridge */
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#define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2)
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#define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4)
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/* flag for GFDT type */
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/* flag for GFDT type */
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#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
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#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
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#ifdef CONFIG_INTEL_IOMMU
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#ifdef CONFIG_INTEL_IOMMU
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extern int intel_iommu_gfx_mapped;
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extern int intel_iommu_gfx_mapped;
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#endif
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#endif
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#endif
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#endif