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| 3 | #ifndef _DRM_INTEL_GTT_H |
3 | #ifndef _DRM_INTEL_GTT_H |
| 4 | #define _DRM_INTEL_GTT_H |
4 | #define _DRM_INTEL_GTT_H |
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| 5 | 5 | ||
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| 6 | struct agp_bridge_data; |
- | |
| 7 | - | ||
| 8 | struct intel_gtt { |
- | |
| 9 | /* Size of memory reserved for graphics by the BIOS */ |
- | |
| 10 | unsigned int stolen_size; |
6 | struct agp_bridge_data; |
| 11 | /* Total number of gtt entries. */ |
7 | |
| 12 | unsigned int gtt_total_entries; |
- | |
| 13 | /* Part of the gtt that is mappable by the cpu, for those chips where |
- | |
| 14 | * this is not the full gtt. */ |
- | |
| 15 | unsigned int gtt_mappable_entries; |
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| 16 | /* Whether i915 needs to use the dmar apis or not. */ |
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| 17 | unsigned int needs_dmar : 1; |
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| 18 | /* Whether we idle the gpu before mapping/unmapping */ |
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| 19 | unsigned int do_idle_maps : 1; |
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| 20 | /* Share the scratch page dma with ppgtts. */ |
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| 21 | dma_addr_t scratch_page_dma; |
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| 22 | struct page *scratch_page; |
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| 23 | /* for ppgtt PDE access */ |
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| 24 | u32 __iomem *gtt; |
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| 25 | /* needed for ioremap in drm/i915 */ |
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| 26 | phys_addr_t gma_bus_addr; |
8 | void intel_gtt_get(size_t *gtt_total, size_t *stolen_size, |
| 27 | } *intel_gtt_get(void); |
9 | phys_addr_t *mappable_base, unsigned long *mappable_end); |
| 28 | 10 | ||
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| 40 | 22 | ||
| 41 | /* Special gtt memory types */ |
23 | /* Special gtt memory types */ |
| 42 | #define AGP_DCACHE_MEMORY 1 |
24 | #define AGP_DCACHE_MEMORY 1 |
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| 43 | #define AGP_PHYS_MEMORY 2 |
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| 44 | - | ||
| 45 | /* New caching attributes for gen6/sandybridge */ |
- | |
| 46 | #define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2) |
- | |
| 47 | #define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4) |
25 | #define AGP_PHYS_MEMORY 2 |
| 48 | 26 | ||
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| 49 | /* flag for GFDT type */ |
27 | /* flag for GFDT type */ |
| 50 | #define AGP_USER_CACHED_MEMORY_GFDT (1 << 3) |
28 | #define AGP_USER_CACHED_MEMORY_GFDT (1 << 3) |