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#define _DRM_DP_HELPER_H_
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#define _DRM_DP_HELPER_H_
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#include
26 
#include
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#include
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 28 
 
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 29 
/*
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 30 
 * Unless otherwise noted, all values are from the DP 1.1a spec.  Note that
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 31 
 * DP and DPCD versions are independent.  Differences from 1.0 are not noted,
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 32 
 * 1.0 devices basically don't exist in the wild.
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 33 
 *
27 
#include
34 
 * Abbreviations, in chronological order:
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 35 
 *
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 36 
 * eDP: Embedded DisplayPort version 1
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 37 
 * DPI: DisplayPort Interoperability Guideline v1.1a
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 38 
 * 1.2: DisplayPort 1.2
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 39 
 *
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 40 
 * 1.2 formally includes both eDP and DPI definitions.
29 
/* From the VESA DisplayPort spec */
 41 
 */
30 
 
 42 
 
31 
#define AUX_NATIVE_WRITE	0x8
 43 
#define AUX_NATIVE_WRITE	0x8
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 63 
 
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#define DP_MAX_LINK_RATE                    0x001
 64 
#define DP_MAX_LINK_RATE                    0x001
53 
 
 65 
 
54 
#define DP_MAX_LANE_COUNT                   0x002
 66 
#define DP_MAX_LANE_COUNT                   0x002
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# define DP_MAX_LANE_COUNT_MASK		    0x1f
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# define DP_MAX_LANE_COUNT_MASK		    0x1f
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# define DP_TPS3_SUPPORTED		    (1 << 6)
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# define DP_TPS3_SUPPORTED		    (1 << 6) /* 1.2 */
57 
# define DP_ENHANCED_FRAME_CAP		    (1 << 7)
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# define DP_ENHANCED_FRAME_CAP		    (1 << 7)
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/* 00b = DisplayPort */
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/* 00b = DisplayPort */
68 
/* 01b = Analog */
 80 
/* 01b = Analog */
69 
/* 10b = TMDS or HDMI */
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/* 10b = TMDS or HDMI */
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/* 11b = Other */
 82 
/* 11b = Other */
71 
# define DP_FORMAT_CONVERSION               (1 << 3)
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# define DP_FORMAT_CONVERSION               (1 << 3)
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# define DP_DETAILED_CAP_INFO_AVAILABLE	    (1 << 4) /* DPI */
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 85 
 
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#define DP_MAIN_LINK_CHANNEL_CODING         0x006
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 87 
 
- 
 
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#define DP_DOWN_STREAM_PORT_COUNT	    0x007
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# define DP_PORT_COUNT_MASK		    0x0f
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 90 
# define DP_MSA_TIMING_PAR_IGNORED	    (1 << 6) /* eDP */
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# define DP_OUI_SUPPORT			    (1 << 7)
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 92 
 
- 
 
 93 
#define DP_I2C_SPEED_CAP		    0x00c    /* DPI */
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# define DP_I2C_SPEED_1K		    0x01
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# define DP_I2C_SPEED_5K		    0x02
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# define DP_I2C_SPEED_10K		    0x04
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# define DP_I2C_SPEED_100K		    0x08
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# define DP_I2C_SPEED_400K		    0x10
73 
#define DP_MAIN_LINK_CHANNEL_CODING         0x006
 99 
# define DP_I2C_SPEED_1M		    0x20
74 
 
 100 
 
- 
 
 101 
#define DP_EDP_CONFIGURATION_CAP            0x00d   /* XXX 1.2? */
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#define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
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 103 
 
- 
 
 104 
/* Multiple stream transport */
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#define DP_EDP_CONFIGURATION_CAP            0x00d
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#define DP_MSTM_CAP			    0x021   /* 1.2 */
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#define DP_TRAINING_AUX_RD_INTERVAL         0x00e
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# define DP_MST_CAP			    (1 << 0)
77 
 
 107 
 
78 
#define DP_PSR_SUPPORT                      0x070
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#define DP_PSR_SUPPORT                      0x070   /* XXX 1.2? */
79 
# define DP_PSR_IS_SUPPORTED                1
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# define DP_PSR_IS_SUPPORTED                1
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#define DP_PSR_CAPS                         0x071
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#define DP_PSR_CAPS                         0x071   /* XXX 1.2? */
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# define DP_PSR_NO_TRAIN_ON_EXIT            1
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# define DP_PSR_NO_TRAIN_ON_EXIT            1
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# define DP_PSR_SETUP_TIME_330              (0 << 1)
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# define DP_PSR_SETUP_TIME_330              (0 << 1)
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# define DP_PSR_SETUP_TIME_55               (5 << 1)
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# define DP_PSR_SETUP_TIME_55               (5 << 1)
88 
# define DP_PSR_SETUP_TIME_0                (6 << 1)
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# define DP_PSR_SETUP_TIME_0                (6 << 1)
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# define DP_PSR_SETUP_TIME_MASK             (7 << 1)
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# define DP_PSR_SETUP_TIME_MASK             (7 << 1)
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# define DP_PSR_SETUP_TIME_SHIFT            1
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# define DP_PSR_SETUP_TIME_SHIFT            1
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- 
 
 122 
/*
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 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
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 124 
 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set.  If it was not,
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 * each port's descriptor is one byte wide.  If it was set, each port's is
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 126 
 * four bytes wide, starting with the one byte from the base info.  As of
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 * DP interop v1.1a only VGA defines additional detail.
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 128 
 */
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 129 
 
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/* offset 0 */
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#define DP_DOWNSTREAM_PORT_0		    0x80
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# define DP_DS_PORT_TYPE_MASK		    (7 << 0)
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# define DP_DS_PORT_TYPE_DP		    0
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# define DP_DS_PORT_TYPE_VGA		    1
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# define DP_DS_PORT_TYPE_DVI		    2
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# define DP_DS_PORT_TYPE_HDMI		    3
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# define DP_DS_PORT_TYPE_NON_EDID	    4
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# define DP_DS_PORT_HPD			    (1 << 3)
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/* offset 1 for VGA is maximum megapixels per second / 8 */
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/* offset 2 */
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# define DP_DS_VGA_MAX_BPC_MASK		    (3 << 0)
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 142 
# define DP_DS_VGA_8BPC			    0
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# define DP_DS_VGA_10BPC		    1
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 144 
# define DP_DS_VGA_12BPC		    2
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 145 
# define DP_DS_VGA_16BPC		    3
91 
 
 146 
 
92 
/* link configuration */
 147 
/* link configuration */
93 
#define	DP_LINK_BW_SET		            0x100
 148 
#define	DP_LINK_BW_SET		            0x100
94 
# define DP_LINK_BW_1_62		    0x06
 149 
# define DP_LINK_BW_1_62		    0x06
95 
# define DP_LINK_BW_2_7			    0x0a
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# define DP_LINK_BW_2_7			    0x0a
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# define DP_LINK_BW_5_4			    0x14
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# define DP_LINK_BW_5_4			    0x14    /* 1.2 */
97 
 
 152 
 
98 
#define DP_LANE_COUNT_SET	            0x101
 153 
#define DP_LANE_COUNT_SET	            0x101
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# define DP_LANE_COUNT_MASK		    0x0f
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# define DP_LANE_COUNT_MASK		    0x0f
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# define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)
 155 
# define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)
101 
 
 156 
 
102 
#define DP_TRAINING_PATTERN_SET	            0x102
 157 
#define DP_TRAINING_PATTERN_SET	            0x102
103 
# define DP_TRAINING_PATTERN_DISABLE	    0
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# define DP_TRAINING_PATTERN_DISABLE	    0
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# define DP_TRAINING_PATTERN_1		    1
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# define DP_TRAINING_PATTERN_1		    1
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# define DP_TRAINING_PATTERN_2		    2
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# define DP_TRAINING_PATTERN_2		    2
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# define DP_TRAINING_PATTERN_3		    3
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# define DP_TRAINING_PATTERN_3		    3	    /* 1.2 */
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# define DP_TRAINING_PATTERN_MASK	    0x3
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# define DP_TRAINING_PATTERN_MASK	    0x3
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# define DP_TRAIN_PRE_EMPHASIS_SHIFT	    3
 197 
# define DP_TRAIN_PRE_EMPHASIS_SHIFT	    3
143 
# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED  (1 << 5)
 198 
# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED  (1 << 5)
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 199 
 
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#define DP_DOWNSPREAD_CTRL		    0x107
 200 
#define DP_DOWNSPREAD_CTRL		    0x107
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 201 
# define DP_SPREAD_AMP_0_5		    (1 << 4)
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# define DP_SPREAD_AMP_0_5		    (1 << 4)
 202 
# define DP_MSA_TIMING_PAR_IGNORE_EN	    (1 << 7) /* eDP */
147 
 
 203 
 
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 204 
#define DP_MAIN_LINK_CHANNEL_CODING_SET	    0x108
- 
 
 205 
# define DP_SET_ANSI_8B10B		    (1 << 0)
- 
 
 206 
 
- 
 
 207 
#define DP_I2C_SPEED_CONTROL_STATUS	    0x109   /* DPI */
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 208 
/* bitmask as for DP_I2C_SPEED_CAP */
- 
 
 209 
 
- 
 
 210 
#define DP_EDP_CONFIGURATION_SET            0x10a   /* XXX 1.2? */
- 
 
 211 
 
- 
 
 212 
#define DP_MSTM_CTRL			    0x111   /* 1.2 */
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 213 
# define DP_MST_EN			    (1 << 0)
148 
#define DP_MAIN_LINK_CHANNEL_CODING_SET	    0x108
 214 
# define DP_UP_REQ_EN			    (1 << 1)
149 
# define DP_SET_ANSI_8B10B		    (1 << 0)
 215 
# define DP_UPSTREAM_IS_SRC		    (1 << 2)
150 
 
 216 
 
151 
#define DP_PSR_EN_CFG			    0x170
 217 
#define DP_PSR_EN_CFG			    0x170   /* XXX 1.2? */
152 
# define DP_PSR_ENABLE			    (1 << 0)
 218 
# define DP_PSR_ENABLE			    (1 << 0)
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# define DP_PSR_MAIN_LINK_ACTIVE	    (1 << 1)
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# define DP_PSR_CRC_VERIFICATION	    (1 << 2)
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 221 
# define DP_PSR_FRAME_CAPTURE		    (1 << 3)
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#define DP_SINK_COUNT			    0x200
153 
# define DP_PSR_MAIN_LINK_ACTIVE	    (1 << 1)
 224 
/* prior to 1.2 bit 7 was reserved mbz */
154 
# define DP_PSR_CRC_VERIFICATION	    (1 << 2)
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# define DP_GET_SINK_COUNT(x)		    ((((x) & 0x80) >> 1) | ((x) & 0x3f))
155 
# define DP_PSR_FRAME_CAPTURE		    (1 << 3)
 226 
# define DP_SINK_CP_READY		    (1 << 6)
156 
 
 227 
 
157 
#define DP_DEVICE_SERVICE_IRQ_VECTOR	    0x201
 228 
#define DP_DEVICE_SERVICE_IRQ_VECTOR	    0x201
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# define DP_REMOTE_CONTROL_COMMAND_PENDING  (1 << 0)
 - 
 
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# define DP_AUTOMATED_TEST_REQUEST	    (1 << 1)
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160 
# define DP_CP_IRQ			    (1 << 2)
 229 
# define DP_REMOTE_CONTROL_COMMAND_PENDING  (1 << 0)
161 
# define DP_SINK_SPECIFIC_IRQ		    (1 << 6)
 230 
# define DP_AUTOMATED_TEST_REQUEST	    (1 << 1)
162 
 
 231 
# define DP_CP_IRQ			    (1 << 2)
163 
#define DP_EDP_CONFIGURATION_SET            0x10a
 232 
# define DP_SINK_SPECIFIC_IRQ		    (1 << 6)
164 
 
 233 
 
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#define DP_TEST_RESPONSE		    0x260
 280 
#define DP_TEST_RESPONSE		    0x260
212 
# define DP_TEST_ACK			    (1 << 0)
 281 
# define DP_TEST_ACK			    (1 << 0)
213 
# define DP_TEST_NAK			    (1 << 1)
 282 
# define DP_TEST_NAK			    (1 << 1)
214 
# define DP_TEST_EDID_CHECKSUM_WRITE	    (1 << 2)
 283 
# define DP_TEST_EDID_CHECKSUM_WRITE	    (1 << 2)
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 284 
 
- 
 
 285 
#define DP_SOURCE_OUI			    0x300
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 286 
#define DP_SINK_OUI			    0x400
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 287 
#define DP_BRANCH_OUI			    0x500
215 
 
 288 
 
216 
#define DP_SET_POWER                        0x600
 289 
#define DP_SET_POWER                        0x600
217 
# define DP_SET_POWER_D0                    0x1
 290 
# define DP_SET_POWER_D0                    0x1
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218 
# define DP_SET_POWER_D3                    0x2
 291 
# define DP_SET_POWER_D3                    0x2
219 
 
 292 
 
220 
#define DP_PSR_ERROR_STATUS                 0x2006
 293 
#define DP_PSR_ERROR_STATUS                 0x2006  /* XXX 1.2? */
Line 221... Line 294...
221 
# define DP_PSR_LINK_CRC_ERROR              (1 << 0)
 294 
# define DP_PSR_LINK_CRC_ERROR              (1 << 0)
222 
# define DP_PSR_RFB_STORAGE_ERROR           (1 << 1)
 295 
# define DP_PSR_RFB_STORAGE_ERROR           (1 << 1)
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223 
 
 296 
 
224 
#define DP_PSR_ESI                          0x2007
 297 
#define DP_PSR_ESI                          0x2007  /* XXX 1.2? */
225 
# define DP_PSR_CAPS_CHANGE                 (1 << 0)
 298 
# define DP_PSR_CAPS_CHANGE                 (1 << 0)
226 
 
 299 
 
227 
#define DP_PSR_STATUS                       0x2008
 300 
#define DP_PSR_STATUS                       0x2008  /* XXX 1.2? */
228 
# define DP_PSR_SINK_INACTIVE               0
 301 
# define DP_PSR_SINK_INACTIVE               0