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Rev 1964 | Rev 2967 | ||
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Line 70... | Line 70... | ||
70 | /* 11b = Other */ |
70 | /* 11b = Other */ |
71 | # define DP_FORMAT_CONVERSION (1 << 3) |
71 | # define DP_FORMAT_CONVERSION (1 << 3) |
Line 72... | Line 72... | ||
72 | 72 | ||
Line -... | Line 73... | ||
- | 73 | #define DP_MAIN_LINK_CHANNEL_CODING 0x006 |
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73 | #define DP_MAIN_LINK_CHANNEL_CODING 0x006 |
74 | |
Line -... | Line 75... | ||
- | 75 | #define DP_EDP_CONFIGURATION_CAP 0x00d |
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- | 76 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e |
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- | 77 | ||
- | 78 | #define DP_PSR_SUPPORT 0x070 |
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- | 79 | # define DP_PSR_IS_SUPPORTED 1 |
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- | 80 | #define DP_PSR_CAPS 0x071 |
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- | 81 | # define DP_PSR_NO_TRAIN_ON_EXIT 1 |
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- | 82 | # define DP_PSR_SETUP_TIME_330 (0 << 1) |
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- | 83 | # define DP_PSR_SETUP_TIME_275 (1 << 1) |
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- | 84 | # define DP_PSR_SETUP_TIME_220 (2 << 1) |
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- | 85 | # define DP_PSR_SETUP_TIME_165 (3 << 1) |
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- | 86 | # define DP_PSR_SETUP_TIME_110 (4 << 1) |
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- | 87 | # define DP_PSR_SETUP_TIME_55 (5 << 1) |
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- | 88 | # define DP_PSR_SETUP_TIME_0 (6 << 1) |
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74 | 89 | # define DP_PSR_SETUP_TIME_MASK (7 << 1) |
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75 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e |
90 | # define DP_PSR_SETUP_TIME_SHIFT 1 |
76 | 91 | ||
77 | /* link configuration */ |
92 | /* link configuration */ |
78 | #define DP_LINK_BW_SET 0x100 |
93 | #define DP_LINK_BW_SET 0x100 |
Line 131... | Line 146... | ||
131 | # define DP_SPREAD_AMP_0_5 (1 << 4) |
146 | # define DP_SPREAD_AMP_0_5 (1 << 4) |
Line 132... | Line 147... | ||
132 | 147 | ||
133 | #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 |
148 | #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 |
Line -... | Line 149... | ||
- | 149 | # define DP_SET_ANSI_8B10B (1 << 0) |
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- | 150 | ||
- | 151 | #define DP_PSR_EN_CFG 0x170 |
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- | 152 | # define DP_PSR_ENABLE (1 << 0) |
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- | 153 | # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) |
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- | 154 | # define DP_PSR_CRC_VERIFICATION (1 << 2) |
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- | 155 | # define DP_PSR_FRAME_CAPTURE (1 << 3) |
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- | 156 | ||
- | 157 | #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 |
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- | 158 | # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) |
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- | 159 | # define DP_AUTOMATED_TEST_REQUEST (1 << 1) |
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- | 160 | # define DP_CP_IRQ (1 << 2) |
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- | 161 | # define DP_SINK_SPECIFIC_IRQ (1 << 6) |
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- | 162 | ||
134 | # define DP_SET_ANSI_8B10B (1 << 0) |
163 | #define DP_EDP_CONFIGURATION_SET 0x10a |
135 | 164 | ||
136 | #define DP_LANE0_1_STATUS 0x202 |
165 | #define DP_LANE0_1_STATUS 0x202 |
137 | #define DP_LANE2_3_STATUS 0x203 |
166 | #define DP_LANE2_3_STATUS 0x203 |
138 | # define DP_LANE_CR_DONE (1 << 0) |
167 | # define DP_LANE_CR_DONE (1 << 0) |
Line 163... | Line 192... | ||
163 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 |
192 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 |
164 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 |
193 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 |
165 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 |
194 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 |
166 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 |
195 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 |
Line -... | Line 196... | ||
- | 196 | ||
- | 197 | #define DP_TEST_REQUEST 0x218 |
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- | 198 | # define DP_TEST_LINK_TRAINING (1 << 0) |
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- | 199 | # define DP_TEST_LINK_PATTERN (1 << 1) |
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- | 200 | # define DP_TEST_LINK_EDID_READ (1 << 2) |
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- | 201 | # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ |
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- | 202 | ||
- | 203 | #define DP_TEST_LINK_RATE 0x219 |
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- | 204 | # define DP_LINK_RATE_162 (0x6) |
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- | 205 | # define DP_LINK_RATE_27 (0xa) |
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- | 206 | ||
- | 207 | #define DP_TEST_LANE_COUNT 0x220 |
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- | 208 | ||
- | 209 | #define DP_TEST_PATTERN 0x221 |
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- | 210 | ||
- | 211 | #define DP_TEST_RESPONSE 0x260 |
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- | 212 | # define DP_TEST_ACK (1 << 0) |
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- | 213 | # define DP_TEST_NAK (1 << 1) |
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- | 214 | # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) |
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167 | 215 | ||
168 | #define DP_SET_POWER 0x600 |
216 | #define DP_SET_POWER 0x600 |
169 | # define DP_SET_POWER_D0 0x1 |
217 | # define DP_SET_POWER_D0 0x1 |
Line -... | Line 218... | ||
- | 218 | # define DP_SET_POWER_D3 0x2 |
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- | 219 | ||
- | 220 | #define DP_PSR_ERROR_STATUS 0x2006 |
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- | 221 | # define DP_PSR_LINK_CRC_ERROR (1 << 0) |
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- | 222 | # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) |
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- | 223 | ||
- | 224 | #define DP_PSR_ESI 0x2007 |
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- | 225 | # define DP_PSR_CAPS_CHANGE (1 << 0) |
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- | 226 | ||
- | 227 | #define DP_PSR_STATUS 0x2008 |
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- | 228 | # define DP_PSR_SINK_INACTIVE 0 |
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- | 229 | # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 |
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- | 230 | # define DP_PSR_SINK_ACTIVE_RFB 2 |
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- | 231 | # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 |
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- | 232 | # define DP_PSR_SINK_ACTIVE_RESYNC 4 |
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- | 233 | # define DP_PSR_SINK_INTERNAL_ERROR 7 |
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170 | # define DP_SET_POWER_D3 0x2 |
234 | # define DP_PSR_SINK_STATE_MASK 0x07 |
171 | 235 | ||
172 | #define MODE_I2C_START 1 |
236 | #define MODE_I2C_START 1 |
173 | #define MODE_I2C_WRITE 2 |
237 | #define MODE_I2C_WRITE 2 |