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#ifndef _ASM_X86_MSR_H
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#ifndef _ASM_X86_MSR_H
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#define _ASM_X86_MSR_H
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#define _ASM_X86_MSR_H
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#include
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#include "msr-index.h"
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLY__
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#include
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#include
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#include
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#include
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#include
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#include
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#include
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 * constraint has different meanings. For i386, "A" means exactly
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 * constraint has different meanings. For i386, "A" means exactly
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 * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
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 * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
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 * it means rax *or* rdx.
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 * it means rax *or* rdx.
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 */
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 */
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#ifdef CONFIG_X86_64
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#ifdef CONFIG_X86_64
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/* Using 64-bit values saves one instruction clearing the high half of low */
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#define DECLARE_ARGS(val, low, high)	unsigned low, high
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#define DECLARE_ARGS(val, low, high)	unsigned long low, high
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#define EAX_EDX_VAL(val, low, high)	((low) | ((u64)(high) << 32))
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#define EAX_EDX_VAL(val, low, high)	((low) | (high) << 32)
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#define EAX_EDX_ARGS(val, low, high)	"a" (low), "d" (high)
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#define EAX_EDX_RET(val, low, high)	"=a" (low), "=d" (high)
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#define EAX_EDX_RET(val, low, high)	"=a" (low), "=d" (high)
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#else
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#else
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#define DECLARE_ARGS(val, low, high)	unsigned long long val
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#define DECLARE_ARGS(val, low, high)	unsigned long long val
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#define EAX_EDX_VAL(val, low, high)	(val)
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#define EAX_EDX_VAL(val, low, high)	(val)
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#define EAX_EDX_ARGS(val, low, high)	"A" (val)
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#define EAX_EDX_RET(val, low, high)	"=A" (val)
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#define EAX_EDX_RET(val, low, high)	"=A" (val)
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#endif
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#endif
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static inline unsigned long long native_read_msr(unsigned int msr)
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static inline unsigned long long native_read_msr(unsigned int msr)
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		       [fault] "i" (-EIO)
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		       [fault] "i" (-EIO)
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		     : "memory");
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		     : "memory");
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	return err;
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	return err;
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}
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}
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extern unsigned long long native_read_tsc(void);
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extern int rdmsr_safe_regs(u32 regs[8]);
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extern int rdmsr_safe_regs(u32 regs[8]);
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extern int wrmsr_safe_regs(u32 regs[8]);
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/**
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 * rdtsc() - returns the current TSC without ordering constraints
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 *
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 * rdtsc() returns the result of RDTSC as a 64-bit integer.  The
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 * only ordering constraint it supplies is the ordering implied by
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 * "asm volatile": it will put the RDTSC in the place you expect.  The
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 * CPU can and will speculatively execute that RDTSC, though, so the
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extern int wrmsr_safe_regs(u32 regs[8]);
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 * results can be non-monotonic if compared on different CPUs.
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 */
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static __always_inline unsigned long long __native_read_tsc(void)
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static __always_inline unsigned long long rdtsc(void)
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{
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{
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}
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}
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#define rdmsrl(msr, val)			\
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#define rdmsrl(msr, val)			\
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	((val) = native_read_msr((msr)))
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	((val) = native_read_msr((msr)))
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static inline void wrmsrl(unsigned msr, u64 val)
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{
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#define wrmsrl(msr, val)						\
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	native_write_msr(msr, (u32)val, (u32)(val >> 32));
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	native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32))
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}
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/* wrmsr with exception handling */
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/* wrmsr with exception handling */
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	*p = native_read_msr_safe(msr, &err);
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	*p = native_read_msr_safe(msr, &err);
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	return err;
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	return err;
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}
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#define rdtscl(low)						\
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	((low) = (u32)__native_read_tsc())
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#define rdtscll(val)						\
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	((val) = __native_read_tsc())
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}
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#define rdpmc(counter, low, high)			\
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#define rdpmc(counter, low, high)			\
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do {							\
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do {							\
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	u64 _l = native_read_pmc((counter));		\
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	u64 _l = native_read_pmc((counter));		\
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	(low)  = (u32)_l;				\
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	(low)  = (u32)_l;				\
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	(high) = (u32)(_l >> 32);			\
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	(high) = (u32)(_l >> 32);			\
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} while (0)
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#define rdpmcl(counter, val) ((val) = native_read_pmc(counter))
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#define rdtscp(low, high, aux)					\
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do {                                                            \
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	unsigned long long _val = native_read_tscp(&(aux));     \
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	(low) = (u32)_val;                                      \
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	(high) = (u32)(_val >> 32);                             \
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} while (0)
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} while (0)
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#define rdpmcl(counter, val) ((val) = native_read_pmc(counter))
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#endif	/* !CONFIG_PARAVIRT */
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#define rdtscpll(val, aux) (val) = native_read_tscp(&(aux))
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/*
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 * 64-bit version of wrmsr_safe():
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 */
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#endif	/* !CONFIG_PARAVIRT */
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static inline int wrmsrl_safe(u32 msr, u64 val)