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| 1 | #ifndef _ASM_X86_MSR_INDEX_H |
1 | #ifndef _ASM_X86_MSR_INDEX_H |
| 2 | #define _ASM_X86_MSR_INDEX_H |
2 | #define _ASM_X86_MSR_INDEX_H |
| Line -... | Line 3... | ||
| - | 3 | ||
| 3 | 4 | /* |
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| - | 5 | * CPU model specific register (MSR) numbers. |
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| - | 6 | * |
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| - | 7 | * Do not add new entries to this file unless the definitions are shared |
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| - | 8 | * between multiple compilation units. |
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| Line 4... | Line 9... | ||
| 4 | /* CPU model specific register (MSR) numbers */ |
9 | */ |
| 5 | 10 | ||
| 6 | /* x86-64 specific MSRs */ |
11 | /* x86-64 specific MSRs */ |
| 7 | #define MSR_EFER 0xc0000080 /* extended feature register */ |
12 | #define MSR_EFER 0xc0000080 /* extended feature register */ |
| Line 160... | Line 165... | ||
| 160 | #define MSR_PKG_C2_RESIDENCY 0x0000060d |
165 | #define MSR_PKG_C2_RESIDENCY 0x0000060d |
| 161 | #define MSR_PKG_C8_RESIDENCY 0x00000630 |
166 | #define MSR_PKG_C8_RESIDENCY 0x00000630 |
| 162 | #define MSR_PKG_C9_RESIDENCY 0x00000631 |
167 | #define MSR_PKG_C9_RESIDENCY 0x00000631 |
| 163 | #define MSR_PKG_C10_RESIDENCY 0x00000632 |
168 | #define MSR_PKG_C10_RESIDENCY 0x00000632 |
| Line -... | Line 169... | ||
| - | 169 | ||
| - | 170 | /* Interrupt Response Limit */ |
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| - | 171 | #define MSR_PKGC3_IRTL 0x0000060a |
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| - | 172 | #define MSR_PKGC6_IRTL 0x0000060b |
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| - | 173 | #define MSR_PKGC7_IRTL 0x0000060c |
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| - | 174 | #define MSR_PKGC8_IRTL 0x00000633 |
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| - | 175 | #define MSR_PKGC9_IRTL 0x00000634 |
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| - | 176 | #define MSR_PKGC10_IRTL 0x00000635 |
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| 164 | 177 | ||
| Line 165... | Line 178... | ||
| 165 | /* Run Time Average Power Limiting (RAPL) Interface */ |
178 | /* Run Time Average Power Limiting (RAPL) Interface */ |
| Line 166... | Line 179... | ||
| 166 | 179 | ||
| Line 183... | Line 196... | ||
| 183 | 196 | ||
| 184 | #define MSR_PP1_POWER_LIMIT 0x00000640 |
197 | #define MSR_PP1_POWER_LIMIT 0x00000640 |
| 185 | #define MSR_PP1_ENERGY_STATUS 0x00000641 |
198 | #define MSR_PP1_ENERGY_STATUS 0x00000641 |
| Line -... | Line 199... | ||
| - | 199 | #define MSR_PP1_POLICY 0x00000642 |
|
| 186 | #define MSR_PP1_POLICY 0x00000642 |
200 | |
| 187 | 201 | /* Config TDP MSRs */ |
|
| 188 | #define MSR_CONFIG_TDP_NOMINAL 0x00000648 |
202 | #define MSR_CONFIG_TDP_NOMINAL 0x00000648 |
| 189 | #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 |
203 | #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 |
| 190 | #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A |
204 | #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A |
| Line 203... | Line 217... | ||
| 203 | 217 | ||
| 204 | #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 |
218 | #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 |
| 205 | #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 |
219 | #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 |
| Line 206... | Line -... | ||
| 206 | #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 |
- | |
| 207 | - | ||
| 208 | /* Config TDP MSRs */ |
- | |
| 209 | #define MSR_CONFIG_TDP_NOMINAL 0x00000648 |
- | |
| 210 | #define MSR_CONFIG_TDP_LEVEL1 0x00000649 |
- | |
| 211 | #define MSR_CONFIG_TDP_LEVEL2 0x0000064A |
- | |
| 212 | #define MSR_CONFIG_TDP_CONTROL 0x0000064B |
- | |
| 213 | #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C |
220 | #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 |
| 214 | 221 | ||
| 215 | /* Hardware P state interface */ |
222 | /* Hardware P state interface */ |
| 216 | #define MSR_PPERF 0x0000064e |
223 | #define MSR_PPERF 0x0000064e |
| 217 | #define MSR_PERF_LIMIT_REASONS 0x0000064f |
224 | #define MSR_PERF_LIMIT_REASONS 0x0000064f |
| Line 228... | Line 235... | ||
| 228 | #define HWP_ACTIVITY_WINDOW_BIT (1<<9) |
235 | #define HWP_ACTIVITY_WINDOW_BIT (1<<9) |
| 229 | #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) |
236 | #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) |
| 230 | #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) |
237 | #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) |
| Line 231... | Line 238... | ||
| 231 | 238 | ||
| 232 | /* IA32_HWP_CAPABILITIES */ |
239 | /* IA32_HWP_CAPABILITIES */ |
| 233 | #define HWP_HIGHEST_PERF(x) (x & 0xff) |
240 | #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) |
| 234 | #define HWP_GUARANTEED_PERF(x) ((x & (0xff << 8)) >>8) |
241 | #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) |
| 235 | #define HWP_MOSTEFFICIENT_PERF(x) ((x & (0xff << 16)) >>16) |
242 | #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) |
| Line 236... | Line 243... | ||
| 236 | #define HWP_LOWEST_PERF(x) ((x & (0xff << 24)) >>24) |
243 | #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) |
| 237 | 244 | ||
| 238 | /* IA32_HWP_REQUEST */ |
245 | /* IA32_HWP_REQUEST */ |
| 239 | #define HWP_MIN_PERF(x) (x & 0xff) |
246 | #define HWP_MIN_PERF(x) (x & 0xff) |