WebSVN – Kolibri OS – Diff – /drivers/ethernet/pcnet32.asm


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                  ;;
;; Copyright (C) KolibriOS team 2004-2015. All rights reserved.     ;;
;; Distributed under terms of the GNU General Public License        ;;
;;                                                                  ;;
;;  AMD PCnet driver for KolibriOS                                  ;;
;;                                                                  ;;
;;  By hidnplayr & clevermouse                                      ;;
;;                                                                  ;;
;;  Based on the PCnet32 driver for MenuetOS, by Jarek Pelczar      ;;
;;                                                                  ;;
;;          GNU GENERAL PUBLIC LICENSE                              ;;
;;             Version 2, June 1991                                 ;;
;;                                                                  ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
format PE DLL native
entry START
 
        CURRENT_API             = 0x0200
        COMPATIBLE_API          = 0x0100
        API_VERSION             = (COMPATIBLE_API shl 16) + CURRENT_API
 
        MAX_DEVICES             = 16
 
        __DEBUG__               = 1
        __DEBUG_LEVEL__         = 2             ; 1 = verbose, 2 = errors only
 
        TX_RING_SIZE            = 4
        RX_RING_SIZE            = 4
 
section '.flat' readable writable executable
 
include '../struct.inc'
include '../macros.inc'
include '../proc32.inc'
include '../fdo.inc'
include '../netdrv.inc'
 
 
        PORT_AUI                = 0x00
        PORT_10BT               = 0x01
        PORT_GPSI               = 0x02
        PORT_MII                = 0x03
        PORT_PORTSEL            = 0x03
        PORT_ASEL               = 0x04
        PORT_100                = 0x40
        PORT_FD                 = 0x80
 
        DMA_MASK                = 0xffffffff
 
        LOG_TX_BUFFERS          = 2             ; FIXME
        LOG_RX_BUFFERS          = 2
 
        TX_RING_MOD_MASK        = (TX_RING_SIZE-1)
        TX_RING_LEN_BITS        = (LOG_TX_BUFFERS shl 12)
 
        RX_RING_MOD_MASK        = (RX_RING_SIZE-1)
        RX_RING_LEN_BITS        = (LOG_RX_BUFFERS shl 4)
 
        PKT_BUF_SZ              = 1544
 
        WIO_RDP                 = 0x10
        WIO_RAP                 = 0x12
        WIO_RESET               = 0x14
        WIO_BDP                 = 0x16
 
        DWIO_RDP                = 0x10
        DWIO_RAP                = 0x14
        DWIO_RESET              = 0x18
        DWIO_BDP                = 0x1C
 
; CSR registers
 
        CSR_CSR                 = 0x00
        CSR_IAB0                = 0x01
        CSR_IAB1                = 0x02
        CSR_IMR                 = 0x03
        CSR_TFEAT               = 0x04
        CSR_EXTCTL1             = 0x05
        CSR_DTBLLEN             = 0x06
        CSR_EXTCTL2             = 0x07
        CSR_MAR0                = 0x08
        CSR_MAR1                = 0x09
        CSR_MAR2                = 0x0A
        CSR_MAR3                = 0x0B
        CSR_PAR0                = 0x0C
        CSR_PAR1                = 0x0D
        CSR_PAR2                = 0x0E
        CSR_MODE                = 0x0F
        CSR_RXADDR0             = 0x18
        CSR_RXADDR1             = 0x19
        CSR_TXADDR0             = 0x1E
        CSR_TXADDR1             = 0x1F
        CSR_TXPOLL              = 0x2F
        CSR_RXPOLL              = 0x31
        CSR_RXRINGLEN           = 0x4C
        CSR_TXRINGLEN           = 0x4E
        CSR_DMACTL              = 0x50
        CSR_BUSTIMER            = 0x52
        CSR_MEMERRTIMEO         = 0x64
        CSR_ONNOWMISC           = 0x74
        CSR_ADVFEAT             = 0x7A
        CSR_MACCFG              = 0x7D
        CSR_CHIPID0             = 0x58
        CSR_CHIPID1             = 0x59
 
; Control and Status Register (CSR0)
 
        CSR_INIT                = 0x0001 ;1 shl 0
        CSR_START               = 0x0002 ;1 shl 1
        CSR_STOP                = 0x0004 ;1 shl 2
        CSR_TX                  = 0x0008 ;1 shl 3
        CSR_TXON                = 0x0010 ;1 shl 4
        CSR_RXON                = 0x0020 ;1 shl 5
        CSR_INTEN               = 0x0040 ;1 shl 6
        CSR_INTR                = 0x0080 ;1 shl 7
        CSR_IDONE               = 0x0100 ;1 shl 8
        CSR_TINT                = 0x0200 ;1 shl 9
        CSR_RINT                = 0x0400 ;1 shl 10
        CSR_MERR                = 0x0800 ;1 shl 11
        CSR_MISS                = 0x1000 ;1 shl 12
        CSR_CERR                = 0x2000 ;1 shl 13
 
; Interrupt masks and deferral control (CSR3)
 
        IMR_BSWAP               = 0x0004
        IMR_ENMBA               = 0x0008  ; enable modified backoff alg
        IMR_DXMT2PD             = 0x0010
        IMR_LAPPEN              = 0x0020  ; lookahead packet processing enb
        IMR_DXSUFLO             = 0x0040  ; disable TX stop on underflow
        IMR_IDONE               = 0x0100
        IMR_TINT                = 0x0200
        IMR_RINT                = 0x0400
        IMR_MERR                = 0x0800
        IMR_MISS                = 0x1000
 
        ; Masked interrupts will be disabled.
        IMR                     = 0 ;IMR_IDONE ;or IMR_TINT or IMR_RINT or IMR_MERR or IMR_MISS
 
; Test and features control (CSR4)
 
        TFEAT_TXSTRTMASK        = 0x0004
        TFEAT_TXSTRT            = 0x0008
        TFEAT_RXCCOFLOWM        = 0x0010  ; Rx collision counter oflow
        TFEAT_RXCCOFLOW         = 0x0020
        TFEAT_UINT              = 0x0040
        TFEAT_UINTREQ           = 0x0080
        TFEAT_MISSOFLOWM        = 0x0100
        TFEAT_MISSOFLOW         = 0x0200
        TFEAT_STRIP_FCS         = 0x0400
        TFEAT_PAD_TX            = 0x0800
        TFEAT_TXDPOLL           = 0x1000
        TFEAT_DMAPLUS           = 0x4000
 
; Extended control and interrupt 1 (CSR5)
 
        EXTCTL1_SPND            = 0x0001  ; suspend
        EXTCTL1_MPMODE          = 0x0002  ; magic packet mode
        EXTCTL1_MPENB           = 0x0004  ; magic packet enable
        EXTCTL1_MPINTEN         = 0x0008  ; magic packet interrupt enable
        EXTCTL1_MPINT           = 0x0010  ; magic packet interrupt
        EXTCTL1_MPPLBA          = 0x0020  ; magic packet phys. logical bcast
        EXTCTL1_EXDEFEN         = 0x0040  ; excessive deferral interrupt enb.
        EXTCTL1_EXDEF           = 0x0080  ; excessive deferral interrupt
        EXTCTL1_SINTEN          = 0x0400  ; system interrupt enable
        EXTCTL1_SINT            = 0x0800  ; system interrupt
        EXTCTL1_LTINTEN         = 0x4000  ; last TX interrupt enb
        EXTCTL1_TXOKINTD        = 0x8000  ; TX OK interrupt disable
 
; RX/TX descriptor len (CSR6)
 
        DTBLLEN_RLEN            = 0x0F00
        DTBLLEN_TLEN            = 0xF000
 
; Extended control and interrupt 2 (CSR7)
 
        EXTCTL2_MIIPDTINTE      = 0x0001
        EXTCTL2_MIIPDTINT       = 0x0002
        EXTCTL2_MCCIINTE        = 0x0004
        EXTCTL2_MCCIINT         = 0x0008
        EXTCTL2_MCCINTE         = 0x0010
        EXTCTL2_MCCINT          = 0x0020
        EXTCTL2_MAPINTE         = 0x0040
        EXTCTL2_MAPINT          = 0x0080
        EXTCTL2_MREINTE         = 0x0100
        EXTCTL2_MREINT          = 0x0200
        EXTCTL2_STINTE          = 0x0400
        EXTCTL2_STINT           = 0x0800
        EXTCTL2_RXDPOLL         = 0x1000
        EXTCTL2_RDMD            = 0x2000
        EXTCTL2_RXFRTG          = 0x4000
        EXTCTL2_FASTSPNDE       = 0x8000
 
; Mode (CSR15)
 
        MODE_RXD                = 0x0001  ; RX disable
        MODE_TXD                = 0x0002  ; TX disable
        MODE_LOOP               = 0x0004  ; loopback enable
        MODE_TXCRCD             = 0x0008
        MODE_FORCECOLL          = 0x0010
        MODE_RETRYD             = 0x0020
        MODE_INTLOOP            = 0x0040
        MODE_PORTSEL            = 0x0180
        MODE_RXVPAD             = 0x2000
        MODE_RXNOBROAD          = 0x4000
        MODE_PROMISC            = 0x8000
 
; BCR (Bus Control Registers)
 
        BCR_MMRA                = 0x00    ; Master Mode Read Active
        BCR_MMW                 = 0x01    ; Master Mode Write Active
        BCR_MISCCFG             = 0x02
        BCR_LED0                = 0x04
        BCR_LED1                = 0x05
        BCR_LED2                = 0x06
        BCR_LED3                = 0x07
        BCR_DUPLEX              = 0x09
        BCR_BUSCTL              = 0x12
        BCR_EECTL               = 0x13
        BCR_SSTYLE              = 0x14
        BCR_PCILAT              = 0x16
        BCR_PCISUBVENID         = 0x17
        BCR_PCISUBSYSID         = 0x18
        BCR_SRAMSIZE            = 0x19
        BCR_SRAMBOUND           = 0x1A
        BCR_SRAMCTL             = 0x1B
        BCR_MIICTL              = 0x20
        BCR_MIIADDR             = 0x21
        BCR_MIIDATA             = 0x22
        BCR_PCIVENID            = 0x23
        BCR_PCIPCAP             = 0x24
        BCR_DATA0               = 0x25
        BCR_DATA1               = 0x26
        BCR_DATA2               = 0x27
        BCR_DATA3               = 0x28
        BCR_DATA4               = 0x29
        BCR_DATA5               = 0x2A
        BCR_DATA6               = 0x2B
        BCR_DATA7               = 0x2C
        BCR_ONNOWPAT0           = 0x2D
        BCR_ONNOWPAT1           = 0x2E
        BCR_ONNOWPAT2           = 0x2F
        BCR_PHYSEL              = 0x31
 
; RX status register
 
        RXSTAT_BPE              = 0x0080        ; bus parity error
        RXSTAT_ENP              = 0x0100        ; end of packet
        RXSTAT_STP              = 0x0200        ; start of packet
        RXSTAT_BUFF             = 0x0400        ; buffer error
        RXSTAT_CRC              = 0x0800        ; CRC error
        RXSTAT_OFLOW            = 0x1000        ; rx overrun
        RXSTAT_FRAM             = 0x2000        ; framing error
        RXSTAT_ERR              = 0x4000        ; error summary
        RXSTAT_OWN              = 0x8000
 
; TX status register
 
        TXSTAT_TRC              = 0x0000000F    ; transmit retries
        TXSTAT_RTRY             = 0x04000000    ; retry
        TXSTAT_LCAR             = 0x08000000    ; lost carrier
        TXSTAT_LCOL             = 0x10000000    ; late collision
        TXSTAT_EXDEF            = 0x20000000    ; excessive deferrals
        TXSTAT_UFLOW            = 0x40000000    ; transmit underrun
        TXSTAT_BUFF             = 0x80000000    ; buffer error
 
        TXCTL_OWN               = 0x8000
        TXCTL_ERR               = 0x4000        ; error summary
        TXCTL_ADD_FCS           = 0x2000        ; add FCS to pkt
        TXCTL_MORE_LTINT        = 0x1000
        TXCTL_ONE               = 0x0800
        TXCTL_DEF               = 0x0400
        TXCTL_STP               = 0x0200
        TXCTL_ENP               = 0x0100
        TXCTL_BPE               = 0x0080
 
        TXCTL_MBO               = 0x0000F000
        TXCTL_BUFSZ             = 0x00000FFF
 
        MAX_PHYS                = 32
 
 
struct  device          ETH_DEVICE
 
        rb 0x100-($ and 0xff)   ; align 256
 
; Pcnet configuration structure
        mode            dw ?
        tlen_rlen       dw ?
        phys_addr       dp ?
        reserved        dw ?
        filter          dq ?
        rx_ring_phys    dd ?
        tx_ring_phys    dd ?
; end of pcnet config struct
 
        rb 0x100-($ and 0xff)   ; align 256
 
        rx_ring         rb RX_RING_SIZE * sizeof.descriptor
 
        rb 0x100-($ and 0xff)   ; align 256
 
        tx_ring         rb TX_RING_SIZE * sizeof.descriptor
 
        cur_rx          db ?
        cur_tx          db ?
        last_tx         db ?
        options         dd ?
        full_duplex     db ?
        chip_version    dw ?
        mii             db ?
        ltint           db ?
        dxsuflo         db ?
        fset            db ?
        fdx             db ?
 
        io_addr         dd ?
        irq_line        db ?
        pci_bus         dd ?
        pci_dev         dd ?
 
        phy             dw ?
 
        read_csr        dd ?
        write_csr       dd ?
        read_bcr        dd ?
        write_bcr       dd ?
        read_rap        dd ?
        write_rap       dd ?
        sw_reset        dd ?
 
ends
 
struct  descriptor
 
        base            dd ?
        length          dw ?
        status          dw ?
        msg_length      dw ?
        misc            dw ?
        virtual         dd ?
 
ends
 
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                        ;;
;; proc START             ;;
;;                        ;;
;; (standard driver proc) ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
proc START c, reason:dword, cmdline:dword
 
        cmp     [reason], DRV_ENTRY
        jne     .fail
 
        DEBUGF  2,"Loading driver\n"
        invoke  RegService, my_service, service_proc
        ret
 
  .fail:
        xor eax, eax
        ret
 
endp
 
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                        ;;
;; proc SERVICE_PROC      ;;
;;                        ;;
;; (standard driver proc) ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
proc service_proc stdcall, ioctl:dword
 
        mov     edx, [ioctl]
        mov     eax, [edx + IOCTL.io_code]
 
;------------------------------------------------------
 
        cmp     eax, 0 ;SRV_GETVERSION
        jne     @F
 
        cmp     [edx + IOCTL.out_size], 4
        jb      .fail
        mov     eax, [edx + IOCTL.output]
        mov     [eax], dword API_VERSION
 
        xor     eax, eax
        ret
 
;------------------------------------------------------
  @@:
        cmp     eax, 1 ;SRV_HOOK
        jne     .fail
 
        cmp     [edx + IOCTL.inp_size], 3               ; Data input must be at least 3 bytes
        jb      .fail
 
        mov     eax, [edx + IOCTL.input]
        cmp     byte[eax], 1                            ; 1 means device number and bus number (pci) are given
        jne     .fail                                   ; other types arent supported for this card yet
 
; check if the device is already listed
 
        mov     ecx, [devices]
        test    ecx, ecx
        jz      .firstdevice
 
        mov     esi, device_list
;        mov     eax, [edx + IOCTL.input]                ; get the pci bus and device numbers
        mov     ax, [eax+1]                             ;
  .nextdevice:
        mov     ebx, [esi]
        cmp     al, byte[ebx + device.pci_bus]
        jne     @f
        cmp     ah, byte[ebx + device.pci_dev]
        je      .find_devicenum                         ; Device is already loaded, let's find it's device number
       @@:
        add     esi, 4
        loop    .nextdevice
 
; This device doesnt have its own eth_device structure yet, lets create one
 
  .firstdevice:
        cmp     [devices], MAX_DEVICES                  ; First check if the driver can handle one more card
        jae     .fail
 
        allocate_and_clear ebx, sizeof.device, .fail
 
; Fill in the direct call addresses into the struct
 
        mov     [ebx + device.reset], reset
        mov     [ebx + device.transmit], transmit
        mov     [ebx + device.unload], unload
        mov     [ebx + device.name], my_service
 
; save the pci bus and device numbers
 
        mov     eax, [edx + IOCTL.input]
        movzx   ecx, byte[eax+1]
        mov     [ebx + device.pci_bus], ecx
        movzx   ecx, byte[eax+2]
        mov     [ebx + device.pci_dev], ecx
 
; Now, it's time to find the base io addres of the PCI device
 
        stdcall PCI_find_io, [ebx + device.pci_bus], [ebx + device.pci_dev]
        mov     [ebx + device.io_addr], eax
 
; We've found the io address, find IRQ now
 
        invoke  PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.interrupt_line
        mov     [ebx + device.irq_line], al
 
        DEBUGF  1,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
        [ebx + device.pci_dev]:1,[ebx + device.pci_bus]:1,[ebx + device.irq_line]:1,[ebx + device.io_addr]:4
 
; Ok, the eth_device structure is ready, let's probe the device
; Because initialization fires IRQ, IRQ handler must be aware of this device
        mov     eax, [devices]                                          ; Add the device structure to our device list
        mov     [device_list+4*eax], ebx                                ; (IRQ handler uses this list to find device)
        inc     [devices]                                               ;
 
        call    probe                                                   ; this function will output in eax
        test    eax, eax
        jnz     .destroy                                                ; If an error occured, exit
 
        mov     [ebx + device.type], NET_TYPE_ETH
        invoke  NetRegDev
        cmp     eax, -1
        je      .destroy
 
        ret
 
; If the device was already loaded, find the device number and return it in eax
 
  .find_devicenum:
        DEBUGF  1,"Trying to find device number of already registered device\n"
        invoke  NetPtrToNum                                             ; This kernel procedure converts a pointer to device struct in ebx
                                                                        ; into a device number in edi
        mov     eax, edi                                                ; Application wants it in eax instead
        DEBUGF  1,"Kernel says: %u\n", eax
        ret
 
; If an error occured, remove all allocated data and exit (returning -1 in eax)
 
  .destroy:
        ; todo: reset device into virgin state
        add     eax, NET_BUFF.data
        dec     [devices]
  .err:
        DEBUGF  2,"Error, removing all data !\n"
        invoke  KernelFree, ebx
 
  .fail:
        or      eax, -1
        ret
 
;------------------------------------------------------
endp
 
 
;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;
;;                                                                        ;;
;;        Actual Hardware dependent code starts here                      ;;
;;                                                                        ;;
;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;
 
align 4
unload:
        ; TODO: (in this particular order)
        ;
        ; - Stop the device
        ; - Detach int handler
        ; - Remove device from local list (device_list)
        ; - call unregister function in kernel
        ; - Remove all allocated structures and buffers the card used
 
        or      eax, -1
        ret
 
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;;  probe: enables the device (if it really is a PCnet device)
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
probe:
 
        mov     edx, [ebx + device.io_addr]
 
        call    wio_reset
 
        xor     ecx, ecx
        call    wio_read_csr
        cmp     eax, 4
        jne     .try_dwio
 
        ; Try Word I/O
        mov     ax, 88
        add     edx, WIO_RAP
        out     dx, ax
        nop
        nop
        in      ax, dx
        sub     edx, WIO_RAP
        cmp     ax, 88
        jne     .try_dwio
 
        call    switch_to_wio
 
        jmp     .L1
 
  .try_dwio:
        call    dwio_reset
 
        xor     ecx, ecx
        call    dwio_read_csr
        cmp     eax, 4
        jne     .no_dev
 
        ; Try Dword I/O
        add     edx, DWIO_RAP
        mov     eax, 88
        out     dx, eax
        nop
        nop
        in      eax, dx
        sub     edx, DWIO_RAP
        and     eax, 0xffff
        cmp     eax, 88
        jne     .no_dev
 
        call    switch_to_dwio
 
        jmp     .L1
 
  .no_dev:
        DEBUGF  2,"device not found!\n"
        mov     eax, 1
        ret
 
  .L1:
        mov     ecx, CSR_CHIPID0
        call    [ebx + device.read_csr]
 
        mov     esi, eax
        shr     esi, 12
 
        and     ax, 0xfff
        cmp     ax, 3
        jne     .no_dev
 
        mov     ecx, CSR_CHIPID1
        call    [ebx + device.read_csr]
        shl     eax, 4
        or      eax, esi
        mov     [ebx + device.chip_version], ax
 
        mov     [ebx + device.fdx], 0
        mov     [ebx + device.mii], 0
        mov     [ebx + device.fset], 0
        mov     [ebx + device.dxsuflo], 0
        mov     [ebx + device.ltint], 0
 
        cmp     ax, 0x2420
        je      .L2
        cmp     ax, 0x2430
        je      .L2
 
        mov     [ebx + device.fdx], 1
 
        cmp     ax, 0x2621
        je      .L4
        cmp     ax, 0x2623
        je      .L5
        cmp     ax, 0x2624
        je      .L6
        cmp     ax, 0x2625
        je      .L7
        cmp     ax, 0x2626
        je      .L8
        cmp     ax, 0x2627
        je      .L9
 
        DEBUGF  2,"Invalid chip rev\n"
        jmp     .no_dev
  .L2:
        mov     [ebx + device.name], device_l2
        jmp     .L10
  .L4:
        mov     [ebx + device.name], device_l4
;        mov     [ebx + device.fdx], 1
        jmp     .L10
  .L5:
        mov     [ebx + device.name], device_l5
;        mov     [ebx + device.fdx], 1
        mov     [ebx + device.mii], 1
        mov     [ebx + device.fset], 1
        mov     [ebx + device.ltint], 1
        jmp     .L10
  .L6:
        mov     [ebx + device.name], device_l6
;        mov     [ebx + device.fdx], 1
        mov     [ebx + device.mii], 1
        mov     [ebx + device.fset], 1
        jmp     .L10
  .L7:
        mov     [ebx + device.name], device_l7
;        mov     [ebx + device.fdx], 1
        mov     [ebx + device.mii], 1
        jmp     .L10
  .L8:
        mov     [ebx + device.name], device_l8
;        mov     [ebx + device.fdx], 1
        mov     ecx, CSR_RXPOLL
        call    dword [ebx + device.read_bcr]
        call    dword [ebx + device.write_bcr]
        jmp     .L10
  .L9:
        mov     [ebx + device.name], device_l9
;        mov     [ebx + device.fdx], 1
        mov     [ebx + device.mii], 1
  .L10:
        DEBUGF  1,"device name: %s\n", [ebx + device.name]
 
        cmp     [ebx + device.fset], 1
        jne     .L11
        mov     ecx, BCR_BUSCTL
        call    [ebx + device.read_bcr]
        or      eax, 0x800
        call    [ebx + device.write_bcr]
 
        mov     ecx, CSR_DMACTL
;        call    [ebx + device.read_csr]
 
 
        mov     eax, 0xc00
        call    [ebx + device.write_csr]
 
        mov     [ebx + device.dxsuflo],1
        mov     [ebx + device.ltint],1
  .L11:
 
; Make the device a bus master
        invoke  PciRead32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command
        or      al, PCI_CMD_MASTER
        invoke  PciWrite32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command, eax
 
        mov     [ebx + device.options], PORT_ASEL
        mov     [ebx + device.mode], MODE_RXD + MODE_TXD     ; disable receive and transmit
        mov     [ebx + device.tlen_rlen], (TX_RING_LEN_BITS or RX_RING_LEN_BITS)
 
        mov     dword[ebx + device.filter], 0
        mov     dword[ebx + device.filter+4], 0
 
align 4
reset:
 
; attach int handler
 
        movzx   eax, [ebx + device.irq_line]
        DEBUGF  1,"Attaching int handler to irq %x\n", eax:1
        invoke  AttachIntHandler, eax, int_handler, ebx
        test    eax, eax
        jnz     @f
        DEBUGF  2,"Could not attach int handler!\n"
        or      eax, -1
        ret
  @@:
 
        mov     edx, [ebx + device.io_addr]
        call    [ebx + device.sw_reset]
 
        ; Switch pcnet32 to 32bit mode
        mov     ecx, BCR_SSTYLE
        mov     eax, 2
        call    [ebx + device.write_bcr]
 
        ; set/reset autoselect bit
        mov     ecx, BCR_MISCCFG
        call    [ebx + device.read_bcr]
        and     eax, not 2
        test    [ebx + device.options], PORT_ASEL
        jz      @f
        or      eax, 2
  @@:
        call    [ebx + device.write_bcr]
 
        ; Handle full duplex setting
        cmp     byte [ebx + device.full_duplex], 0
        je      .duplex_ok
        mov     ecx, BCR_DUPLEX
        call    [ebx + device.read_bcr]
        and     eax, not 3
        test    [ebx + device.options], PORT_FD
        jz      @f
        or      eax, 1
        cmp     [ebx + device.options], PORT_FD or PORT_AUI
        jne     .set_duplex
        or      eax, 2
        jmp     .set_duplex
  @@:
        test    [ebx + device.options], PORT_ASEL
        jz      .set_duplex
        cmp     [ebx + device.chip_version], 0x2627
        jne     .set_duplex
        or      eax, 3
  .set_duplex:
        mov     ecx, BCR_DUPLEX
        call    [ebx + device.write_bcr]
  .duplex_ok:
 
        ; set/reset GPSI bit in test register
        mov     ecx, 124
        call    [ebx + device.read_csr]
        mov     ecx, [ebx + device.options]
        and     ecx, PORT_PORTSEL
        cmp     ecx, PORT_GPSI
        jne     @f
        or      eax, 0x10
  @@:
        call    [ebx + device.write_csr]
        cmp     [ebx + device.mii], 0
        je      .L6
        test    [ebx + device.options], PORT_ASEL
        jnz     .L6
        mov     ecx, BCR_MIICTL
        call    [ebx + device.read_bcr]
        and     eax, not 0x38
        test    [ebx + device.options], PORT_FD
        jz      @f
        or      eax, 0x10
  @@:
        test    [ebx + device.options], PORT_100
        jz      @f
        or      eax, 0x08
  @@:
        call    [ebx + device.write_bcr]
        jmp     .L9
  .L6:
        test    [ebx + device.options], PORT_ASEL
        jz      .L9
        mov     ecx, BCR_MIICTL
        DEBUGF  1,"ASEL, enable auto-negotiation\n"
        call    [ebx + device.read_bcr]
        and     eax, not 0x98
        or      eax, 0x20
        call    [ebx + device.write_bcr]
  .L9:
        cmp     [ebx + device.ltint], 0
        je      @f
        mov     ecx, 5
        call    [ebx + device.read_csr]
        or      eax, (1 shl 14)
        call    [ebx + device.write_csr]
  @@:
        mov     eax, [ebx + device.options]
        and     eax, PORT_PORTSEL
        shl     eax, 7
        mov     [ebx + device.mode], ax
        mov     dword [ebx + device.filter], -1
        mov     dword [ebx + device.filter+4], -1
 
 
 
;-----------------------------
 
        test    [ebx + device.mii], 1
        jz      .no_mii
 
        mov     [ebx + device.phy], 0
 
  .mii_loop:
        mov     ecx, MII_PHYSID1
        call    mdio_read
        cmp     ax, 0xffff
        je      .next
 
        DEBUGF  1, "0x%x\n", ax
 
        mov     ecx, MII_PHYSID2
        call    mdio_read
        cmp     ax, 0xffff
        je      .next
 
        DEBUGF  1, "0x%x\n", ax
 
        jmp     .got_phy
 
        cmp     [ebx + device.phy], 31
        jne     .next
        mov     ax, [ebx + device.chip_version]
        inc     ax
        and     ax, 0xfffe
        cmp     ax, 0x2624              ; 79c971 & 79c972 have phantom phy at id 31
        je      .got_phy
 
  .next:
        inc     [ebx + device.phy]
        cmp     [ebx + device.phy], MAX_PHYS
        jb      .mii_loop
 
        DEBUGF  2, "No PHY found!\n"
        or      eax, -1
        ret
 
  .got_phy:
        DEBUGF  1, "Found PHY at 0x%x\n", [ebx + device.phy]:4
 
  .no_mii:
 
;-----------------------------------------------
 
        call    read_mac
 
        lea     esi, [ebx + device.mac]
        lea     edi, [ebx + device.phys_addr]
        movsd
        movsw
 
        call    init_ring
        test    eax, eax
        jnz     .fail
 
        mov     edx, [ebx + device.io_addr]   ; init ring destroys edx
 
        lea     eax, [ebx + device.mode]
        invoke  GetPhysAddr
        push    eax
        and     eax, 0xffff
        mov     ecx, 1
        call    [ebx + device.write_csr]
        pop     eax
        shr     eax, 16
        mov     ecx, 2
        call    [ebx + device.write_csr]
 
        mov     ecx, 4
        mov     eax, 0x0915
        call    [ebx + device.write_csr]
 
; Set the interrupt mask
        mov     ecx, CSR_IMR
        mov     eax, IMR
        call    [ebx + device.write_csr]
 
; Initialise the device
        xor     ecx, ecx
        mov     eax, CSR_INIT
        call    [ebx + device.write_csr]
 
        mov     esi, 100
;        xor     ecx, ecx
  @@:
        call    [ebx + device.read_csr]
        test    ax, CSR_IDONE
        jnz     @f
 
        dec     esi
        jnz     @r
        DEBUGF  2,"Initialize timeout!\n"
  @@:
 
; Start the device and enable interrupts
        xor     ecx, ecx
        mov     eax, CSR_START + CSR_INTEN
        call    [ebx + device.write_csr]
 
; Set the mtu, kernel will be able to send now
        mov     [ebx + device.mtu], 1514
 
; get link status
        mov     [ebx + device.state], ETH_LINK_UNKNOWN
 
        call    check_media
 
        DEBUGF  1,"reset complete\n"
        xor     eax, eax
  .fail:
        ret
 
 
align 4
init_ring:
 
        DEBUGF  1,"init ring\n"
 
        lea     edi, [ebx + device.rx_ring]
        mov     eax, edi
        invoke  GetPhysAddr
        mov     [ebx + device.rx_ring_phys], eax
        mov     ecx, RX_RING_SIZE
  .rx_init:
        push    ecx
        invoke  NetAlloc, PKT_BUF_SZ+NET_BUFF.data
        pop     ecx
        test    eax, eax
        jz      .out_of_mem
        mov     [edi + descriptor.virtual], eax
        invoke  GetPhysAddr
        add     eax, NET_BUFF.data
        mov     [edi + descriptor.base], eax
        mov     [edi + descriptor.length], - PKT_BUF_SZ
        mov     [edi + descriptor.status], RXSTAT_OWN
        mov     dword[edi + descriptor.msg_length], 0    ; also clears misc field
        add     edi, sizeof.descriptor
        dec     ecx
        jnz     .rx_init
 
        lea     edi, [ebx + device.tx_ring]
        mov     eax, edi
        invoke  GetPhysAddr
        mov     [ebx + device.tx_ring_phys], eax
        mov     ecx, TX_RING_SIZE
  .tx_init:
        mov     [edi + descriptor.status], 0
        add     edi, sizeof.descriptor
        dec     ecx
        jnz     .tx_init
 
        mov     [ebx + device.tlen_rlen], (TX_RING_LEN_BITS or RX_RING_LEN_BITS)
 
        mov     [ebx + device.cur_tx], 0
        mov     [ebx + device.last_tx], 0
        mov     [ebx + device.cur_rx], 0
 
        xor     eax, eax
        ret
 
  .out_of_mem:
        DEBUGF  2,"Out of memory!\n"
 
        or      eax, -1
        ret
 
 
 
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                         ;;
;; Transmit                                ;;
;;                                         ;;
;; In: pointer to device structure in ebx  ;;
;;                                         ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
proc transmit stdcall bufferptr
 
        pushf
        cli
 
        mov     esi, [bufferptr]
        DEBUGF  1,"Transmitting packet, buffer:%x, size:%u\n", [bufferptr], [esi + NET_BUFF.length]
        lea     eax, [esi + NET_BUFF.data]
        DEBUGF  1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\
        [eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\
        [eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\
        [eax+13]:2,[eax+12]:2
 
        cmp     [esi + NET_BUFF.length], 1514
        ja      .fail
        cmp     [esi + NET_BUFF.length], 60
        jb      .fail
 
; check descriptor
        lea     edi, [ebx + device.tx_ring]
        movzx   ecx, [ebx + device.cur_tx]
        shl     ecx, 4
        add     edi, ecx
 
        test    [edi + descriptor.status], TXCTL_OWN
        jnz     .fail
; descriptor is free, use it
        mov     [edi + descriptor.virtual], esi
        mov     eax, esi
        add     eax, [eax + NET_BUFF.offset]
        invoke  GetPhysAddr
        mov     [edi + descriptor.base], eax
; set length
        mov     eax, [esi + NET_BUFF.length]
        neg     eax
        mov     [edi + descriptor.length], ax
; put to transfer queue
        mov     [edi + descriptor.status], TXCTL_OWN + TXCTL_STP + TXCTL_ENP
 
; trigger an immediate send
        mov     edx, [ebx + device.io_addr]
        xor     ecx, ecx                        ; CSR0
        call    [ebx + device.read_csr]
        or      eax, CSR_TX
        call    [ebx + device.write_csr]
 
; get next descriptor 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, ...
        inc     [ebx + device.cur_tx]
        and     [ebx + device.cur_tx], TX_RING_SIZE - 1
 
; Update stats
        inc     [ebx + device.packets_tx]
        mov     eax, [esi + NET_BUFF.length]
        add     dword[ebx + device.bytes_tx], eax
        adc     dword[ebx + device.bytes_tx + 4], 0
 
  .finish:
        popf
        xor     eax, eax
        ret
 
  .fail:
        DEBUGF  2, "Send failed\n"
        invoke  NetFree, [bufferptr]
        popf
        or      eax, -1
        ret
 
endp
 
 
;;;;;;;;;;;;;;;;;;;;;;;
;;                   ;;
;; Interrupt handler ;;
;;                   ;;
;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
int_handler:
 
        push    ebx esi edi
 
        DEBUGF  1,"INT\n"
 
; find pointer of device wich made IRQ occur
 
        mov     ecx, [devices]
        test    ecx, ecx
        jz      .nothing
        mov     esi, device_list
  .nextdevice:
        mov     ebx, [esi]
        mov     edx, [ebx + device.io_addr]
        push    ecx
        xor     ecx, ecx                        ; CSR0
        call    [ebx + device.read_csr]         ; get IRQ reason
        call    [ebx + device.write_csr]        ; write it back to ACK
        pop     ecx
        test    ax, CSR_RINT or CSR_TINT
 
        jnz     .got_it
  .continue:
        add     esi, 4
        dec     ecx
        jnz     .nextdevice
  .nothing:
        pop     edi esi ebx
        xor     eax, eax
 
        ret
 
  .got_it:
        DEBUGF  1,"Device: %x status: %x\n", ebx, eax:4
 
        push    ax
        test    ax, CSR_RINT
        jz      .not_receive
 
        push    ebx
  .rx_loop:
        pop     ebx
        movzx   eax, [ebx + device.cur_rx]
        shl     eax, 4
        lea     edi, [ebx + device.rx_ring]
        add     edi, eax                        ; edi now points to current rx ring entry
 
        mov     ax, [edi + descriptor.status]
        DEBUGF  1,"RX packet status: %x\n", eax:4
 
        test    ax, RXSTAT_OWN                  ; If this bit is set, the controller OWN's the packet, if not, we do
        jnz     .not_receive
 
        test    ax, RXSTAT_ENP
        jz      .not_receive
 
        test    ax, RXSTAT_STP
        jz      .not_receive
 
        movzx   ecx, [edi + descriptor.msg_length]      ; get packet length in ecx
        sub     ecx, 4                                  ; We dont need the CRC
        DEBUGF  1,"Got %u bytes\n", ecx
 
; Set pointers for ETH_input
        push    ebx
 
        push    .rx_loop                                ; return address
        mov     eax, [edi + descriptor.virtual]
        push    eax                                     ; packet address
        mov     [eax + NET_BUFF.length], ecx
        mov     [eax + NET_BUFF.device], ebx
        mov     [eax + NET_BUFF.offset], NET_BUFF.data
 
; Update stats
        add     dword[ebx + device.bytes_rx], ecx
        adc     dword[ebx + device.bytes_rx + 4], 0
        inc     [ebx + device.packets_rx]
 
; now allocate a new buffer
        invoke  NetAlloc, PKT_BUF_SZ+NET_BUFF.data      ; Allocate a buffer for the next packet
        test    eax, eax
        jz      .out_of_mem
        mov     [edi + descriptor.virtual], eax         ; set virtual address
        invoke  GetPhysAddr
        add     eax, NET_BUFF.data
        mov     [edi + descriptor.base], eax            ; and physical address
        mov     [edi + descriptor.status], RXSTAT_OWN   ; give it back to PCnet controller
 
        inc     [ebx + device.cur_rx]                   ; set next receive descriptor
        and     [ebx + device.cur_rx], RX_RING_SIZE - 1
 
        jmp     [EthInput]
 
  .out_of_mem:
        DEBUGF  2,"Out of memory!\n"
 
        inc     [ebx + device.cur_rx]                   ; set next receive descriptor
        and     [ebx + device.cur_rx], RX_RING_SIZE - 1
 
        jmp     [EthInput]
 
  .not_receive:
        pop     ax
 
        test    ax, CSR_TINT
        jz      .not_transmit
 
  .tx_loop:
        lea     edi, [ebx + device.tx_ring]
        movzx   eax, [ebx + device.last_tx]
        shl     eax, 4
        add     edi, eax
 
        test    [edi + descriptor.status], TXCTL_OWN
        jnz     .not_transmit
 
        mov     eax, [edi + descriptor.virtual]
        test    eax, eax
        jz      .not_transmit
 
        mov     [edi + descriptor.virtual], 0
 
        DEBUGF  1,"Removing packet %x from memory\n", eax
 
        invoke  NetFree, eax
 
        inc     [ebx + device.last_tx]
        and     [ebx + device.last_tx], TX_RING_SIZE - 1
        jmp     .tx_loop
 
  .not_transmit:
        pop     edi esi ebx
        xor     eax, eax
        inc     eax
 
        ret
 
 
 
 
;;;;;;;;;;;;;;;;;;;;;;;
;;                   ;;
;; Write MAC address ;;
;;                   ;;
;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
write_mac:      ; in: mac pushed onto stack (as 3 words)
 
        DEBUGF  1,"Writing MAC: %x-%x-%x-%x-%x-%x\n",\
        [esp+0]:2,[esp+1]:2,[esp+2]:2,[esp+3]:2,[esp+4]:2,[esp+5]:2
 
        mov     edx, [ebx + device.io_addr]
        add     dx, 2
        xor     eax, eax
 
        mov     ecx, CSR_PAR0
       @@:
        pop     ax
        call    [ebx + device.write_csr]
        inc     ecx
        cmp     ecx, CSR_PAR2
        jb      @r
 
; Notice this procedure does not ret, but continues to read_mac instead.
 
;;;;;;;;;;;;;;;;;;;;;;
;;                  ;;
;; Read MAC address ;;
;;                  ;;
;;;;;;;;;;;;;;;;;;;;;;
align 4
read_mac:
        DEBUGF  1,"Reading MAC\n"
 
        mov     edx, [ebx + device.io_addr]
        lea     edi, [ebx + device.mac]
        in      ax, dx
        stosw
 
        inc     dx
        inc     dx
        in      ax, dx
        stosw
 
        inc     dx
        inc     dx
        in      ax, dx
        stosw
 
        DEBUGF  1,"MAC = %x-%x-%x-%x-%x-%x\n",\
        [ebx + device.mac+0]:2,[ebx + device.mac+1]:2,[ebx + device.mac+2]:2,\
        [ebx + device.mac+3]:2,[ebx + device.mac+4]:2,[ebx + device.mac+5]:2
 
        ret
 
align 4
switch_to_wio:
 
        DEBUGF  1,"Switching to 16-bit mode\n"
 
        mov     [ebx + device.read_csr], wio_read_csr
        mov     [ebx + device.write_csr], wio_write_csr
        mov     [ebx + device.read_bcr], wio_read_bcr
        mov     [ebx + device.write_bcr], wio_write_bcr
        mov     [ebx + device.read_rap], wio_read_rap
        mov     [ebx + device.write_rap], wio_write_rap
        mov     [ebx + device.sw_reset], wio_reset
 
        ret
 
align 4
switch_to_dwio:
 
        DEBUGF  1,"Switching to 32-bit mode\n"
 
        mov     [ebx + device.read_csr], dwio_read_csr
        mov     [ebx + device.write_csr], dwio_write_csr
        mov     [ebx + device.read_bcr], dwio_read_bcr
        mov     [ebx + device.write_bcr], dwio_write_bcr
        mov     [ebx + device.read_rap], dwio_read_rap
        mov     [ebx + device.write_rap], dwio_write_rap
        mov     [ebx + device.sw_reset], dwio_reset
 
        ret
 
 
; ecx - index
; return:
; eax - data
align 4
wio_read_csr:
 
        add     edx, WIO_RAP
        mov     ax, cx
        out     dx, ax
        add     edx, WIO_RDP - WIO_RAP
        in      ax, dx
        and     eax, 0xffff
        sub     edx, WIO_RDP
 
        ret
 
 
; eax - data
; ecx - index
align 4
wio_write_csr:
 
        add     edx, WIO_RAP
        xchg    eax, ecx
        out     dx, ax
        xchg    eax, ecx
        add     edx, WIO_RDP - WIO_RAP
        out     dx, ax
        sub     edx, WIO_RDP
 
        ret
 
 
; ecx - index
; return:
; eax - data
align 4
wio_read_bcr:
 
        add     edx, WIO_RAP
        mov     ax, cx
        out     dx, ax
        add     edx, WIO_BDP - WIO_RAP
        in      ax, dx
        and     eax, 0xffff
        sub     edx, WIO_BDP
 
        ret
 
 
; eax - data
; ecx - index
align 4
wio_write_bcr:
 
        add     edx, WIO_RAP
        xchg    eax, ecx
        out     dx, ax
        xchg    eax, ecx
        add     edx, WIO_BDP - WIO_RAP
        out     dx, ax
        sub     edx, WIO_BDP
 
        ret
 
align 4
wio_read_rap:
 
        add     edx, WIO_RAP
        in      ax, dx
        and     eax, 0xffff
        sub     edx, WIO_RAP
 
        ret
 
; eax - val
align 4
wio_write_rap:
 
        add     edx, WIO_RAP
        out     dx, ax
        sub     edx, WIO_RAP
 
        ret
 
align 4
wio_reset:
 
        push    eax
        add     edx, WIO_RESET
        in      ax, dx
        pop     eax
        sub     edx, WIO_RESET
 
        ret
 
 
 
; ecx - index
; return:
; eax - data
align 4
dwio_read_csr:
 
        add     edx, DWIO_RAP
        mov     eax, ecx
        out     dx, eax
        add     edx, DWIO_RDP - DWIO_RAP
        in      eax, dx
        and     eax, 0xffff
        sub     edx, DWIO_RDP
 
        ret
 
 
; ecx - index
; eax - data
align 4
dwio_write_csr:
 
        add     edx, DWIO_RAP
        xchg    eax, ecx
        out     dx, eax
        add     edx, DWIO_RDP - DWIO_RAP
        xchg    eax, ecx
        out     dx, eax
        sub     edx, DWIO_RDP
 
        ret
 
; ecx - index
; return:
; eax - data
align 4
dwio_read_bcr:
 
        add     edx, DWIO_RAP
        mov     eax, ecx
        out     dx, eax
        add     edx, DWIO_BDP - DWIO_RAP
        in      eax, dx
        and     eax, 0xffff
        sub     edx, DWIO_BDP
 
        ret
 
 
; ecx - index
; eax - data
align 4
dwio_write_bcr:
 
        add     edx, DWIO_RAP
        xchg    eax, ecx
        out     dx, eax
        add     edx, DWIO_BDP - DWIO_RAP
        xchg    eax, ecx
        out     dx, eax
        sub     edx, DWIO_BDP
 
        ret
 
align 4
dwio_read_rap:
 
        add     edx, DWIO_RAP
        in      eax, dx
        and     eax, 0xffff
        sub     edx, DWIO_RAP
 
        ret
 
 
; eax - val
align 4
dwio_write_rap:
 
        add     edx, DWIO_RAP
        out     dx, eax
        sub     edx, DWIO_RAP
 
        ret
 
align 4
dwio_reset:
 
        push    eax
        add     edx, DWIO_RESET
        in      eax, dx
        pop     eax
        sub     edx, DWIO_RESET
 
        ret
 
 
align 4
mdio_read:
 
        and     ecx, 0x1f
        mov     ax, [ebx + device.phy]
        and     ax, 0x1f
        shl     ax, 5
        or      ax, cx
 
        mov     ecx, BCR_MIIADDR
        call    [ebx + device.write_bcr]
 
        mov     ecx, BCR_MIIDATA
        call    [ebx + device.read_bcr]
 
        ret
 
 
align 4
mdio_write:
 
        push    eax
        and     ecx, 0x1f
        mov     ax, [ebx + device.phy]
        and     ax, 0x1f
        shl     ax, 5
        or      ax, cx
 
        mov     ecx, BCR_MIIADDR
        call    [ebx + device.write_bcr]
 
        pop     eax
        mov     ecx, BCR_MIIDATA
        call    [ebx + device.write_bcr]
 
        ret
 
 
align 4
check_media:
 
        DEBUGF  1, "check_media\n"
 
        test    [ebx + device.mii], 1
        jnz     mii_link_ok
 
        mov     ecx, BCR_LED0
        call    [ebx + device.read_bcr]
        cmp     eax, 0xc0
 
        DEBUGF  2, "link status=0x%x\n", ax
 
        ret
 
 
 
; End of code
 
 
data fixups
end data
 
include '../peimport.inc'
 
my_service    db 'PCNET32',0            ; max 16 chars include zero
 
device_l2     db "PCnet/PCI 79C970",0
device_l4     db "PCnet/PCI II 79C970A",0
device_l5     db "PCnet/FAST 79C971",0
device_l6     db "PCnet/FAST+ 79C972",0
device_l7     db "PCnet/FAST III 79C973",0
device_l8     db "PCnet/Home 79C978",0
device_l9     db "PCnet/FAST III 79C975",0
 
options_mapping:
dd PORT_ASEL                            ; 0 Auto-select
dd PORT_AUI                             ; 1 BNC/AUI
dd PORT_AUI                             ; 2 AUI/BNC
dd PORT_ASEL                            ; 3 not supported
dd PORT_10BT or PORT_FD                 ; 4 10baseT-FD
dd PORT_ASEL                            ; 5 not supported
dd PORT_ASEL                            ; 6 not supported
dd PORT_ASEL                            ; 7 not supported
dd PORT_ASEL                            ; 8 not supported
dd PORT_MII                             ; 9 MII 10baseT
dd PORT_MII or PORT_FD                  ; 10 MII 10baseT-FD
dd PORT_MII                             ; 11 MII (autosel)
dd PORT_10BT                            ; 12 10BaseT
dd PORT_MII or PORT_100                 ; 13 MII 100BaseTx
dd PORT_MII or PORT_100 or PORT_FD      ; 14 MII 100BaseTx-FD
dd PORT_ASEL                            ; 15 not supported
 
include_debug_strings                                   ; All data wich FDO uses will be included here
 
 
align 4
devices     dd 0
device_list rd MAX_DEVICES                              ; This list contains all pointers to device structures the driver is handling

Rev 5522	Rev 5617
1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2	;; ;;	2	;; ;;
3	;; Copyright (C) KolibriOS team 2004-2015. All rights reserved. ;;	3	;; Copyright (C) KolibriOS team 2004-2015. All rights reserved. ;;
4	;; Distributed under terms of the GNU General Public License ;;	4	;; Distributed under terms of the GNU General Public License ;;
5	;; ;;	5	;; ;;
6	;; AMD PCnet driver for KolibriOS ;;	6	;; AMD PCnet driver for KolibriOS ;;
7	;; ;;	7	;; ;;
8	;; By hidnplayr & clevermouse ;;	8	;; By hidnplayr & clevermouse ;;
9	;; ;;	9	;; ;;
10	;; Based on the PCnet32 driver for MenuetOS, by Jarek Pelczar ;;	10	;; Based on the PCnet32 driver for MenuetOS, by Jarek Pelczar ;;
11	;; ;;	11	;; ;;
12	;; GNU GENERAL PUBLIC LICENSE ;;	12	;; GNU GENERAL PUBLIC LICENSE ;;
13	;; Version 2, June 1991 ;;	13	;; Version 2, June 1991 ;;
14	;; ;;	14	;; ;;
15	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	15	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
16		16
17	format PE DLL native	17	format PE DLL native
18	entry START	18	entry START
19		19
20	CURRENT_API = 0x0200	20	CURRENT_API = 0x0200
21	COMPATIBLE_API = 0x0100	21	COMPATIBLE_API = 0x0100
22	API_VERSION = (COMPATIBLE_API shl 16) + CURRENT_API	22	API_VERSION = (COMPATIBLE_API shl 16) + CURRENT_API
23		23
24	MAX_DEVICES = 16	24	MAX_DEVICES = 16
25		25
26	__DEBUG__ = 1	26	__DEBUG__ = 1
27	__DEBUG_LEVEL__ = 2 ; 1 = verbose, 2 = errors only	27	__DEBUG_LEVEL__ = 2 ; 1 = verbose, 2 = errors only
28		28
29	TX_RING_SIZE = 4	29	TX_RING_SIZE = 4
30	RX_RING_SIZE = 4	30	RX_RING_SIZE = 4
31		31
32	section '.flat' readable writable executable	32	section '.flat' readable writable executable
33		33
34	include '../struct.inc'	34	include '../struct.inc'
35	include '../macros.inc'	35	include '../macros.inc'
36	include '../proc32.inc'	36	include '../proc32.inc'
37	include '../fdo.inc'	37	include '../fdo.inc'
38	include '../netdrv.inc'	38	include '../netdrv.inc'
39		39
40		40
41	PORT_AUI = 0x00	41	PORT_AUI = 0x00
42	PORT_10BT = 0x01	42	PORT_10BT = 0x01
43	PORT_GPSI = 0x02	43	PORT_GPSI = 0x02
44	PORT_MII = 0x03	44	PORT_MII = 0x03
45	PORT_PORTSEL = 0x03	45	PORT_PORTSEL = 0x03
46	PORT_ASEL = 0x04	46	PORT_ASEL = 0x04
47	PORT_100 = 0x40	47	PORT_100 = 0x40
48	PORT_FD = 0x80	48	PORT_FD = 0x80
49		49
50	DMA_MASK = 0xffffffff	50	DMA_MASK = 0xffffffff
51		51
52	LOG_TX_BUFFERS = 2 ; FIXME	52	LOG_TX_BUFFERS = 2 ; FIXME
53	LOG_RX_BUFFERS = 2	53	LOG_RX_BUFFERS = 2
54		54
55	TX_RING_MOD_MASK = (TX_RING_SIZE-1)	55	TX_RING_MOD_MASK = (TX_RING_SIZE-1)
56	TX_RING_LEN_BITS = (LOG_TX_BUFFERS shl 12)	56	TX_RING_LEN_BITS = (LOG_TX_BUFFERS shl 12)
57		57
58	RX_RING_MOD_MASK = (RX_RING_SIZE-1)	58	RX_RING_MOD_MASK = (RX_RING_SIZE-1)
59	RX_RING_LEN_BITS = (LOG_RX_BUFFERS shl 4)	59	RX_RING_LEN_BITS = (LOG_RX_BUFFERS shl 4)
60		60
61	PKT_BUF_SZ = 1544	61	PKT_BUF_SZ = 1544
62		62
63	WIO_RDP = 0x10	63	WIO_RDP = 0x10
64	WIO_RAP = 0x12	64	WIO_RAP = 0x12
65	WIO_RESET = 0x14	65	WIO_RESET = 0x14
66	WIO_BDP = 0x16	66	WIO_BDP = 0x16
67		67
68	DWIO_RDP = 0x10	68	DWIO_RDP = 0x10
69	DWIO_RAP = 0x14	69	DWIO_RAP = 0x14
70	DWIO_RESET = 0x18	70	DWIO_RESET = 0x18
71	DWIO_BDP = 0x1C	71	DWIO_BDP = 0x1C
72		72
73	; CSR registers	73	; CSR registers
74		74
75	CSR_CSR = 0x00	75	CSR_CSR = 0x00
76	CSR_IAB0 = 0x01	76	CSR_IAB0 = 0x01
77	CSR_IAB1 = 0x02	77	CSR_IAB1 = 0x02
78	CSR_IMR = 0x03	78	CSR_IMR = 0x03
79	CSR_TFEAT = 0x04	79	CSR_TFEAT = 0x04
80	CSR_EXTCTL1 = 0x05	80	CSR_EXTCTL1 = 0x05
81	CSR_DTBLLEN = 0x06	81	CSR_DTBLLEN = 0x06
82	CSR_EXTCTL2 = 0x07	82	CSR_EXTCTL2 = 0x07
83	CSR_MAR0 = 0x08	83	CSR_MAR0 = 0x08
84	CSR_MAR1 = 0x09	84	CSR_MAR1 = 0x09
85	CSR_MAR2 = 0x0A	85	CSR_MAR2 = 0x0A
86	CSR_MAR3 = 0x0B	86	CSR_MAR3 = 0x0B
87	CSR_PAR0 = 0x0C	87	CSR_PAR0 = 0x0C
88	CSR_PAR1 = 0x0D	88	CSR_PAR1 = 0x0D
89	CSR_PAR2 = 0x0E	89	CSR_PAR2 = 0x0E
90	CSR_MODE = 0x0F	90	CSR_MODE = 0x0F
91	CSR_RXADDR0 = 0x18	91	CSR_RXADDR0 = 0x18
92	CSR_RXADDR1 = 0x19	92	CSR_RXADDR1 = 0x19
93	CSR_TXADDR0 = 0x1E	93	CSR_TXADDR0 = 0x1E
94	CSR_TXADDR1 = 0x1F	94	CSR_TXADDR1 = 0x1F
95	CSR_TXPOLL = 0x2F	95	CSR_TXPOLL = 0x2F
96	CSR_RXPOLL = 0x31	96	CSR_RXPOLL = 0x31
97	CSR_RXRINGLEN = 0x4C	97	CSR_RXRINGLEN = 0x4C
98	CSR_TXRINGLEN = 0x4E	98	CSR_TXRINGLEN = 0x4E
99	CSR_DMACTL = 0x50	99	CSR_DMACTL = 0x50
100	CSR_BUSTIMER = 0x52	100	CSR_BUSTIMER = 0x52
101	CSR_MEMERRTIMEO = 0x64	101	CSR_MEMERRTIMEO = 0x64
102	CSR_ONNOWMISC = 0x74	102	CSR_ONNOWMISC = 0x74
103	CSR_ADVFEAT = 0x7A	103	CSR_ADVFEAT = 0x7A
104	CSR_MACCFG = 0x7D	104	CSR_MACCFG = 0x7D
105	CSR_CHIPID0 = 0x58	105	CSR_CHIPID0 = 0x58
106	CSR_CHIPID1 = 0x59	106	CSR_CHIPID1 = 0x59
107		107
108	; Control and Status Register (CSR0)	108	; Control and Status Register (CSR0)
109		109
110	CSR_INIT = 0x0001 ;1 shl 0	110	CSR_INIT = 0x0001 ;1 shl 0
111	CSR_START = 0x0002 ;1 shl 1	111	CSR_START = 0x0002 ;1 shl 1
112	CSR_STOP = 0x0004 ;1 shl 2	112	CSR_STOP = 0x0004 ;1 shl 2
113	CSR_TX = 0x0008 ;1 shl 3	113	CSR_TX = 0x0008 ;1 shl 3
114	CSR_TXON = 0x0010 ;1 shl 4	114	CSR_TXON = 0x0010 ;1 shl 4
115	CSR_RXON = 0x0020 ;1 shl 5	115	CSR_RXON = 0x0020 ;1 shl 5
116	CSR_INTEN = 0x0040 ;1 shl 6	116	CSR_INTEN = 0x0040 ;1 shl 6
117	CSR_INTR = 0x0080 ;1 shl 7	117	CSR_INTR = 0x0080 ;1 shl 7
118	CSR_IDONE = 0x0100 ;1 shl 8	118	CSR_IDONE = 0x0100 ;1 shl 8
119	CSR_TINT = 0x0200 ;1 shl 9	119	CSR_TINT = 0x0200 ;1 shl 9
120	CSR_RINT = 0x0400 ;1 shl 10	120	CSR_RINT = 0x0400 ;1 shl 10
121	CSR_MERR = 0x0800 ;1 shl 11	121	CSR_MERR = 0x0800 ;1 shl 11
122	CSR_MISS = 0x1000 ;1 shl 12	122	CSR_MISS = 0x1000 ;1 shl 12
123	CSR_CERR = 0x2000 ;1 shl 13	123	CSR_CERR = 0x2000 ;1 shl 13
124		124
125	; Interrupt masks and deferral control (CSR3)	125	; Interrupt masks and deferral control (CSR3)
126		126
127	IMR_BSWAP = 0x0004	127	IMR_BSWAP = 0x0004
128	IMR_ENMBA = 0x0008 ; enable modified backoff alg	128	IMR_ENMBA = 0x0008 ; enable modified backoff alg
129	IMR_DXMT2PD = 0x0010	129	IMR_DXMT2PD = 0x0010
130	IMR_LAPPEN = 0x0020 ; lookahead packet processing enb	130	IMR_LAPPEN = 0x0020 ; lookahead packet processing enb
131	IMR_DXSUFLO = 0x0040 ; disable TX stop on underflow	131	IMR_DXSUFLO = 0x0040 ; disable TX stop on underflow
132	IMR_IDONE = 0x0100	132	IMR_IDONE = 0x0100
133	IMR_TINT = 0x0200	133	IMR_TINT = 0x0200
134	IMR_RINT = 0x0400	134	IMR_RINT = 0x0400
135	IMR_MERR = 0x0800	135	IMR_MERR = 0x0800
136	IMR_MISS = 0x1000	136	IMR_MISS = 0x1000
137		137
138	; Masked interrupts will be disabled.	138	; Masked interrupts will be disabled.
139	IMR = 0 ;IMR_IDONE ;or IMR_TINT or IMR_RINT or IMR_MERR or IMR_MISS	139	IMR = 0 ;IMR_IDONE ;or IMR_TINT or IMR_RINT or IMR_MERR or IMR_MISS
140		140
141	; Test and features control (CSR4)	141	; Test and features control (CSR4)
142		142
143	TFEAT_TXSTRTMASK = 0x0004	143	TFEAT_TXSTRTMASK = 0x0004
144	TFEAT_TXSTRT = 0x0008	144	TFEAT_TXSTRT = 0x0008
145	TFEAT_RXCCOFLOWM = 0x0010 ; Rx collision counter oflow	145	TFEAT_RXCCOFLOWM = 0x0010 ; Rx collision counter oflow
146	TFEAT_RXCCOFLOW = 0x0020	146	TFEAT_RXCCOFLOW = 0x0020
147	TFEAT_UINT = 0x0040	147	TFEAT_UINT = 0x0040
148	TFEAT_UINTREQ = 0x0080	148	TFEAT_UINTREQ = 0x0080
149	TFEAT_MISSOFLOWM = 0x0100	149	TFEAT_MISSOFLOWM = 0x0100
150	TFEAT_MISSOFLOW = 0x0200	150	TFEAT_MISSOFLOW = 0x0200
151	TFEAT_STRIP_FCS = 0x0400	151	TFEAT_STRIP_FCS = 0x0400
152	TFEAT_PAD_TX = 0x0800	152	TFEAT_PAD_TX = 0x0800
153	TFEAT_TXDPOLL = 0x1000	153	TFEAT_TXDPOLL = 0x1000
154	TFEAT_DMAPLUS = 0x4000	154	TFEAT_DMAPLUS = 0x4000
155		155
156	; Extended control and interrupt 1 (CSR5)	156	; Extended control and interrupt 1 (CSR5)
157		157
158	EXTCTL1_SPND = 0x0001 ; suspend	158	EXTCTL1_SPND = 0x0001 ; suspend
159	EXTCTL1_MPMODE = 0x0002 ; magic packet mode	159	EXTCTL1_MPMODE = 0x0002 ; magic packet mode
160	EXTCTL1_MPENB = 0x0004 ; magic packet enable	160	EXTCTL1_MPENB = 0x0004 ; magic packet enable
161	EXTCTL1_MPINTEN = 0x0008 ; magic packet interrupt enable	161	EXTCTL1_MPINTEN = 0x0008 ; magic packet interrupt enable
162	EXTCTL1_MPINT = 0x0010 ; magic packet interrupt	162	EXTCTL1_MPINT = 0x0010 ; magic packet interrupt
163	EXTCTL1_MPPLBA = 0x0020 ; magic packet phys. logical bcast	163	EXTCTL1_MPPLBA = 0x0020 ; magic packet phys. logical bcast
164	EXTCTL1_EXDEFEN = 0x0040 ; excessive deferral interrupt enb.	164	EXTCTL1_EXDEFEN = 0x0040 ; excessive deferral interrupt enb.
165	EXTCTL1_EXDEF = 0x0080 ; excessive deferral interrupt	165	EXTCTL1_EXDEF = 0x0080 ; excessive deferral interrupt
166	EXTCTL1_SINTEN = 0x0400 ; system interrupt enable	166	EXTCTL1_SINTEN = 0x0400 ; system interrupt enable
167	EXTCTL1_SINT = 0x0800 ; system interrupt	167	EXTCTL1_SINT = 0x0800 ; system interrupt
168	EXTCTL1_LTINTEN = 0x4000 ; last TX interrupt enb	168	EXTCTL1_LTINTEN = 0x4000 ; last TX interrupt enb
169	EXTCTL1_TXOKINTD = 0x8000 ; TX OK interrupt disable	169	EXTCTL1_TXOKINTD = 0x8000 ; TX OK interrupt disable
170		170
171	; RX/TX descriptor len (CSR6)	171	; RX/TX descriptor len (CSR6)
172		172
173	DTBLLEN_RLEN = 0x0F00	173	DTBLLEN_RLEN = 0x0F00
174	DTBLLEN_TLEN = 0xF000	174	DTBLLEN_TLEN = 0xF000
175		175
176	; Extended control and interrupt 2 (CSR7)	176	; Extended control and interrupt 2 (CSR7)
177		177
178	EXTCTL2_MIIPDTINTE = 0x0001	178	EXTCTL2_MIIPDTINTE = 0x0001
179	EXTCTL2_MIIPDTINT = 0x0002	179	EXTCTL2_MIIPDTINT = 0x0002
180	EXTCTL2_MCCIINTE = 0x0004	180	EXTCTL2_MCCIINTE = 0x0004
181	EXTCTL2_MCCIINT = 0x0008	181	EXTCTL2_MCCIINT = 0x0008
182	EXTCTL2_MCCINTE = 0x0010	182	EXTCTL2_MCCINTE = 0x0010
183	EXTCTL2_MCCINT = 0x0020	183	EXTCTL2_MCCINT = 0x0020
184	EXTCTL2_MAPINTE = 0x0040	184	EXTCTL2_MAPINTE = 0x0040
185	EXTCTL2_MAPINT = 0x0080	185	EXTCTL2_MAPINT = 0x0080
186	EXTCTL2_MREINTE = 0x0100	186	EXTCTL2_MREINTE = 0x0100
187	EXTCTL2_MREINT = 0x0200	187	EXTCTL2_MREINT = 0x0200
188	EXTCTL2_STINTE = 0x0400	188	EXTCTL2_STINTE = 0x0400
189	EXTCTL2_STINT = 0x0800	189	EXTCTL2_STINT = 0x0800
190	EXTCTL2_RXDPOLL = 0x1000	190	EXTCTL2_RXDPOLL = 0x1000
191	EXTCTL2_RDMD = 0x2000	191	EXTCTL2_RDMD = 0x2000
192	EXTCTL2_RXFRTG = 0x4000	192	EXTCTL2_RXFRTG = 0x4000
193	EXTCTL2_FASTSPNDE = 0x8000	193	EXTCTL2_FASTSPNDE = 0x8000
194		194
195	; Mode (CSR15)	195	; Mode (CSR15)
196		196
197	MODE_RXD = 0x0001 ; RX disable	197	MODE_RXD = 0x0001 ; RX disable
198	MODE_TXD = 0x0002 ; TX disable	198	MODE_TXD = 0x0002 ; TX disable
199	MODE_LOOP = 0x0004 ; loopback enable	199	MODE_LOOP = 0x0004 ; loopback enable
200	MODE_TXCRCD = 0x0008	200	MODE_TXCRCD = 0x0008
201	MODE_FORCECOLL = 0x0010	201	MODE_FORCECOLL = 0x0010
202	MODE_RETRYD = 0x0020	202	MODE_RETRYD = 0x0020
203	MODE_INTLOOP = 0x0040	203	MODE_INTLOOP = 0x0040
204	MODE_PORTSEL = 0x0180	204	MODE_PORTSEL = 0x0180
205	MODE_RXVPAD = 0x2000	205	MODE_RXVPAD = 0x2000
206	MODE_RXNOBROAD = 0x4000	206	MODE_RXNOBROAD = 0x4000
207	MODE_PROMISC = 0x8000	207	MODE_PROMISC = 0x8000
208		208
209	; BCR (Bus Control Registers)	209	; BCR (Bus Control Registers)
210		210
211	BCR_MMRA = 0x00 ; Master Mode Read Active	211	BCR_MMRA = 0x00 ; Master Mode Read Active
212	BCR_MMW = 0x01 ; Master Mode Write Active	212	BCR_MMW = 0x01 ; Master Mode Write Active
213	BCR_MISCCFG = 0x02	213	BCR_MISCCFG = 0x02
214	BCR_LED0 = 0x04	214	BCR_LED0 = 0x04
215	BCR_LED1 = 0x05	215	BCR_LED1 = 0x05
216	BCR_LED2 = 0x06	216	BCR_LED2 = 0x06
217	BCR_LED3 = 0x07	217	BCR_LED3 = 0x07
218	BCR_DUPLEX = 0x09	218	BCR_DUPLEX = 0x09
219	BCR_BUSCTL = 0x12	219	BCR_BUSCTL = 0x12
220	BCR_EECTL = 0x13	220	BCR_EECTL = 0x13
221	BCR_SSTYLE = 0x14	221	BCR_SSTYLE = 0x14
222	BCR_PCILAT = 0x16	222	BCR_PCILAT = 0x16
223	BCR_PCISUBVENID = 0x17	223	BCR_PCISUBVENID = 0x17
224	BCR_PCISUBSYSID = 0x18	224	BCR_PCISUBSYSID = 0x18
225	BCR_SRAMSIZE = 0x19	225	BCR_SRAMSIZE = 0x19
226	BCR_SRAMBOUND = 0x1A	226	BCR_SRAMBOUND = 0x1A
227	BCR_SRAMCTL = 0x1B	227	BCR_SRAMCTL = 0x1B
228	BCR_MIICTL = 0x20	228	BCR_MIICTL = 0x20
229	BCR_MIIADDR = 0x21	229	BCR_MIIADDR = 0x21
230	BCR_MIIDATA = 0x22	230	BCR_MIIDATA = 0x22
231	BCR_PCIVENID = 0x23	231	BCR_PCIVENID = 0x23
232	BCR_PCIPCAP = 0x24	232	BCR_PCIPCAP = 0x24
233	BCR_DATA0 = 0x25	233	BCR_DATA0 = 0x25
234	BCR_DATA1 = 0x26	234	BCR_DATA1 = 0x26
235	BCR_DATA2 = 0x27	235	BCR_DATA2 = 0x27
236	BCR_DATA3 = 0x28	236	BCR_DATA3 = 0x28
237	BCR_DATA4 = 0x29	237	BCR_DATA4 = 0x29
238	BCR_DATA5 = 0x2A	238	BCR_DATA5 = 0x2A
239	BCR_DATA6 = 0x2B	239	BCR_DATA6 = 0x2B
240	BCR_DATA7 = 0x2C	240	BCR_DATA7 = 0x2C
241	BCR_ONNOWPAT0 = 0x2D	241	BCR_ONNOWPAT0 = 0x2D
242	BCR_ONNOWPAT1 = 0x2E	242	BCR_ONNOWPAT1 = 0x2E
243	BCR_ONNOWPAT2 = 0x2F	243	BCR_ONNOWPAT2 = 0x2F
244	BCR_PHYSEL = 0x31	244	BCR_PHYSEL = 0x31
245		245
246	; RX status register	246	; RX status register
247		247
248	RXSTAT_BPE = 0x0080 ; bus parity error	248	RXSTAT_BPE = 0x0080 ; bus parity error
249	RXSTAT_ENP = 0x0100 ; end of packet	249	RXSTAT_ENP = 0x0100 ; end of packet
250	RXSTAT_STP = 0x0200 ; start of packet	250	RXSTAT_STP = 0x0200 ; start of packet
251	RXSTAT_BUFF = 0x0400 ; buffer error	251	RXSTAT_BUFF = 0x0400 ; buffer error
252	RXSTAT_CRC = 0x0800 ; CRC error	252	RXSTAT_CRC = 0x0800 ; CRC error
253	RXSTAT_OFLOW = 0x1000 ; rx overrun	253	RXSTAT_OFLOW = 0x1000 ; rx overrun
254	RXSTAT_FRAM = 0x2000 ; framing error	254	RXSTAT_FRAM = 0x2000 ; framing error
255	RXSTAT_ERR = 0x4000 ; error summary	255	RXSTAT_ERR = 0x4000 ; error summary
256	RXSTAT_OWN = 0x8000	256	RXSTAT_OWN = 0x8000
257		257
258	; TX status register	258	; TX status register
259		259
260	TXSTAT_TRC = 0x0000000F ; transmit retries	260	TXSTAT_TRC = 0x0000000F ; transmit retries
261	TXSTAT_RTRY = 0x04000000 ; retry	261	TXSTAT_RTRY = 0x04000000 ; retry
262	TXSTAT_LCAR = 0x08000000 ; lost carrier	262	TXSTAT_LCAR = 0x08000000 ; lost carrier
263	TXSTAT_LCOL = 0x10000000 ; late collision	263	TXSTAT_LCOL = 0x10000000 ; late collision
264	TXSTAT_EXDEF = 0x20000000 ; excessive deferrals	264	TXSTAT_EXDEF = 0x20000000 ; excessive deferrals
265	TXSTAT_UFLOW = 0x40000000 ; transmit underrun	265	TXSTAT_UFLOW = 0x40000000 ; transmit underrun
266	TXSTAT_BUFF = 0x80000000 ; buffer error	266	TXSTAT_BUFF = 0x80000000 ; buffer error
267		267
268	TXCTL_OWN = 0x8000	268	TXCTL_OWN = 0x8000
269	TXCTL_ERR = 0x4000 ; error summary	269	TXCTL_ERR = 0x4000 ; error summary
270	TXCTL_ADD_FCS = 0x2000 ; add FCS to pkt	270	TXCTL_ADD_FCS = 0x2000 ; add FCS to pkt
271	TXCTL_MORE_LTINT = 0x1000	271	TXCTL_MORE_LTINT = 0x1000
272	TXCTL_ONE = 0x0800	272	TXCTL_ONE = 0x0800
273	TXCTL_DEF = 0x0400	273	TXCTL_DEF = 0x0400
274	TXCTL_STP = 0x0200	274	TXCTL_STP = 0x0200
275	TXCTL_ENP = 0x0100	275	TXCTL_ENP = 0x0100
276	TXCTL_BPE = 0x0080	276	TXCTL_BPE = 0x0080
277		277
278	TXCTL_MBO = 0x0000F000	278	TXCTL_MBO = 0x0000F000
279	TXCTL_BUFSZ = 0x00000FFF	279	TXCTL_BUFSZ = 0x00000FFF
280		280
281	MAX_PHYS = 32	281	MAX_PHYS = 32
282		282
283		283
284	struct device ETH_DEVICE	284	struct device ETH_DEVICE
285		285
286	rb 0x100-($ and 0xff) ; align 256	286	rb 0x100-($ and 0xff) ; align 256
287		287
288	; Pcnet configuration structure	288	; Pcnet configuration structure
289	mode dw ?	289	mode dw ?
290	tlen_rlen dw ?	290	tlen_rlen dw ?
291	phys_addr dp ?	291	phys_addr dp ?
292	reserved dw ?	292	reserved dw ?
293	filter dq ?	293	filter dq ?
294	rx_ring_phys dd ?	294	rx_ring_phys dd ?
295	tx_ring_phys dd ?	295	tx_ring_phys dd ?
296	; end of pcnet config struct	296	; end of pcnet config struct
297		297
298	rb 0x100-($ and 0xff) ; align 256	298	rb 0x100-($ and 0xff) ; align 256
299		299
300	rx_ring rb RX_RING_SIZE * sizeof.descriptor	300	rx_ring rb RX_RING_SIZE * sizeof.descriptor
301		301
302	rb 0x100-($ and 0xff) ; align 256	302	rb 0x100-($ and 0xff) ; align 256
303		303
304	tx_ring rb TX_RING_SIZE * sizeof.descriptor	304	tx_ring rb TX_RING_SIZE * sizeof.descriptor
305		305
306	cur_rx db ?	306	cur_rx db ?
307	cur_tx db ?	307	cur_tx db ?
308	last_tx db ?	308	last_tx db ?
309	options dd ?	309	options dd ?
310	full_duplex db ?	310	full_duplex db ?
311	chip_version dw ?	311	chip_version dw ?
312	mii db ?	312	mii db ?
313	ltint db ?	313	ltint db ?
314	dxsuflo db ?	314	dxsuflo db ?
315	fset db ?	315	fset db ?
316	fdx db ?	316	fdx db ?
317		317
318	io_addr dd ?	318	io_addr dd ?
319	irq_line db ?	319	irq_line db ?
320	pci_bus dd ?	320	pci_bus dd ?
321	pci_dev dd ?	321	pci_dev dd ?
322		322
323	phy dw ?	323	phy dw ?
324		324
325	read_csr dd ?	325	read_csr dd ?
326	write_csr dd ?	326	write_csr dd ?
327	read_bcr dd ?	327	read_bcr dd ?
328	write_bcr dd ?	328	write_bcr dd ?
329	read_rap dd ?	329	read_rap dd ?
330	write_rap dd ?	330	write_rap dd ?
331	sw_reset dd ?	331	sw_reset dd ?
332		332
333	ends	333	ends
334		334
335	struct descriptor	335	struct descriptor
336		336
337	base dd ?	337	base dd ?
338	length dw ?	338	length dw ?
339	status dw ?	339	status dw ?
340	msg_length dw ?	340	msg_length dw ?
341	misc dw ?	341	misc dw ?
342	virtual dd ?	342	virtual dd ?
343		343
344	ends	344	ends
345		345
346		346
347	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	347	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
348	;; ;;	348	;; ;;
349	;; proc START ;;	349	;; proc START ;;
350	;; ;;	350	;; ;;
351	;; (standard driver proc) ;;	351	;; (standard driver proc) ;;
352	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	352	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
353		353
354	proc START c, reason:dword, cmdline:dword	354	proc START c, reason:dword, cmdline:dword
355		355
356	cmp [reason], DRV_ENTRY	356	cmp [reason], DRV_ENTRY
357	jne .fail	357	jne .fail
358		358
359	DEBUGF 2,"Loading driver\n"	359	DEBUGF 2,"Loading driver\n"
360	invoke RegService, my_service, service_proc	360	invoke RegService, my_service, service_proc
361	ret	361	ret
362		362
363	.fail:	363	.fail:
364	xor eax, eax	364	xor eax, eax
365	ret	365	ret
366		366
367	endp	367	endp
368		368
369		369
370	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	370	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
371	;; ;;	371	;; ;;
372	;; proc SERVICE_PROC ;;	372	;; proc SERVICE_PROC ;;
373	;; ;;	373	;; ;;
374	;; (standard driver proc) ;;	374	;; (standard driver proc) ;;
375	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	375	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
376		376
377	align 4	377	align 4
378	proc service_proc stdcall, ioctl:dword	378	proc service_proc stdcall, ioctl:dword
379		379
380	mov edx, [ioctl]	380	mov edx, [ioctl]
381	mov eax, [edx + IOCTL.io_code]	381	mov eax, [edx + IOCTL.io_code]
382		382
383	;------------------------------------------------------	383	;------------------------------------------------------
384		384
385	cmp eax, 0 ;SRV_GETVERSION	385	cmp eax, 0 ;SRV_GETVERSION
386	jne @F	386	jne @F
387		387
388	cmp [edx + IOCTL.out_size], 4	388	cmp [edx + IOCTL.out_size], 4
389	jb .fail	389	jb .fail
390	mov eax, [edx + IOCTL.output]	390	mov eax, [edx + IOCTL.output]
391	mov [eax], dword API_VERSION	391	mov [eax], dword API_VERSION
392		392
393	xor eax, eax	393	xor eax, eax
394	ret	394	ret
395		395
396	;------------------------------------------------------	396	;------------------------------------------------------
397	@@:	397	@@:
398	cmp eax, 1 ;SRV_HOOK	398	cmp eax, 1 ;SRV_HOOK
399	jne .fail	399	jne .fail
400		400
401	cmp [edx + IOCTL.inp_size], 3 ; Data input must be at least 3 bytes	401	cmp [edx + IOCTL.inp_size], 3 ; Data input must be at least 3 bytes
402	jb .fail	402	jb .fail
403		403
404	mov eax, [edx + IOCTL.input]	404	mov eax, [edx + IOCTL.input]
405	cmp byte[eax], 1 ; 1 means device number and bus number (pci) are given	405	cmp byte[eax], 1 ; 1 means device number and bus number (pci) are given
406	jne .fail ; other types arent supported for this card yet	406	jne .fail ; other types arent supported for this card yet
407		407
408	; check if the device is already listed	408	; check if the device is already listed
409		409
410	mov ecx, [devices]	410	mov ecx, [devices]
411	test ecx, ecx	411	test ecx, ecx
412	jz .firstdevice	412	jz .firstdevice
413		413
414	mov esi, device_list	414	mov esi, device_list
415	; mov eax, [edx + IOCTL.input] ; get the pci bus and device numbers	415	; mov eax, [edx + IOCTL.input] ; get the pci bus and device numbers
416	mov ax, [eax+1] ;	416	mov ax, [eax+1] ;
417	.nextdevice:	417	.nextdevice:
418	mov ebx, [esi]	418	mov ebx, [esi]
419	cmp al, byte[ebx + device.pci_bus]	419	cmp al, byte[ebx + device.pci_bus]
420	jne @f	420	jne @f
421	cmp ah, byte[ebx + device.pci_dev]	421	cmp ah, byte[ebx + device.pci_dev]
422	je .find_devicenum ; Device is already loaded, let's find it's device number	422	je .find_devicenum ; Device is already loaded, let's find it's device number
423	@@:	423	@@:
424	add esi, 4	424	add esi, 4
425	loop .nextdevice	425	loop .nextdevice
426		426
427	; This device doesnt have its own eth_device structure yet, lets create one	427	; This device doesnt have its own eth_device structure yet, lets create one
428		428
429	.firstdevice:	429	.firstdevice:
430	cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card	430	cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card
431	jae .fail	431	jae .fail
432		432
433	allocate_and_clear ebx, sizeof.device, .fail	433	allocate_and_clear ebx, sizeof.device, .fail
434		434
435	; Fill in the direct call addresses into the struct	435	; Fill in the direct call addresses into the struct
436		436
437	mov [ebx + device.reset], reset	437	mov [ebx + device.reset], reset
438	mov [ebx + device.transmit], transmit	438	mov [ebx + device.transmit], transmit
439	mov [ebx + device.unload], unload	439	mov [ebx + device.unload], unload
440	mov [ebx + device.name], my_service	440	mov [ebx + device.name], my_service
441		441
442	; save the pci bus and device numbers	442	; save the pci bus and device numbers
443		443
444	mov eax, [edx + IOCTL.input]	444	mov eax, [edx + IOCTL.input]
445	movzx ecx, byte[eax+1]	445	movzx ecx, byte[eax+1]
446	mov [ebx + device.pci_bus], ecx	446	mov [ebx + device.pci_bus], ecx
447	movzx ecx, byte[eax+2]	447	movzx ecx, byte[eax+2]
448	mov [ebx + device.pci_dev], ecx	448	mov [ebx + device.pci_dev], ecx
449		449
450	; Now, it's time to find the base io addres of the PCI device	450	; Now, it's time to find the base io addres of the PCI device
451		451
452	stdcall PCI_find_io, [ebx + device.pci_bus], [ebx + device.pci_dev]	452	stdcall PCI_find_io, [ebx + device.pci_bus], [ebx + device.pci_dev]
453	mov [ebx + device.io_addr], eax	453	mov [ebx + device.io_addr], eax
454		454
455	; We've found the io address, find IRQ now	455	; We've found the io address, find IRQ now
456		456
457	invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.interrupt_line	457	invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.interrupt_line
458	mov [ebx + device.irq_line], al	458	mov [ebx + device.irq_line], al
459		459
460	DEBUGF 1,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\	460	DEBUGF 1,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
461	[ebx + device.pci_dev]:1,[ebx + device.pci_bus]:1,[ebx + device.irq_line]:1,[ebx + device.io_addr]:4	461	[ebx + device.pci_dev]:1,[ebx + device.pci_bus]:1,[ebx + device.irq_line]:1,[ebx + device.io_addr]:4
462		462
463	; Ok, the eth_device structure is ready, let's probe the device	463	; Ok, the eth_device structure is ready, let's probe the device
464	; Because initialization fires IRQ, IRQ handler must be aware of this device	464	; Because initialization fires IRQ, IRQ handler must be aware of this device
465	mov eax, [devices] ; Add the device structure to our device list	465	mov eax, [devices] ; Add the device structure to our device list
466	mov [device_list+4*eax], ebx ; (IRQ handler uses this list to find device)	466	mov [device_list+4*eax], ebx ; (IRQ handler uses this list to find device)
467	inc [devices] ;	467	inc [devices] ;
468		468
469	call probe ; this function will output in eax	469	call probe ; this function will output in eax
470	test eax, eax	470	test eax, eax
471	jnz .destroy ; If an error occured, exit	471	jnz .destroy ; If an error occured, exit
472		472
473	mov [ebx + device.type], NET_TYPE_ETH	473	mov [ebx + device.type], NET_TYPE_ETH
474	invoke NetRegDev	474	invoke NetRegDev
475	cmp eax, -1	475	cmp eax, -1
476	je .destroy	476	je .destroy
477		477
478	ret	478	ret
479		479
480	; If the device was already loaded, find the device number and return it in eax	480	; If the device was already loaded, find the device number and return it in eax
481		481
482	.find_devicenum:	482	.find_devicenum:
483	DEBUGF 1,"Trying to find device number of already registered device\n"	483	DEBUGF 1,"Trying to find device number of already registered device\n"
484	invoke NetPtrToNum ; This kernel procedure converts a pointer to device struct in ebx	484	invoke NetPtrToNum ; This kernel procedure converts a pointer to device struct in ebx
485	; into a device number in edi	485	; into a device number in edi
486	mov eax, edi ; Application wants it in eax instead	486	mov eax, edi ; Application wants it in eax instead
487	DEBUGF 1,"Kernel says: %u\n", eax	487	DEBUGF 1,"Kernel says: %u\n", eax
488	ret	488	ret
489		489
490	; If an error occured, remove all allocated data and exit (returning -1 in eax)	490	; If an error occured, remove all allocated data and exit (returning -1 in eax)
491		491
492	.destroy:	492	.destroy:
493	; todo: reset device into virgin state	493	; todo: reset device into virgin state
494	add eax, NET_BUFF.data	494	add eax, NET_BUFF.data
495	dec [devices]	495	dec [devices]
496	.err:	496	.err:
497	DEBUGF 2,"Error, removing all data !\n"	497	DEBUGF 2,"Error, removing all data !\n"
498	invoke KernelFree, ebx	498	invoke KernelFree, ebx
499		499
500	.fail:	500	.fail:

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(root)/drivers/ethernet/pcnet32.asm @ 3545 – Rev 5522 → 5617