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3 | #include |
3 | #include |
4 | #include |
4 | #include |
5 | #include |
5 | #include |
6 | 6 | ||
Line -... | Line 7... | ||
- | 7 | LIST_HEAD(pci_root_buses); |
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- | 8 | ||
- | 9 | #define IO_SPACE_LIMIT 0xffff |
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- | 10 | ||
- | 11 | ||
- | 12 | ||
Line 7... | Line 13... | ||
7 | 13 | ||
Line -... | Line 14... | ||
- | 14 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
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- | 15 | ||
- | 16 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ |
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- | 17 | #define CARDBUS_RESERVE_BUSNR 3 |
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- | 18 | ||
- | 19 | static int pcibios_assign_all_busses(void) |
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- | 20 | { |
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- | 21 | return 0; |
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- | 22 | }; |
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- | 23 | ||
- | 24 | /** |
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- | 25 | * pci_ari_enabled - query ARI forwarding status |
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- | 26 | * @bus: the PCI bus |
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- | 27 | * |
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- | 28 | * Returns 1 if ARI forwarding is enabled, or 0 if not enabled; |
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- | 29 | */ |
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- | 30 | static inline int pci_ari_enabled(struct pci_bus *bus) |
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- | 31 | { |
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- | 32 | return bus->self && bus->self->ari_enabled; |
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- | 33 | } |
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- | 34 | ||
- | 35 | /* |
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- | 36 | * Translate the low bits of the PCI base |
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- | 37 | * to the resource type |
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- | 38 | */ |
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- | 39 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) |
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- | 40 | { |
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- | 41 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) |
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- | 42 | return IORESOURCE_IO; |
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- | 43 | ||
- | 44 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) |
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- | 45 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; |
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- | 46 | ||
- | 47 | return IORESOURCE_MEM; |
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- | 48 | } |
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- | 49 | ||
- | 50 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
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- | 51 | { |
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- | 52 | u64 size = mask & maxbase; /* Find the significant bits */ |
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- | 53 | if (!size) |
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- | 54 | return 0; |
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- | 55 | ||
- | 56 | /* Get the lowest of them to find the decode size, and |
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- | 57 | from that the extent. */ |
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- | 58 | size = (size & ~(size-1)) - 1; |
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- | 59 | ||
- | 60 | /* base == maxbase can be valid only if the BAR has |
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- | 61 | already been programmed with all 1s. */ |
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- | 62 | if (base == maxbase && ((base | size) & mask) != mask) |
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- | 63 | return 0; |
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- | 64 | ||
- | 65 | return size; |
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- | 66 | } |
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- | 67 | ||
- | 68 | static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar) |
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- | 69 | { |
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- | 70 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { |
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- | 71 | res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; |
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- | 72 | return pci_bar_io; |
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- | 73 | } |
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- | 74 | ||
- | 75 | res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
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- | 76 | ||
- | 77 | if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) |
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- | 78 | return pci_bar_mem64; |
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- | 79 | return pci_bar_mem32; |
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- | 80 | } |
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- | 81 | ||
- | 82 | ||
- | 83 | ||
- | 84 | /** |
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- | 85 | * pci_read_base - read a PCI BAR |
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- | 86 | * @dev: the PCI device |
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- | 87 | * @type: type of the BAR |
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- | 88 | * @res: resource buffer to be filled in |
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- | 89 | * @pos: BAR position in the config space |
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- | 90 | * |
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- | 91 | * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. |
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- | 92 | */ |
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- | 93 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
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- | 94 | struct resource *res, unsigned int pos) |
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- | 95 | { |
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- | 96 | u32 l, sz, mask; |
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- | 97 | u16 orig_cmd; |
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- | 98 | ||
- | 99 | mask = type ? PCI_ROM_ADDRESS_MASK : ~0; |
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- | 100 | ||
- | 101 | if (!dev->mmio_always_on) { |
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- | 102 | pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); |
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- | 103 | pci_write_config_word(dev, PCI_COMMAND, |
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- | 104 | orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); |
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- | 105 | } |
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- | 106 | ||
- | 107 | res->name = pci_name(dev); |
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- | 108 | ||
- | 109 | pci_read_config_dword(dev, pos, &l); |
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- | 110 | pci_write_config_dword(dev, pos, l | mask); |
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- | 111 | pci_read_config_dword(dev, pos, &sz); |
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- | 112 | pci_write_config_dword(dev, pos, l); |
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- | 113 | ||
- | 114 | if (!dev->mmio_always_on) |
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- | 115 | pci_write_config_word(dev, PCI_COMMAND, orig_cmd); |
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- | 116 | ||
- | 117 | /* |
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- | 118 | * All bits set in sz means the device isn't working properly. |
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- | 119 | * If the BAR isn't implemented, all bits must be 0. If it's a |
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- | 120 | * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit |
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- | 121 | * 1 must be clear. |
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- | 122 | */ |
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- | 123 | if (!sz || sz == 0xffffffff) |
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- | 124 | goto fail; |
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- | 125 | ||
- | 126 | /* |
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- | 127 | * I don't know how l can have all bits set. Copied from old code. |
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- | 128 | * Maybe it fixes a bug on some ancient platform. |
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- | 129 | */ |
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- | 130 | if (l == 0xffffffff) |
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- | 131 | l = 0; |
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- | 132 | ||
- | 133 | if (type == pci_bar_unknown) { |
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- | 134 | type = decode_bar(res, l); |
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- | 135 | res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; |
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- | 136 | if (type == pci_bar_io) { |
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- | 137 | l &= PCI_BASE_ADDRESS_IO_MASK; |
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- | 138 | mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT; |
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- | 139 | } else { |
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- | 140 | l &= PCI_BASE_ADDRESS_MEM_MASK; |
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- | 141 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; |
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- | 142 | } |
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- | 143 | } else { |
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- | 144 | res->flags |= (l & IORESOURCE_ROM_ENABLE); |
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- | 145 | l &= PCI_ROM_ADDRESS_MASK; |
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- | 146 | mask = (u32)PCI_ROM_ADDRESS_MASK; |
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- | 147 | } |
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- | 148 | ||
- | 149 | if (type == pci_bar_mem64) { |
|
- | 150 | u64 l64 = l; |
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- | 151 | u64 sz64 = sz; |
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- | 152 | u64 mask64 = mask | (u64)~0 << 32; |
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- | 153 | ||
- | 154 | pci_read_config_dword(dev, pos + 4, &l); |
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- | 155 | pci_write_config_dword(dev, pos + 4, ~0); |
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- | 156 | pci_read_config_dword(dev, pos + 4, &sz); |
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- | 157 | pci_write_config_dword(dev, pos + 4, l); |
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- | 158 | ||
- | 159 | l64 |= ((u64)l << 32); |
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- | 160 | sz64 |= ((u64)sz << 32); |
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- | 161 | ||
- | 162 | sz64 = pci_size(l64, sz64, mask64); |
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- | 163 | ||
- | 164 | if (!sz64) |
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- | 165 | goto fail; |
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- | 166 | ||
- | 167 | if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { |
|
- | 168 | dbgprintf("%s reg %x: can't handle 64-bit BAR\n", |
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- | 169 | __FUNCTION__, pos); |
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- | 170 | goto fail; |
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- | 171 | } |
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- | 172 | ||
- | 173 | res->flags |= IORESOURCE_MEM_64; |
|
- | 174 | if ((sizeof(resource_size_t) < 8) && l) { |
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- | 175 | /* Address above 32-bit boundary; disable the BAR */ |
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- | 176 | pci_write_config_dword(dev, pos, 0); |
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- | 177 | pci_write_config_dword(dev, pos + 4, 0); |
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- | 178 | res->start = 0; |
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- | 179 | res->end = sz64; |
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- | 180 | } else { |
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- | 181 | res->start = l64; |
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- | 182 | res->end = l64 + sz64; |
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- | 183 | dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res); |
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- | 184 | } |
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- | 185 | } else { |
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- | 186 | sz = pci_size(l, sz, mask); |
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- | 187 | ||
- | 188 | if (!sz) |
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- | 189 | goto fail; |
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- | 190 | ||
- | 191 | res->start = l; |
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- | 192 | res->end = l + sz; |
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- | 193 | ||
- | 194 | dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res); |
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- | 195 | } |
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- | 196 | ||
- | 197 | out: |
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- | 198 | return (type == pci_bar_mem64) ? 1 : 0; |
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- | 199 | fail: |
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- | 200 | res->flags = 0; |
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- | 201 | goto out; |
|
- | 202 | } |
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- | 203 | ||
- | 204 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
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- | 205 | { |
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- | 206 | unsigned int pos, reg; |
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- | 207 | ||
- | 208 | for (pos = 0; pos < howmany; pos++) { |
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- | 209 | struct resource *res = &dev->resource[pos]; |
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- | 210 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
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- | 211 | pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
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- | 212 | } |
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- | 213 | ||
- | 214 | if (rom) { |
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- | 215 | struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
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- | 216 | dev->rom_base_reg = rom; |
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- | 217 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
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- | 218 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE | |
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- | 219 | IORESOURCE_SIZEALIGN; |
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- | 220 | __pci_read_base(dev, pci_bar_mem32, res, rom); |
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- | 221 | } |
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- | 222 | } |
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- | 223 | ||
- | 224 | #if 0 |
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- | 225 | ||
- | 226 | void pci_read_bridge_bases(struct pci_bus *child) |
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- | 227 | { |
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- | 228 | struct pci_dev *dev = child->self; |
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- | 229 | struct resource *res; |
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- | 230 | int i; |
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- | 231 | ||
- | 232 | if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ |
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- | 233 | return; |
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- | 234 | ||
- | 235 | dbgprintf("PCI bridge to [bus %02x-%02x]%s\n", |
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- | 236 | child->secondary, child->subordinate, |
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- | 237 | dev->transparent ? " (subtractive decode)" : ""); |
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- | 238 | ||
- | 239 | pci_bus_remove_resources(child); |
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- | 240 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) |
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- | 241 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; |
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- | 242 | ||
- | 243 | pci_read_bridge_io(child); |
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- | 244 | pci_read_bridge_mmio(child); |
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- | 245 | pci_read_bridge_mmio_pref(child); |
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- | 246 | ||
- | 247 | if (dev->transparent) { |
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- | 248 | pci_bus_for_each_resource(child->parent, res, i) { |
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- | 249 | if (res) { |
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- | 250 | pci_bus_add_resource(child, res, |
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- | 251 | PCI_SUBTRACTIVE_DECODE); |
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- | 252 | dbgprintf(" bridge window %pR (subtractive decode)\n", res); |
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- | 253 | } |
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- | 254 | } |
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- | 255 | } |
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- | 256 | } |
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- | 257 | ||
- | 258 | #endif |
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- | 259 | ||
- | 260 | static struct pci_bus * pci_alloc_bus(void) |
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- | 261 | { |
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- | 262 | struct pci_bus *b; |
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- | 263 | ||
- | 264 | b = kzalloc(sizeof(*b), GFP_KERNEL); |
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- | 265 | if (b) { |
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- | 266 | INIT_LIST_HEAD(&b->node); |
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- | 267 | INIT_LIST_HEAD(&b->children); |
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- | 268 | INIT_LIST_HEAD(&b->devices); |
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- | 269 | INIT_LIST_HEAD(&b->slots); |
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- | 270 | INIT_LIST_HEAD(&b->resources); |
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- | 271 | // b->max_bus_speed = PCI_SPEED_UNKNOWN; |
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- | 272 | // b->cur_bus_speed = PCI_SPEED_UNKNOWN; |
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- | 273 | } |
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- | 274 | return b; |
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- | 275 | } |
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- | 276 | ||
- | 277 | ||
- | 278 | #if 0 |
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- | 279 | ||
- | 280 | static unsigned char pcix_bus_speed[] = { |
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- | 281 | PCI_SPEED_UNKNOWN, /* 0 */ |
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- | 282 | PCI_SPEED_66MHz_PCIX, /* 1 */ |
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- | 283 | PCI_SPEED_100MHz_PCIX, /* 2 */ |
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- | 284 | PCI_SPEED_133MHz_PCIX, /* 3 */ |
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- | 285 | PCI_SPEED_UNKNOWN, /* 4 */ |
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- | 286 | PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ |
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- | 287 | PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ |
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- | 288 | PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ |
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- | 289 | PCI_SPEED_UNKNOWN, /* 8 */ |
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- | 290 | PCI_SPEED_66MHz_PCIX_266, /* 9 */ |
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- | 291 | PCI_SPEED_100MHz_PCIX_266, /* A */ |
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- | 292 | PCI_SPEED_133MHz_PCIX_266, /* B */ |
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- | 293 | PCI_SPEED_UNKNOWN, /* C */ |
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- | 294 | PCI_SPEED_66MHz_PCIX_533, /* D */ |
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- | 295 | PCI_SPEED_100MHz_PCIX_533, /* E */ |
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- | 296 | PCI_SPEED_133MHz_PCIX_533 /* F */ |
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- | 297 | }; |
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- | 298 | ||
- | 299 | static unsigned char pcie_link_speed[] = { |
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- | 300 | PCI_SPEED_UNKNOWN, /* 0 */ |
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- | 301 | PCIE_SPEED_2_5GT, /* 1 */ |
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- | 302 | PCIE_SPEED_5_0GT, /* 2 */ |
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- | 303 | PCIE_SPEED_8_0GT, /* 3 */ |
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- | 304 | PCI_SPEED_UNKNOWN, /* 4 */ |
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- | 305 | PCI_SPEED_UNKNOWN, /* 5 */ |
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- | 306 | PCI_SPEED_UNKNOWN, /* 6 */ |
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- | 307 | PCI_SPEED_UNKNOWN, /* 7 */ |
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- | 308 | PCI_SPEED_UNKNOWN, /* 8 */ |
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- | 309 | PCI_SPEED_UNKNOWN, /* 9 */ |
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- | 310 | PCI_SPEED_UNKNOWN, /* A */ |
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- | 311 | PCI_SPEED_UNKNOWN, /* B */ |
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- | 312 | PCI_SPEED_UNKNOWN, /* C */ |
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- | 313 | PCI_SPEED_UNKNOWN, /* D */ |
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- | 314 | PCI_SPEED_UNKNOWN, /* E */ |
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- | 315 | PCI_SPEED_UNKNOWN /* F */ |
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- | 316 | }; |
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- | 317 | ||
- | 318 | ||
- | 319 | static void pci_set_bus_speed(struct pci_bus *bus) |
|
- | 320 | { |
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- | 321 | struct pci_dev *bridge = bus->self; |
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- | 322 | int pos; |
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- | 323 | ||
- | 324 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); |
|
- | 325 | if (!pos) |
|
- | 326 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); |
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- | 327 | if (pos) { |
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- | 328 | u32 agpstat, agpcmd; |
|
- | 329 | ||
- | 330 | pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); |
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- | 331 | bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); |
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- | 332 | ||
- | 333 | pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); |
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- | 334 | bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); |
|
- | 335 | } |
|
- | 336 | ||
- | 337 | pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); |
|
- | 338 | if (pos) { |
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- | 339 | u16 status; |
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- | 340 | enum pci_bus_speed max; |
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- | 341 | pci_read_config_word(bridge, pos + 2, &status); |
|
- | 342 | ||
- | 343 | if (status & 0x8000) { |
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- | 344 | max = PCI_SPEED_133MHz_PCIX_533; |
|
- | 345 | } else if (status & 0x4000) { |
|
- | 346 | max = PCI_SPEED_133MHz_PCIX_266; |
|
- | 347 | } else if (status & 0x0002) { |
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- | 348 | if (((status >> 12) & 0x3) == 2) { |
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- | 349 | max = PCI_SPEED_133MHz_PCIX_ECC; |
|
- | 350 | } else { |
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- | 351 | max = PCI_SPEED_133MHz_PCIX; |
|
- | 352 | } |
|
- | 353 | } else { |
|
- | 354 | max = PCI_SPEED_66MHz_PCIX; |
|
- | 355 | } |
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- | 356 | ||
- | 357 | bus->max_bus_speed = max; |
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- | 358 | bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf]; |
|
- | 359 | ||
- | 360 | return; |
|
- | 361 | } |
|
- | 362 | ||
- | 363 | pos = pci_find_capability(bridge, PCI_CAP_ID_EXP); |
|
- | 364 | if (pos) { |
|
- | 365 | u32 linkcap; |
|
- | 366 | u16 linksta; |
|
- | 367 | ||
- | 368 | pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap); |
|
- | 369 | bus->max_bus_speed = pcie_link_speed[linkcap & 0xf]; |
|
- | 370 | ||
- | 371 | pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta); |
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- | 372 | pcie_update_link_speed(bus, linksta); |
|
- | 373 | } |
|
- | 374 | } |
|
- | 375 | ||
- | 376 | #endif |
|
- | 377 | ||
- | 378 | ||
- | 379 | static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, |
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- | 380 | struct pci_dev *bridge, int busnr) |
|
- | 381 | { |
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- | 382 | struct pci_bus *child; |
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- | 383 | int i; |
|
- | 384 | ||
- | 385 | /* |
|
- | 386 | * Allocate a new bus, and inherit stuff from the parent.. |
|
- | 387 | */ |
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- | 388 | child = pci_alloc_bus(); |
|
- | 389 | if (!child) |
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- | 390 | return NULL; |
|
- | 391 | ||
- | 392 | child->parent = parent; |
|
- | 393 | child->ops = parent->ops; |
|
- | 394 | child->sysdata = parent->sysdata; |
|
- | 395 | child->bus_flags = parent->bus_flags; |
|
- | 396 | ||
- | 397 | /* initialize some portions of the bus device, but don't register it |
|
- | 398 | * now as the parent is not properly set up yet. This device will get |
|
- | 399 | * registered later in pci_bus_add_devices() |
|
- | 400 | */ |
|
- | 401 | // child->dev.class = &pcibus_class; |
|
- | 402 | // dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); |
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- | 403 | ||
- | 404 | /* |
|
- | 405 | * Set up the primary, secondary and subordinate |
|
- | 406 | * bus numbers. |
|
- | 407 | */ |
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- | 408 | child->number = child->secondary = busnr; |
|
- | 409 | child->primary = parent->secondary; |
|
- | 410 | child->subordinate = 0xff; |
|
- | 411 | ||
- | 412 | if (!bridge) |
|
- | 413 | return child; |
|
- | 414 | ||
- | 415 | child->self = bridge; |
|
- | 416 | // child->bridge = get_device(&bridge->dev); |
|
- | 417 | ||
- | 418 | // pci_set_bus_speed(child); |
|
- | 419 | ||
- | 420 | /* Set up default resource pointers and names.. */ |
|
- | 421 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
|
- | 422 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; |
|
- | 423 | child->resource[i]->name = child->name; |
|
- | 424 | } |
|
- | 425 | bridge->subordinate = child; |
|
- | 426 | ||
- | 427 | return child; |
|
- | 428 | } |
|
- | 429 | ||
- | 430 | struct pci_bus* pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) |
|
- | 431 | { |
|
- | 432 | struct pci_bus *child; |
|
- | 433 | ||
- | 434 | child = pci_alloc_child_bus(parent, dev, busnr); |
|
- | 435 | if (child) { |
|
- | 436 | // down_write(&pci_bus_sem); |
|
- | 437 | list_add_tail(&child->node, &parent->children); |
|
- | 438 | // up_write(&pci_bus_sem); |
|
- | 439 | } |
|
- | 440 | return child; |
|
- | 441 | } |
|
- | 442 | ||
- | 443 | ||
- | 444 | static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) |
|
- | 445 | { |
|
- | 446 | struct pci_bus *parent = child->parent; |
|
- | 447 | ||
- | 448 | /* Attempts to fix that up are really dangerous unless |
|
- | 449 | we're going to re-assign all bus numbers. */ |
|
- | 450 | if (!pcibios_assign_all_busses()) |
|
- | 451 | return; |
|
- | 452 | ||
- | 453 | while (parent->parent && parent->subordinate < max) { |
|
- | 454 | parent->subordinate = max; |
|
- | 455 | pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); |
|
- | 456 | parent = parent->parent; |
|
- | 457 | } |
|
- | 458 | } |
|
- | 459 | ||
- | 460 | ||
- | 461 | /* |
|
- | 462 | * If it's a bridge, configure it and scan the bus behind it. |
|
- | 463 | * For CardBus bridges, we don't scan behind as the devices will |
|
- | 464 | * be handled by the bridge driver itself. |
|
- | 465 | * |
|
- | 466 | * We need to process bridges in two passes -- first we scan those |
|
- | 467 | * already configured by the BIOS and after we are done with all of |
|
- | 468 | * them, we proceed to assigning numbers to the remaining buses in |
|
- | 469 | * order to avoid overlaps between old and new bus numbers. |
|
- | 470 | */ |
|
- | 471 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) |
|
- | 472 | { |
|
- | 473 | struct pci_bus *child; |
|
- | 474 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); |
|
- | 475 | u32 buses, i, j = 0; |
|
- | 476 | u16 bctl; |
|
- | 477 | u8 primary, secondary, subordinate; |
|
- | 478 | int broken = 0; |
|
- | 479 | ||
- | 480 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); |
|
- | 481 | primary = buses & 0xFF; |
|
- | 482 | secondary = (buses >> 8) & 0xFF; |
|
- | 483 | subordinate = (buses >> 16) & 0xFF; |
|
- | 484 | ||
- | 485 | dbgprintf("scanning [bus %02x-%02x] behind bridge, pass %d\n", |
|
- | 486 | secondary, subordinate, pass); |
|
- | 487 | ||
- | 488 | /* Check if setup is sensible at all */ |
|
- | 489 | if (!pass && |
|
- | 490 | (primary != bus->number || secondary <= bus->number)) { |
|
- | 491 | dbgprintf("bus configuration invalid, reconfiguring\n"); |
|
- | 492 | broken = 1; |
|
- | 493 | } |
|
- | 494 | ||
- | 495 | /* Disable MasterAbortMode during probing to avoid reporting |
|
- | 496 | of bus errors (in some architectures) */ |
|
- | 497 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); |
|
- | 498 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, |
|
- | 499 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); |
|
- | 500 | ||
- | 501 | if ((secondary || subordinate) && !pcibios_assign_all_busses() && |
|
- | 502 | !is_cardbus && !broken) { |
|
- | 503 | unsigned int cmax; |
|
- | 504 | /* |
|
- | 505 | * Bus already configured by firmware, process it in the first |
|
- | 506 | * pass and just note the configuration. |
|
- | 507 | */ |
|
- | 508 | if (pass) |
|
- | 509 | goto out; |
|
- | 510 | ||
- | 511 | /* |
|
- | 512 | * If we already got to this bus through a different bridge, |
|
- | 513 | * don't re-add it. This can happen with the i450NX chipset. |
|
- | 514 | * |
|
- | 515 | * However, we continue to descend down the hierarchy and |
|
- | 516 | * scan remaining child buses. |
|
- | 517 | */ |
|
- | 518 | child = pci_find_bus(pci_domain_nr(bus), secondary); |
|
- | 519 | if (!child) { |
|
- | 520 | child = pci_add_new_bus(bus, dev, secondary); |
|
- | 521 | if (!child) |
|
- | 522 | goto out; |
|
- | 523 | child->primary = primary; |
|
- | 524 | child->subordinate = subordinate; |
|
- | 525 | child->bridge_ctl = bctl; |
|
- | 526 | } |
|
- | 527 | ||
- | 528 | cmax = pci_scan_child_bus(child); |
|
- | 529 | if (cmax > max) |
|
- | 530 | max = cmax; |
|
- | 531 | if (child->subordinate > max) |
|
- | 532 | max = child->subordinate; |
|
- | 533 | } else { |
|
- | 534 | /* |
|
- | 535 | * We need to assign a number to this bus which we always |
|
- | 536 | * do in the second pass. |
|
- | 537 | */ |
|
- | 538 | if (!pass) { |
|
- | 539 | if (pcibios_assign_all_busses() || broken) |
|
- | 540 | /* Temporarily disable forwarding of the |
|
- | 541 | configuration cycles on all bridges in |
|
- | 542 | this bus segment to avoid possible |
|
- | 543 | conflicts in the second pass between two |
|
- | 544 | bridges programmed with overlapping |
|
- | 545 | bus ranges. */ |
|
- | 546 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, |
|
- | 547 | buses & ~0xffffff); |
|
- | 548 | goto out; |
|
- | 549 | } |
|
- | 550 | ||
- | 551 | /* Clear errors */ |
|
- | 552 | pci_write_config_word(dev, PCI_STATUS, 0xffff); |
|
- | 553 | ||
- | 554 | /* Prevent assigning a bus number that already exists. |
|
- | 555 | * This can happen when a bridge is hot-plugged */ |
|
- | 556 | if (pci_find_bus(pci_domain_nr(bus), max+1)) |
|
- | 557 | goto out; |
|
- | 558 | child = pci_add_new_bus(bus, dev, ++max); |
|
- | 559 | buses = (buses & 0xff000000) |
|
- | 560 | | ((unsigned int)(child->primary) << 0) |
|
- | 561 | | ((unsigned int)(child->secondary) << 8) |
|
- | 562 | | ((unsigned int)(child->subordinate) << 16); |
|
- | 563 | ||
- | 564 | /* |
|
- | 565 | * yenta.c forces a secondary latency timer of 176. |
|
- | 566 | * Copy that behaviour here. |
|
- | 567 | */ |
|
- | 568 | if (is_cardbus) { |
|
- | 569 | buses &= ~0xff000000; |
|
- | 570 | buses |= CARDBUS_LATENCY_TIMER << 24; |
|
- | 571 | } |
|
- | 572 | ||
- | 573 | /* |
|
- | 574 | * We need to blast all three values with a single write. |
|
- | 575 | */ |
|
- | 576 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); |
|
- | 577 | ||
- | 578 | if (!is_cardbus) { |
|
- | 579 | child->bridge_ctl = bctl; |
|
- | 580 | /* |
|
- | 581 | * Adjust subordinate busnr in parent buses. |
|
- | 582 | * We do this before scanning for children because |
|
- | 583 | * some devices may not be detected if the bios |
|
- | 584 | * was lazy. |
|
- | 585 | */ |
|
- | 586 | pci_fixup_parent_subordinate_busnr(child, max); |
|
- | 587 | /* Now we can scan all subordinate buses... */ |
|
- | 588 | max = pci_scan_child_bus(child); |
|
- | 589 | /* |
|
- | 590 | * now fix it up again since we have found |
|
- | 591 | * the real value of max. |
|
- | 592 | */ |
|
- | 593 | pci_fixup_parent_subordinate_busnr(child, max); |
|
- | 594 | } else { |
|
- | 595 | /* |
|
- | 596 | * For CardBus bridges, we leave 4 bus numbers |
|
- | 597 | * as cards with a PCI-to-PCI bridge can be |
|
- | 598 | * inserted later. |
|
- | 599 | */ |
|
- | 600 | for (i=0; i |
|
- | 601 | struct pci_bus *parent = bus; |
|
- | 602 | if (pci_find_bus(pci_domain_nr(bus), |
|
- | 603 | max+i+1)) |
|
- | 604 | break; |
|
- | 605 | while (parent->parent) { |
|
- | 606 | if ((!pcibios_assign_all_busses()) && |
|
- | 607 | (parent->subordinate > max) && |
|
- | 608 | (parent->subordinate <= max+i)) { |
|
- | 609 | j = 1; |
|
- | 610 | } |
|
- | 611 | parent = parent->parent; |
|
- | 612 | } |
|
- | 613 | if (j) { |
|
- | 614 | /* |
|
- | 615 | * Often, there are two cardbus bridges |
|
- | 616 | * -- try to leave one valid bus number |
|
- | 617 | * for each one. |
|
- | 618 | */ |
|
- | 619 | i /= 2; |
|
- | 620 | break; |
|
- | 621 | } |
|
- | 622 | } |
|
- | 623 | max += i; |
|
- | 624 | pci_fixup_parent_subordinate_busnr(child, max); |
|
- | 625 | } |
|
- | 626 | /* |
|
- | 627 | * Set the subordinate bus number to its real value. |
|
- | 628 | */ |
|
- | 629 | child->subordinate = max; |
|
- | 630 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); |
|
- | 631 | } |
|
- | 632 | ||
- | 633 | vsprintf(child->name, |
|
- | 634 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), |
|
- | 635 | pci_domain_nr(bus), child->number); |
|
- | 636 | ||
- | 637 | /* Has only triggered on CardBus, fixup is in yenta_socket */ |
|
- | 638 | while (bus->parent) { |
|
- | 639 | if ((child->subordinate > bus->subordinate) || |
|
- | 640 | (child->number > bus->subordinate) || |
|
- | 641 | (child->number < bus->number) || |
|
- | 642 | (child->subordinate < bus->number)) { |
|
- | 643 | dbgprintf("[bus %02x-%02x] %s " |
|
- | 644 | "hidden behind%s bridge %s [bus %02x-%02x]\n", |
|
- | 645 | child->number, child->subordinate, |
|
- | 646 | (bus->number > child->subordinate && |
|
- | 647 | bus->subordinate < child->number) ? |
|
- | 648 | "wholly" : "partially", |
|
- | 649 | bus->self->transparent ? " transparent" : "", |
|
- | 650 | "FIX BRIDGE NAME", |
|
- | 651 | bus->number, bus->subordinate); |
|
- | 652 | } |
|
- | 653 | bus = bus->parent; |
|
- | 654 | } |
|
- | 655 | ||
- | 656 | out: |
|
- | 657 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); |
|
- | 658 | ||
- | 659 | return max; |
|
- | 660 | } |
|
- | 661 | ||
- | 662 | void set_pcie_port_type(struct pci_dev *pdev) |
|
- | 663 | { |
|
- | 664 | int pos; |
|
- | 665 | u16 reg16; |
|
- | 666 | ||
- | 667 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
|
- | 668 | if (!pos) |
|
- | 669 | return; |
|
- | 670 | pdev->is_pcie = 1; |
|
- | 671 | pdev->pcie_cap = pos; |
|
- | 672 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); |
|
- | 673 | pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; |
|
- | 674 | } |
|
- | 675 | ||
- | 676 | void set_pcie_hotplug_bridge(struct pci_dev *pdev) |
|
- | 677 | { |
|
- | 678 | int pos; |
|
- | 679 | u16 reg16; |
|
- | 680 | u32 reg32; |
|
- | 681 | ||
- | 682 | pos = pci_pcie_cap(pdev); |
|
- | 683 | if (!pos) |
|
- | 684 | return; |
|
- | 685 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); |
|
- | 686 | if (!(reg16 & PCI_EXP_FLAGS_SLOT)) |
|
- | 687 | return; |
|
- | 688 | pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32); |
|
- | 689 | if (reg32 & PCI_EXP_SLTCAP_HPC) |
|
- | 690 | pdev->is_hotplug_bridge = 1; |
|
- | 691 | } |
|
- | 692 | ||
- | 693 | /* |
|
- | 694 | * Read interrupt line and base address registers. |
|
- | 695 | * The architecture-dependent code can tweak these, of course. |
|
- | 696 | */ |
|
- | 697 | static void pci_read_irq(struct pci_dev *dev) |
|
- | 698 | { |
|
- | 699 | unsigned char irq; |
|
- | 700 | ||
- | 701 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); |
|
- | 702 | dev->pin = irq; |
|
- | 703 | if (irq) |
|
- | 704 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
|
- | 705 | dev->irq = irq; |
|
- | 706 | } |
|
8 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
707 | |
9 | 708 | ||
10 | /** |
709 | /** |
11 | * pci_setup_device - fill in class and map information of a device |
710 | * pci_setup_device - fill in class and map information of a device |
12 | * @dev: the device structure to fill |
711 | * @dev: the device structure to fill |
Line 174... | Line 873... | ||
174 | return NULL; |
873 | return NULL; |
175 | 874 | ||
Line 176... | Line 875... | ||
176 | /* some broken boards return 0 or ~0 if a slot is empty: */ |
875 | /* some broken boards return 0 or ~0 if a slot is empty: */ |
177 | if (l == 0xffffffff || l == 0x00000000 || |
876 | if (l == 0xffffffff || l == 0x00000000 || |
178 | l == 0x0000ffff || l == 0xffff0000) |
877 | l == 0x0000ffff || l == 0xffff0000 || |
- | 878 | (l & 0xffff0000) == 0xffff0000 || |
|
- | 879 | (l & 0x0000ffff) == 0x0000ffff ) |
|
179 | return NULL; |
880 | return NULL; |
Line 180... | Line 881... | ||
180 | 881 | ||
181 | /* Configuration request Retry Status */ |
882 | /* Configuration request Retry Status */ |
182 | while (l == 0xffff0001) { |
883 | while (l == 0xffff0001) { |
183 | delay(timeout/10); |
884 | delay(timeout/10); |
184 | timeout *= 2; |
885 | timeout *= 2; |
185 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) |
886 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) |
186 | return NULL; |
887 | return NULL; |
187 | /* Card hasn't responded in 60 seconds? Must be stuck. */ |
888 | /* Card hasn't responded in 60 seconds? Must be stuck. */ |
188 | if (delay > 60 * 1000) { |
889 | if (timeout > 60 * 1000) { |
189 | printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " |
890 | printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " |
190 | "responding\n", pci_domain_nr(bus), |
891 | "responding\n", pci_domain_nr(bus), |
191 | bus->number, PCI_SLOT(devfn), |
892 | bus->number, PCI_SLOT(devfn), |
192 | PCI_FUNC(devfn)); |
893 | PCI_FUNC(devfn)); |
Line 210... | Line 911... | ||
210 | 911 | ||
Line 211... | Line 912... | ||
211 | return dev; |
912 | return dev; |
212 | } |
913 | } |
Line -... | Line 914... | ||
- | 914 | ||
- | 915 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
|
- | 916 | { |
|
- | 917 | // device_initialize(&dev->dev); |
|
- | 918 | // dev->dev.release = pci_release_dev; |
|
- | 919 | // pci_dev_get(dev); |
|
- | 920 | ||
- | 921 | // dev->dev.dma_mask = &dev->dma_mask; |
|
- | 922 | // dev->dev.dma_parms = &dev->dma_parms; |
|
- | 923 | // dev->dev.coherent_dma_mask = 0xffffffffull; |
|
- | 924 | ||
- | 925 | // pci_set_dma_max_seg_size(dev, 65536); |
|
- | 926 | // pci_set_dma_seg_boundary(dev, 0xffffffff); |
|
- | 927 | ||
- | 928 | /* Fix up broken headers */ |
|
- | 929 | // pci_fixup_device(pci_fixup_header, dev); |
|
- | 930 | ||
- | 931 | /* Clear the state_saved flag. */ |
|
- | 932 | dev->state_saved = false; |
|
- | 933 | ||
- | 934 | /* Initialize various capabilities */ |
|
- | 935 | // pci_init_capabilities(dev); |
|
- | 936 | ||
- | 937 | /* |
|
- | 938 | * Add the device to our list of discovered devices |
|
- | 939 | * and the bus list for fixup functions, etc. |
|
- | 940 | */ |
|
- | 941 | // down_write(&pci_bus_sem); |
|
- | 942 | list_add_tail(&dev->bus_list, &bus->devices); |
|
- | 943 | // up_write(&pci_bus_sem); |
|
Line 213... | Line 944... | ||
213 | 944 | } |
|
214 | 945 | ||
215 | struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn) |
946 | struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn) |
Line 310... | Line 1041... | ||
310 | } |
1041 | } |
311 | } |
1042 | } |
312 | 1043 | ||
Line 313... | Line 1044... | ||
313 | /* only one slot has pcie device */ |
1044 | /* only one slot has pcie device */ |
314 | if (bus->self && nr) |
1045 | // if (bus->self && nr) |
315 | pcie_aspm_init_link_state(bus->self); |
1046 | // pcie_aspm_init_link_state(bus->self); |
Line 316... | Line 1047... | ||
316 | 1047 | ||
317 | return nr; |
1048 | return nr; |
Line 337... | Line 1068... | ||
337 | * all PCI-to-PCI bridges on this bus. |
1068 | * all PCI-to-PCI bridges on this bus. |
338 | */ |
1069 | */ |
339 | if (!bus->is_added) { |
1070 | if (!bus->is_added) { |
340 | dbgprintf("fixups for bus\n"); |
1071 | dbgprintf("fixups for bus\n"); |
341 | pcibios_fixup_bus(bus); |
1072 | // pcibios_fixup_bus(bus); |
342 | if (pci_is_root_bus(bus)) |
1073 | if (pci_is_root_bus(bus)) |
343 | bus->is_added = 1; |
1074 | bus->is_added = 1; |
344 | } |
1075 | } |
345 | 1076 | ||
Line 346... | Line 1077... | ||
346 | for (pass=0; pass < 2; pass++) |
1077 | for (pass=0; pass < 2; pass++) |
Line 415... | Line 1146... | ||
415 | return PCI_CFG_SPACE_SIZE; |
1146 | return PCI_CFG_SPACE_SIZE; |
416 | }>>=> |
1147 | } |
417 | 1148 | ||
Line -... | Line 1149... | ||
- | 1149 | ||
- | 1150 | ||
- | 1151 | struct pci_bus * pci_create_bus(int bus, struct pci_ops *ops, void *sysdata) |
|
- | 1152 | { |
|
- | 1153 | int error; |
|
- | 1154 | struct pci_bus *b, *b2; |
|
- | 1155 | ||
- | 1156 | b = pci_alloc_bus(); |
|
- | 1157 | if (!b) |
|
- | 1158 | return NULL; |
|
- | 1159 | ||
- | 1160 | b->sysdata = sysdata; |
|
- | 1161 | b->ops = ops; |
|
- | 1162 | ||
- | 1163 | b2 = pci_find_bus(pci_domain_nr(b), bus); |
|
- | 1164 | if (b2) { |
|
- | 1165 | /* If we already got to this bus through a different bridge, ignore it */ |
|
- | 1166 | dbgprintf("bus already known\n"); |
|
- | 1167 | goto err_out; |
|
- | 1168 | } |
|
- | 1169 | ||
- | 1170 | // down_write(&pci_bus_sem); |
|
- | 1171 | list_add_tail(&b->node, &pci_root_buses); |
|
- | 1172 | // up_write(&pci_bus_sem); |
|
- | 1173 | ||
- | 1174 | b->number = b->secondary = bus; |
|
- | 1175 | b->resource[0] = &ioport_resource; |
|
- | 1176 | b->resource[1] = &iomem_resource; |
|
- | 1177 | ||
- | 1178 | return b; |
|
- | 1179 | ||
- | 1180 | err_out: |
|
- | 1181 | kfree(b); |
|
- | 1182 | return NULL; |
|
- | 1183 | }>>=>>>>=>><>><>><>><>=>>>>><>>>>><>><>><> |