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Rev 2187 Rev 9499
Line 16... Line 16...
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#define CARDBUS_LATENCY_TIMER   176 /* secondary latency timer */
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#define CARDBUS_LATENCY_TIMER   176 /* secondary latency timer */
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#define CARDBUS_RESERVE_BUSNR   3
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#define CARDBUS_RESERVE_BUSNR   3
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static int pcibios_assign_all_busses(void)
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int pcibios_assign_all_busses(void)
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{
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{
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    return 0;
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    return 0;
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};
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/**
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 * pci_ari_enabled - query ARI forwarding status
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 * @bus: the PCI bus
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 *
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 * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
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 */
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static inline int pci_ari_enabled(struct pci_bus *bus)
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{
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    return bus->self && bus->self->ari_enabled;
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}
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};
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/*
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/*
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 * Translate the low bits of the PCI base
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 * Translate the low bits of the PCI base
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 * to the resource type
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 * to the resource type
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        child->subordinate = max;
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        child->subordinate = max;
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        pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
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        pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
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    }
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    }
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    vsprintf(child->name,
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    sprintf(child->name,
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        (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
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        (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
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        pci_domain_nr(bus), child->number);
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        pci_domain_nr(bus), child->number);
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    /* Has only triggered on CardBus, fixup is in yenta_socket */
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    /* Has only triggered on CardBus, fixup is in yenta_socket */
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    pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
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    pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
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    if (!pos)
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    if (!pos)
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        return;
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        return;
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    pdev->is_pcie = 1;
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    //pdev->is_pcie = 1;
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    pdev->pcie_cap = pos;
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    pdev->pcie_cap = pos;
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    pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
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    pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
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    pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
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    pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
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}
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}
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    for (devfn = 0; devfn < 0x100; devfn += 8)
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    for (devfn = 0; devfn < 0x100; devfn += 8)
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        pci_scan_slot(bus, devfn);
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        pci_scan_slot(bus, devfn);
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    /* Reserve buses for SR-IOV capability. */
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    /* Reserve buses for SR-IOV capability. */
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    max += pci_iov_bus_range(bus);
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    //max += pci_iov_bus_range(bus);
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    /*
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    /*
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     * After performing arch-dependent fixup of the bus, look behind
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     * After performing arch-dependent fixup of the bus, look behind
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     * all PCI-to-PCI bridges on this bus.
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     * all PCI-to-PCI bridges on this bus.